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31. 发明授权

US5007028A Multiport memory with improved timing of word line selection 失效
标题翻译：具有改进字线选择时序的多端口存储器
公开(公告)号：US5007028A
公开(公告)日：1991-04-09
申请号：US552851
申请日：1990-07-16
申请人： Shigeo Ohshima , Haruki Toda , Tatsuo Ikawa
发明人： Shigeo Ohshima , Haruki Toda , Tatsuo Ikawa
IPC分类号： G11C11/401 , G11C7/10 , G11C11/407
CPC分类号： G11C7/1075
摘要： This invention provides a multiport memory including a storage section A having bit lines BL and BL, a word line WL, a data transfer gate .phi.DT, and a dynamic memory cell Cs, and a serial port B having a serial access function in a column direction of the storage section, wherein the memory includes a circuit for disabling a word line signal WL for selecting one word line under the conditions that a row address strobe signal RAS is raised in a transfer cycle in which data held by the memory cell is transferred to the serial port, and that the data transfer to the serial port is completed by the data transfer gate .phi.DT.

32. 发明授权

US4794569A Semiconductor memory having a barrier transistor between a bit line and a sensing amplifier 失效
标题翻译：具有在位线和感测放大器之间的势垒晶体管的半导体存储器
公开(公告)号：US4794569A
公开(公告)日：1988-12-27
申请号：US863190
申请日：1986-05-14
申请人： Hiroshi Sahara , Haruki Toda , Shigeo Ohshima
发明人： Hiroshi Sahara , Haruki Toda , Shigeo Ohshima
IPC分类号： G11C11/409 , G11C11/4094 , G11C11/4096 , G11C7/00
CPC分类号： G11C11/4096 , G11C11/4094
摘要： In this invention, in a sensing circuit of a dynamic memory, barrier transistors are provided between the bit lines and the sensing amplifier. A circuit is provided that, on sensing and on data transfer, changes the gate potential of the barrier transistors so that during the sensing operation the barrier transistors are temporarily turned OFF, so that sensing can be carried out with high sensitivity, as the sensing system is not affected by the parasitic capacitance of the bit lines, while, on data transfer to the input/output lines, the gate potential of the barrier transistors is raised to a level greater than a value reached by adding the threshold value of the MOS transistors to the power source voltage, so that the conductance of the barrier transistors is increased, thereby speeding up the presensing of the input/output lines in the sensing circuit.
摘要翻译：在本发明中，在动态存储器的感测电路中，在位线和感测放大器之间设置有阻挡晶体管。提供了一种电路，其在感测和数据传输时改变势垒晶体管的栅极电位，使得在感测操作期间，阻挡晶体管暂时断开，使得可以以高灵敏度进行感测，作为感测系统不受位线的寄生电容的影响，而在向输入/输出线路传输数据时，势垒晶体管的栅极电位升高到大于通过将MOS晶体管的阈值相加而达到的值以使得阻挡晶体管的电导增加，从而加速感测电路中的输入/输出线的预置。

33. 发明授权

US08179730B2 Semiconductor device and semiconductor memory tester 有权
标题翻译：半导体器件和半导体存储器测试仪
公开(公告)号：US08179730B2
公开(公告)日：2012-05-15
申请号：US12963247
申请日：2010-12-08
申请人： Yuui Shimizu , Shigeo Ohshima , Mie Matsuo
发明人： Yuui Shimizu , Shigeo Ohshima , Mie Matsuo
IPC分类号： G11C5/14 , G11C5/02 , G11C5/06 , H01L23/02 , H01L23/12 , H01L23/52
CPC分类号： G11C5/145 , G11C5/04 , G11C5/066 , G11C5/143 , G11C16/30 , G11C29/12005 , G11C29/48 , G11C29/56 , G11C2029/5602 , H01L25/0657 , H01L25/18 , H01L2224/48091 , H01L2224/48145 , H01L2224/48147 , H01L2225/06506 , H01L2225/06527 , H01L2225/06541 , H01L2225/06562 , H01L2924/01019 , H01L2924/19041 , H01L2924/00014 , H01L2924/00012
摘要： A semiconductor device, a semiconductor memory tester, and a multi-chip package are provided. The semiconductor device includes a plurality of nonvolatile semiconductor memories; a boosting circuit which generates a boosted voltage for operating the plurality of nonvolatile semiconductor memories; and a boosting circuit controller which controls the operation of the boosting circuit to generate the boosted voltage on the basis of an operation sequence of the plurality of nonvolatile semiconductor memories.
摘要翻译：提供半导体器件，半导体存储器测试器和多芯片封装。半导体器件包括多个非易失性半导体存储器; 升压电路，其产生用于操作所述多个非易失性半导体存储器的升压电压; 以及升压电路控制器，其基于所述多个非易失性半导体存储器的操作顺序来控制所述升压电路的操作以产生所述升压电压。

34. 发明申请

US20110074494A1 SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MEMORY TESTER 有权
标题翻译：半导体器件和半导体存储器测试仪
公开(公告)号：US20110074494A1
公开(公告)日：2011-03-31
申请号：US12963247
申请日：2010-12-08
申请人： Yuui Shimizu , Shigeo Ohshima , Mie Matsuo
发明人： Yuui Shimizu , Shigeo Ohshima , Mie Matsuo
IPC分类号： G05F1/10
CPC分类号： G11C5/145 , G11C5/04 , G11C5/066 , G11C5/143 , G11C16/30 , G11C29/12005 , G11C29/48 , G11C29/56 , G11C2029/5602 , H01L25/0657 , H01L25/18 , H01L2224/48091 , H01L2224/48145 , H01L2224/48147 , H01L2225/06506 , H01L2225/06527 , H01L2225/06541 , H01L2225/06562 , H01L2924/01019 , H01L2924/19041 , H01L2924/00014 , H01L2924/00012
摘要： A semiconductor device, a semiconductor memory tester, and a multi-chip package are provided. The semiconductor device includes a plurality of nonvolatile semiconductor memories; a boosting circuit which generates a boosted voltage for operating the plurality of nonvolatile semiconductor memories; and a boosting circuit controller which controls the operation of the boosting circuit to generate the boosted voltage on the basis of an operation sequence of the plurality of nonvolatile semiconductor memories.
摘要翻译：提供半导体器件，半导体存储器测试器和多芯片封装。半导体器件包括多个非易失性半导体存储器; 升压电路，其产生用于操作所述多个非易失性半导体存储器的升压电压; 以及升压电路控制器，其基于所述多个非易失性半导体存储器的操作顺序来控制所述升压电路的操作以产生所述升压电压。

35. 发明授权

US07911823B2 Method of programming a non-volatile memory device 有权
标题翻译：编程非易失性存储器件的方法
公开(公告)号：US07911823B2
公开(公告)日：2011-03-22
申请号：US12123827
申请日：2008-05-20
申请人： Takuya Futatsuyama , Koji Hosono , Toshiaki Edahiro , Naoya Tokiwa , Kazushige Kanda , Shigeo Ohshima
发明人： Takuya Futatsuyama , Koji Hosono , Toshiaki Edahiro , Naoya Tokiwa , Kazushige Kanda , Shigeo Ohshima
IPC分类号： G11C11/00 , G11C7/00 , G11C7/02 , G11C7/12 , G11C8/08
CPC分类号： G11C11/36
摘要： A method of programming a non-volatile memory device with memory cells formed of variable resistance elements and disposed between word lines and bit lines, includes: previously charging a selected word line and a selected bit line together with a non-selected word line and a non-selected bit line up to a certain voltage; and further charging the selected word line and the non-selected bit line up to a program voltage higher than the certain voltage and a program-block voltage, respectively, and simultaneously discharging the selected bit line.
摘要翻译：一种使用由可变电阻元件形成并且设置在字线和位线之间的存储单元来编程非易失性存储器件的方法包括：预先对所选择的字线和所选择的位线以及未选择的字线和非选择位线达到一定电压; 并且进一步对所选字线和未选择的位线进行充电，直到分别高于特定电压和编程块电压的编程电压，并同时对所选择的位线进行放电。

36. 发明授权

US07869240B2 Semiconductor device and semiconductor memory tester 失效
标题翻译：半导体器件和半导体存储测试仪
公开(公告)号：US07869240B2
公开(公告)日：2011-01-11
申请号：US12142278
申请日：2008-06-19
申请人： Yuui Shimizu , Shigeo Ohshima , Mie Matsuo
发明人： Yuui Shimizu , Shigeo Ohshima , Mie Matsuo
IPC分类号： G11C5/02 , G11C5/06 , H01L23/52
CPC分类号： G11C5/145 , G11C5/04 , G11C5/066 , G11C5/143 , G11C16/30 , G11C29/12005 , G11C29/48 , G11C29/56 , G11C2029/5602 , H01L25/0657 , H01L25/18 , H01L2224/48091 , H01L2224/48145 , H01L2224/48147 , H01L2225/06506 , H01L2225/06527 , H01L2225/06541 , H01L2225/06562 , H01L2924/01019 , H01L2924/19041 , H01L2924/00014 , H01L2924/00012
摘要： A semiconductor device, a semiconductor memory tester, and a multi-chip package are provided. The semiconductor device includes a plurality of nonvolatile semiconductor memories; a boosting circuit which generates a boosted voltage for operating the plurality of nonvolatile semiconductor memories; and a boosting circuit controller which controls the operation of the boosting circuit to generate the boosted voltage on the basis of an operation sequence of the plurality of nonvolatile semiconductor memories.
摘要翻译：提供半导体器件，半导体存储器测试器和多芯片封装。半导体器件包括多个非易失性半导体存储器; 升压电路，其产生用于操作所述多个非易失性半导体存储器的升压电压; 以及升压电路控制器，其基于所述多个非易失性半导体存储器的操作顺序来控制所述升压电路的操作以产生所述升压电压。

37. 发明授权

US07823105B2 Layout data generation equipment of semiconductor integrated circuit, data generation method and manufacturing method of semiconductor device 失效
标题翻译：半导体集成电路的布局数据生成设备，半导体器件的数据生成方法和制造方法
公开(公告)号：US07823105B2
公开(公告)日：2010-10-26
申请号：US11945537
申请日：2007-11-27
申请人： Shigeo Ohshima , Kiminobu Suzuki , Kazuhiro Yamada , Takamichi Arizono
发明人： Shigeo Ohshima , Kiminobu Suzuki , Kazuhiro Yamada , Takamichi Arizono
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A layout-data generation equipment includes a logic circuit designing section which designs a logic circuit based on information of the specifications of a semiconductor integrated circuit, a layout-data generation section which creates layout-data based on the logic circuit, a resistance information extraction section which extracts resistance information of a wire from the layout-data, a circuit simulation execution section which executes a circuit simulation, an identification section of current direction which identifies a direction of a current in the wire based on the resistance information of a wire and an execution result of the circuit simulation, a verification section which verifies whether layout-data of the wire breaks a design rule, the design rule being extracted from the information of the specifications of a semiconductor integrated circuit and the verification section generates this verification result, and a data output section which outputs the layout-data.
摘要翻译：布局数据生成装置包括逻辑电路设计部，其基于半导体集成电路的规格信息设计逻辑电路，基于逻辑电路生成布局数据的布局数据生成部，电阻信息提取从布局数据中提取线的电阻信息的部分，执行电路仿真的电路仿真执行部，基于电线的电阻信息识别线中的电流方向的电流方向的识别部，以及电路仿真的执行结果，验证电线的布局数据是否断开设计规则的验证部分，从半导体集成电路的规格信息中提取设计规则，并且验证部分生成该验证结果，以及输出布局数据的数据输出部。

38. 发明授权

US07817457B2 Non-volatile memory device 有权
标题翻译：非易失性存储器件
公开(公告)号：US07817457B2
公开(公告)日：2010-10-19
申请号：US12132972
申请日：2008-06-04
申请人： Naoya Tokiwa , Kazushige Kanda , Toshiaki Edahiro , Koji Hosono , Takuya Futatsuyama , Shigeo Ohshima
发明人： Naoya Tokiwa , Kazushige Kanda , Toshiaki Edahiro , Koji Hosono , Takuya Futatsuyama , Shigeo Ohshima
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C13/0007 , G11C13/0097 , G11C2013/0092 , G11C2213/32 , G11C2213/72
摘要： According to one embodiment, a nonvolatile memory device includes: a memory cell array including memory cells each having a variable resistance element for nonvolatilely storing data identified by an electrically rewritable resistance value; a first data latch storing write and erase data to be written on a given group of memory cells of the memory cell array for a write and erase operation; and a second data latch storing reference data for performing a compensation operation of the given group to compensate write and erase disturbance accompanied by the write or erase operation.
摘要翻译：根据一个实施例，非易失性存储器件包括：存储单元阵列，其包括各自具有用于非易失性地存储由电可重写电阻值识别的数据的可变电阻元件的存储单元; 存储要写入存储单元阵列的给定组的存储单元的用于写入和擦除操作的写入和擦除数据的第一数据锁存器; 以及第二数据锁存器，存储用于执行给定组的补偿操作以补偿伴随着写入或擦除操作的写入和擦除干扰的参考数据。

39. 发明申请

US20090052227A1 NON-VOLATILE MEMORY DEVICE AND METHOD FOR WRITING DATA THERETO 有权
标题翻译：非易失性存储器件及其数据写入方法
公开(公告)号：US20090052227A1
公开(公告)日：2009-02-26
申请号：US12118064
申请日：2008-05-09
申请人： Toshiaki Edahiro , Kazushige Kanda , Naoya Tokiwa , Takuya Futatsuyama , Koji Hosono , Shigeo Ohshima
发明人： Toshiaki Edahiro , Kazushige Kanda , Naoya Tokiwa , Takuya Futatsuyama , Koji Hosono , Shigeo Ohshima
IPC分类号： G11C11/00 , G11C7/00 , G11C7/06
CPC分类号： H01L27/101 , G11C13/0007 , G11C13/004 , G11C13/0069 , G11C2013/0054 , G11C2013/009 , G11C2213/32 , G11C2213/72
摘要： The present invention provides a method for writing data to a non-volatile memory device having first wirings and second wirings intersecting one another and memory cells arranged at each intersection therebetween, each of the memory cells having a variable resistive element and a rectifying element connected in series. According to the method, the second wirings are charged to a certain voltage not less than a rectifying-element threshold value, prior to a rise in a selected first wiring. Then, a selected first wiring is charged to a voltage required for writing or erasing, after which a selected second wiring is discharged.
摘要翻译：本发明提供一种将数据写入非易失性存储器件的方法，该非易失性存储器件具有彼此相交的第一布线和第二布线以及布置在其间的每个交叉处的存储单元，每个存储单元具有可变电阻元件和整流元件系列。根据该方法，在所选择的第一布线中升高之前，将第二布线充电至不小于整流元件阈值的一定电压。然后，将所选择的第一布线充电到写入或擦除所需的电压，之后放电所选择的第二布线。

40. 发明申请

US20080151640A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 有权
标题翻译：半导体集成电路设备
公开(公告)号：US20080151640A1
公开(公告)日：2008-06-26
申请号：US11953319
申请日：2007-12-10
申请人： Eiichi MAKINO , Shigeo Ohshima
发明人： Eiichi MAKINO , Shigeo Ohshima
IPC分类号： G11C16/06
CPC分类号： G11C16/26 , G11C7/1051 , G11C7/1057 , G11C7/1063 , G11C2207/105
摘要： This disclosure concerns a device outputting data to the outside comprising a first transistor with a first conductive type which is connected between an output low voltage corresponding to a first logical value and the pad and which connects the output low voltage to the pad when the digital data has the first logical value; a second transistor with a second conductive type which is connected between an output high voltage corresponding to a second logical value and the pad and which connects the output high voltage to the pad when the digital data has the second logical value; and a third transistor with the first conductive type which is connected between the output high voltage and the pad so as to be parallel to the second transistor and which connects the output high voltage to the pad when the digital data has the second logical value.
摘要翻译：本公开涉及一种向外部输出数据的装置，包括具有第一导电类型的第一晶体管，第一晶体管连接在对应于第一逻辑值的输出低电压和焊盘之间，并且当数字数据被连接时，将输出低电压连接到焊盘具有第一个逻辑值; 具有第二导电类型的第二晶体管，其连接在对应于第二逻辑值的输出高电压和焊盘之间，并且当数字数据具有第二逻辑值时，将输出高电压连接到焊盘; 以及具有第一导电类型的第三晶体管，其连接在输出高电压和焊盘之间，以便平行于第二晶体管并且当数字数据具有第二逻辑值时将输出高电压连接到焊盘。

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