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31. 发明授权

US06292389B1 Magnetic element with improved field response and fabricating method thereof 有权
标题翻译：具有改善的场响应的磁性元件及其制造方法
公开(公告)号：US06292389B1
公开(公告)日：2001-09-18
申请号：US09356864
申请日：1999-07-19
申请人： Eugene Youjun Chen , Jon Michael Slaughter , Jing Shi
发明人： Eugene Youjun Chen , Jon Michael Slaughter , Jing Shi
IPC分类号： H01L2976
CPC分类号： H01F41/307 , B82Y10/00 , B82Y25/00 , B82Y40/00 , H01F10/3268 , H01F10/3272 , H01L43/08
摘要： An improved and novel fabrication method for a magnetic element, and more particularly a magnetic element (10) including a first electrode (14), a second electrode (18) and a spacer layer (16). The first electrode (14) includes a fixed ferromagnetic layer (26) having a thickness t1. A second electrode (18) is included and comprises a free ferromagnetic layer (28) having a thickness t2. A spacer layer (16) is located between the fixed ferromagnetic layer (26) and the free ferromagnetic (28) layer, the spacer layer (16) having a thickness t3, where 0.25t3
摘要翻译：一种用于磁性元件的改进和新颖的制造方法，更具体地，包括第一电极（14），第二电极（18）和间隔层（16）的磁性元件（10）。第一电极（14）包括具有厚度t1的固定铁磁层（26）。包括第二电极（18）并且包括具有厚度t2的自由铁磁层（28）。间隔层（16）位于固定铁磁层（26）和自由铁磁层（28）之间，隔离层（16）的厚度为t3，其中0.25t3

32. 发明授权

US5757695A Mram with aligned magnetic vectors 失效
标题翻译：与对准的磁性矢量
公开(公告)号：US5757695A
公开(公告)日：1998-05-26
申请号：US795488
申请日：1997-02-05
申请人： Jing Shi , Theodore Zhu , Saied N. Tehrani
发明人： Jing Shi , Theodore Zhu , Saied N. Tehrani
IPC分类号： G11C11/15 , G11C11/16 , G11C11/56 , H01L21/8246 , H01L27/105 , H01L43/08 , G11C11/10
CPC分类号： G11C11/5607 , G11C11/15 , G11C11/16 , G11C2211/5616
摘要： A multi-layer magnetic memory cell is provided, with magnetic vectors aligned along a length of the cell. To align the magnetic end vectors, an ellipsoidal shape is formed at the ends of the memory cell. Magnetic vectors aligned along the length prevent from forming high fields and magnetic poles at the discontinuity or ends of the layers. The memory cell with the ellipsoidal shape shows a constant magnetic resistance of the magnetic cell when a magnetic field is applied to the cell and attains a reduction of power consumption for the magnetic cell.
摘要翻译：提供了多层磁存储单元，其中磁矢量沿单元的长度排列。为了对准磁端向量，在存储单元的端部形成椭圆形状。沿着长度排列的磁矢量防止在层的不连续或端部处形成高场和磁极。具有椭圆形状的存储单元在磁场施加到电池并且降低磁性单元的功耗时显示出磁性单元的恒定的磁阻。

33. 发明授权

US08634500B2 Direct feedback equalization with dynamic referencing 有权
标题翻译：直接反馈均衡与动态参考
公开(公告)号：US08634500B2
公开(公告)日：2014-01-21
申请号：US13431009
申请日：2012-03-27
申请人： Zuxu Qin , Rajesh Kumar , Dawei Huang , Jing Shi , Deqiang Song
发明人： Zuxu Qin , Rajesh Kumar , Dawei Huang , Jing Shi , Deqiang Song
IPC分类号： H03K9/00
CPC分类号： H04L25/062 , H04L2025/0349
摘要： A receiver circuit includes a first slicer coupled to receive data signals from a signal path and a reference voltage from a reference voltage path that is separate from the signal path. The first slicer is configured output a logic value based on a comparison between a voltage of the data signal and the reference voltage. The receiver circuit further includes a reference voltage generator configured to generate the reference voltage. The reference voltage generator is configured to dynamically generate the reference voltage based on logic values of previously received signals during operation in a first mode. During operation in a second mode, the reference voltage generator is configured to generate and provide the reference voltage as a static voltage.
摘要翻译：接收器电路包括耦合以从信号路径接收数据信号的第一限幅器和与信号路径分离的参考电压路径的参考电压。第一限幅器被配置为基于数据信号的电压与参考电压之间的比较来输出逻辑值。接收器电路还包括被配置为产生参考电压的参考电压发生器。参考电压发生器被配置为基于在第一模式中的操作期间先前接收到的信号的逻辑值来动态地产生参考电压。在第二模式的操作期间，参考电压发生器被配置为产生并提供参考电压作为静态电压。

34. 发明申请

US20130259162A1 Direct Feedback Equalization with Dynamic Referencing 有权
标题翻译：直接反馈均衡与动态参考
公开(公告)号：US20130259162A1
公开(公告)日：2013-10-03
申请号：US13431009
申请日：2012-03-27
申请人： Zuxu Qin , Rajesh Kumar , Dawei Huang , Jing Shi , Deqiang Song
发明人： Zuxu Qin , Rajesh Kumar , Dawei Huang , Jing Shi , Deqiang Song
IPC分类号： H04L25/10 , H04B1/16
CPC分类号： H04L25/062 , H04L2025/0349
摘要： A receiver circuit includes a first slicer coupled to receive data signals from a signal path and a reference voltage from a reference voltage path that is separate from the signal path. The first slicer is configured output a logic value based on a comparison between a voltage of the data signal and the reference voltage. The receiver circuit further includes a reference voltage generator configured to generate the reference voltage. The reference voltage generator is configured to dynamically generate the reference voltage based on logic values of previously received signals during operation in a first mode. During operation in a second mode, the reference voltage generator is configured to generate and provide the reference voltage as a static voltage.
摘要翻译：接收器电路包括耦合以从信号路径接收数据信号的第一限幅器和与信号路径分离的参考电压路径的参考电压。第一限幅器被配置为基于数据信号的电压与参考电压之间的比较来输出逻辑值。接收器电路还包括被配置为产生参考电压的参考电压发生器。参考电压发生器被配置为基于在第一模式中的操作期间先前接收到的信号的逻辑值来动态地产生参考电压。在第二模式的操作期间，参考电压发生器被配置为产生并提供参考电压作为静态电压。

35. 发明申请

US20130114459A1 METHOD FOR CALIBRATING ANTENNA RECIPROCITY IN A BASE STATION OF WIRELESS NETWORK AND A DEVICE THEREOF 有权
标题翻译：用于在无线网络基站中校准天线回复的方法及其设备
公开(公告)号：US20130114459A1
公开(公告)日：2013-05-09
申请号：US13810487
申请日：2011-07-15
申请人： Qinglin Luo , Jing Shi , Yan Zhao
发明人： Qinglin Luo , Jing Shi , Yan Zhao
IPC分类号： H04W24/00
CPC分类号： H04W24/00 , H04B7/024 , H04B17/12 , H04W24/08
摘要： The present invention provides a method and device for calibrating antenna reciprocity via OTA in a base station of wireless network, and the method comprises: determining, based on a predefined rule, a plurality of calibrating UEs out of a plurality of UEs, and antennas, to be calibrated by the plurality of calibrating UEs, of the plurality of base stations, wherein the plurality of calibrating UEs are configured to calibrate antennas of the plurality of base stations; and calibrating, according to the determined calibration relationship, the antennas reciprocity of the plurality of base stations based on the plurality of calibrating UEs. With the method of present invention, communication channel model can be calibrated effectively so as to enhance antenna reciprocity in CoMP scenario.
摘要翻译：本发明提供了一种用于在无线网络的基站中经由OTA来校准天线互易性的方法和装置，并且所述方法包括：基于预定规则，确定多个UE中的多个校准UE以及天线，由所述多个基站中的多个校准UE校准，其中所述多个校准UE被配置为校准所述多个基站中的天线; 以及根据所确定的校准关系，基于所述多个校准UE来校准所述多个基站的天线互易性。利用本发明的方法，可以有效地校准通信信道模型，以便增强CoMP场景中的天线互易性。

36. 发明申请

US20130113020A1 SIGE HBT AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译： SIGT HBT及其制造方法
公开(公告)号：US20130113020A1
公开(公告)日：2013-05-09
申请号：US13613236
申请日：2012-09-13
申请人： Donghua Liu , Wenting Duan , Wensheng Qian , Jun Hu , Jing Shi
发明人： Donghua Liu , Wenting Duan , Wensheng Qian , Jun Hu , Jing Shi
IPC分类号： H01L29/737 , H01L21/331
CPC分类号： H01L29/66242 , H01L29/0821 , H01L29/7371
摘要： A SiGe HBT is disclosed, which includes: a silicon substrate; shallow trench field oxides formed in the silicon substrate; a pseudo buried layer formed at bottom of each shallow trench field oxide; a collector region formed beneath the surface of the silicon substrate, the collector region being sandwiched between the shallow trench field oxides and between the pseudo buried layers; a polysilicon gate formed above each shallow trench field oxide having a thickness of greater than 150 nm; a base region on the polysilicon gates and the collector region; emitter region isolation oxides on the base region; and an emitter region on the emitter region isolation oxides and a part of the base region. The polysilicon gate is formed by gate polysilicon process of a MOSFET in a CMOS process. A method of manufacturing the SiGe HBT is also disclosed.
摘要翻译：公开了一种SiGe HBT，其包括：硅衬底; 形成在硅衬底中的浅沟槽场氧化物; 形成在每个浅沟槽场氧化物的底部的伪掩埋层; 形成在所述硅衬底的表面下方的集电极区域，所述集电极区域夹在所述浅沟槽场氧化物之间和所述伪埋层之间; 形成在每个浅沟槽场氧化物上方的多晶硅栅极，其厚度大于150nm; 多晶硅栅极和集电极区域上的基极区域; 发射极区隔离氧化物; 并且发射极区域上的发射极区域隔离氧化物和基极区域的一部分。多晶硅栅极通过CMOS工艺中的MOSFET的栅极多晶硅工艺形成。还公开了制造SiGe HBT的方法。

37. 发明申请

US20130034862A1 Methods for Diagnosis, Prognosis and Methods of Treatment 审中-公开
标题翻译：诊断方法，预后及治疗方法
公开(公告)号：US20130034862A1
公开(公告)日：2013-02-07
申请号：US13596579
申请日：2012-08-28
申请人： Wendy J. Fantl , David B. Rosen , Alessandra Cesano , Santosh K. Putta , James R. Hackett , Michael Walker , Jing Shi
发明人： Wendy J. Fantl , David B. Rosen , Alessandra Cesano , Santosh K. Putta , James R. Hackett , Michael Walker , Jing Shi
IPC分类号： G01N21/64 , G01N21/76
CPC分类号： G01N33/57426 , A61K31/4709 , A61K31/513 , A61K31/704 , A61K31/7068 , A61K31/7076 , G01N33/50 , G01N33/5041 , G01N33/5044 , G01N33/5047 , G01N33/5055 , G01N33/5073 , G01N33/5094 , G01N33/53 , G01N33/574 , G01N33/57407 , G01N33/6893 , G01N2333/705 , G01N2800/22 , G01N2800/52
摘要： The present invention provides an approach for the determination of the activation states of a plurality of proteins in single cells. This approach permits the rapid detection of heterogeneity in a complex cell population based on activation states, expression markers and other criteria, and the identification of cellular subsets that exhibit correlated changes in activation within the cell population. Moreover, this approach allows the correlation of cellular activities or properties. In addition, the use of modulators of cellular activation allows for characterization of pathways and cell populations. Several exemplary diseases that can be analyzed using the invention include AML, MDS, and MPN.
摘要翻译：本发明提供了用于确定单细胞中多种蛋白质的活化状态的方法。这种方法允许基于活化状态，表达标志物和其他标准快速检测复杂细胞群体中的异质性，以及在细胞群体内表现出相关的激活变化的细胞亚群的鉴定。此外，这种方法允许细胞活动或性质的相关性。此外，使用细胞激活的调节剂允许表征途径和细胞群体。可以使用本发明分析的几种示例性疾病包括AML，MDS和MPN。

38. 发明申请

US20120211878A1 CHIP PACKAGE WITH PLANK STACK OF SEMICONDUCTOR DIES 有权
标题翻译：芯片包装与平面堆叠的半导体芯片
公开(公告)号：US20120211878A1
公开(公告)日：2012-08-23
申请号：US13029825
申请日：2011-02-17
申请人： Darko R. Popovic , Matthew D. Giere , Bruce M. Guenin , Theresa Y. Sze , Ivan Shubin , John A. Harada , David C. Douglas , Jing Shi
发明人： Darko R. Popovic , Matthew D. Giere , Bruce M. Guenin , Theresa Y. Sze , Ivan Shubin , John A. Harada , David C. Douglas , Jing Shi
IPC分类号： H01L25/07 , H01L21/60
CPC分类号： H01L24/05 , H01L23/5385 , H01L24/16 , H01L24/32 , H01L24/73 , H01L25/0655 , H01L25/0657 , H01L2224/0401 , H01L2224/04042 , H01L2224/04105 , H01L2224/0554 , H01L2224/05554 , H01L2224/1134 , H01L2224/13005 , H01L2224/13011 , H01L2224/1302 , H01L2224/13027 , H01L2224/13082 , H01L2224/13111 , H01L2224/13147 , H01L2224/1329 , H01L2224/13311 , H01L2224/13339 , H01L2224/13347 , H01L2224/1403 , H01L2224/14051 , H01L2224/14151 , H01L2224/14155 , H01L2224/14515 , H01L2224/16105 , H01L2224/16157 , H01L2224/17181 , H01L2224/20 , H01L2224/2919 , H01L2224/32145 , H01L2224/33181 , H01L2224/4813 , H01L2224/48159 , H01L2224/484 , H01L2224/4846 , H01L2224/48463 , H01L2224/48477 , H01L2224/50 , H01L2224/73103 , H01L2224/73203 , H01L2224/73204 , H01L2224/73253 , H01L2224/75704 , H01L2224/81139 , H01L2224/81947 , H01L2225/06589 , H01L2924/00011 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/00012
摘要： In a chip package, semiconductor dies in a vertical stack of semiconductor dies or chips (which is referred to as a ‘plank stack’) are separated by a mechanical spacer (such as a filler material or an adhesive). Moreover, the chip package includes a substrate at a right angle to the plank stack, which is electrically coupled to the semiconductor dies along an edge of the plank stack. In particular, electrical pads proximate to a surface of the substrate (which are along a stacking direction of the plank stack) are electrically coupled to pads that are proximate to edges of the semiconductor dies by an intervening conductive material, such as: solder, stud bumps, plated traces, wire bonds, spring connectors, a conductive adhesive and/or an anisotropic conducting film. Note that the chip package may facilitate high-bandwidth communication of signals between the semiconductor dies and the substrate.
摘要翻译：在芯片封装中，半导体管芯或芯片（被称为“板堆叠”）的垂直堆叠中的半导体管芯由机械间隔件（例如填充材料或粘合剂）分开。此外，芯片封装包括与板堆叠成直角的衬底，其与板堆叠的边缘电耦合到半导体管芯。特别地，靠近基板表面（沿着板堆叠的堆叠方向）的电焊盘通过中间导电材料电耦合到靠近半导体管芯边缘的焊盘，例如：焊料，螺柱凸块，电镀痕迹，线接合，弹簧连接器，导电粘合剂和/或各向异性导电膜。注意，芯片封装可以促进半导体管芯和衬底之间的信号的高带宽通信。

39. 发明授权

US08188581B2 Mechanical coupling in a multi-chip module using magnetic components 有权
公开(公告)号：US08188581B2
公开(公告)日：2012-05-29
申请号：US12568024
申请日：2009-09-28
申请人： Jing Shi , Hiren D. Thacker , Ashok V. Krishnamoorthy , John E. Cunningham
发明人： Jing Shi , Hiren D. Thacker , Ashok V. Krishnamoorthy , John E. Cunningham
IPC分类号： H01L23/495
CPC分类号： H01L23/13 , H01L24/48 , H01L24/73 , H01L25/0652 , H01L25/0657 , H01L2224/16147 , H01L2224/16237 , H01L2224/48091 , H01L2224/48227 , H01L2224/73257 , H01L2224/81141 , H01L2224/81191 , H01L2225/0651 , H01L2225/06517 , H01L2225/06593 , H01L2924/00014 , H01L2924/01006 , H01L2924/01012 , H01L2924/01013 , H01L2924/01019 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01038 , H01L2924/01051 , H01L2924/01056 , H01L2924/01079 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H01L2924/15153 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A multi-chip module (MCM) is described. This MCM includes at least two substrates that are remateably mechanically coupled by positive and negative features on facing surfaces of the substrates. These positive and negative features mate with each other. In particular, a positive feature may mate with a given pair of negative features, which includes negative features on each of the substrates. Furthermore, at least one of the negative features in the given pair may include a hard magnetic material, and the positive feature and the other negative feature in the given pair may include a soft magnetic material that provide a flux-return path to the hard magnetic material. In this way, the hard magnetic material may facilitate the remateable mechanical coupling of the substrates.

40. 发明申请

US20120099469A1 METHODS OF TRANSMITTING A SIGNAL IN A TIME DIVISION DUPLEXING MIMO SYSTEM AND ASSOCIATED APPARATUSES 审中-公开
标题翻译：在时分双工MIMO系统中传输信号的方法和相关设备
公开(公告)号：US20120099469A1
公开(公告)日：2012-04-26
申请号：US13380265
申请日：2009-06-23
申请人： Qinglin Luo , Jing Shi
发明人： Qinglin Luo , Jing Shi
IPC分类号： H04J3/00 , H04W24/00
CPC分类号： H04B7/0434 , H04L25/0242 , H04W24/00
摘要： The present invention relates to methods of transmitting a signal in a time division duplexing MIMO system and associated apparatuses. According to a first aspect of the present invention, there is provided a method of transmitting a signal in an eNodeB of a time division duplexing multiple input multiple output system. The method includes: A. receiving a signal from a user equipment in a space division multiplexing group and estimating uplink channel characteristics according to the received signal; B. determining reciprocity calibration information between the uplink channel characteristics and downlink channel characteristics; C. determining a downlink precoding matrix using zero forcing according to the uplink channel characteristics and the calibration information and transmitting a downlink signal to the user equipment in the space division multiplexing group according to the determined downlink precoding matrix. And the step B further comprises receiving information associated with a downlink vector channel matrix fed back from the user equipment in the space division multiplexing group and selectively updating the calibration information according to the information associated with the downlink vector channel matrix.
摘要翻译：本发明涉及在时分双工MIMO系统和相关设备中发送信号的方法。根据本发明的第一方面，提供了一种在时分双工多输入多输出系统的eNodeB中发送信号的方法。该方法包括：A.接收来自空分复用组中的用户设备的信号，并根据接收到的信号估计上行链路信道特性; B.确定上行链路信道特性与下行链路信道特性之间的互易校准信息; C.根据上行链路信道特性和校准信息，使用零强制来确定下行链路预编码矩阵，并根据确定的下行链路预编码矩阵向空间复用组中的用户设备发送下行链路信号。并且步骤B还包括接收与在空分多路复用组中从用户设备反馈的下行链路向量信道矩阵相关联的信息，并且根据与下行链路向量信道矩阵相关联的信息选择性地更新校准信息。

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