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31. 发明授权

US07020860B1 Method for monitoring and improving integrated circuit fabrication using FPGAs 有权
标题翻译：使用FPGA监控和改进集成电路制造的方法
公开(公告)号：US07020860B1
公开(公告)日：2006-03-28
申请号：US10808737
申请日：2004-03-24
申请人： Joe W. Zhao , Xiao-Yu Li , Feng Wang , Zhi-Min Ling
发明人： Joe W. Zhao , Xiao-Yu Li , Feng Wang , Zhi-Min Ling
IPC分类号： G06F17/50
CPC分类号： G06F17/5054 , G01R31/318321 , G01R31/318519
摘要： Methods for monitoring and improving the fabrication process of integrated circuits using configurable devices are described. In one aspect, the method includes instantiating a test pattern on one or more configurable devices fabricated using the fabrication process, identifying an underperforming region of the configurable devices, and determining if the underperforming region is layout sensitive. At least one of the fabrication process and the layout of the configurable device can then be adjusted based on the determination. In some embodiments, the configurable device may be a programmable logic device, such as a field programmable logic array.
摘要翻译：描述了使用可配置的装置来监测和改进集成电路的制造过程的方法。在一个方面，该方法包括在使用制造工艺制造的一个或多个可配置的设备上实例化测试图案，识别可配置设备的表现不佳的区域，以及确定表现不佳的区域是否是布局敏感的。然后可以基于确定来调整可配置设备的制造过程和布局中的至少一个。在一些实施例中，可配置设备可以是可编程逻辑设备，诸如现场可编程逻辑阵列。

32. 发明授权

US06404006B2 EEPROM cell with tunneling across entire separated channels 失效
标题翻译： EEPROM单元，穿过整个分离的通道
公开(公告)号：US06404006B2
公开(公告)日：2002-06-11
申请号：US09203149
申请日：1998-12-01
申请人： Xiao-Yu Li , Steven J. Fong
发明人： Xiao-Yu Li , Steven J. Fong
IPC分类号： H01L29788
CPC分类号： H01L27/11521 , G11C16/0441 , H01L27/115 , H01L27/11558
摘要： An EEPROM cell is described that is programmed and erased by electron tunneling across an entire portion of separate transistor channels. The EEPROM cell has three transistors formed in a semiconductor substrate. The three transistors are a tunneling transistor (PMOS), a sense transistor (NMOS) and a read transistor (NMOS). Electron tunneling occurs to program the EEPROM cell through a sense tunnel oxide layer having a thickness to allow the electron tunneling across an entire portion of a sense channel upon incurrence of a sufficient voltage potential between a floating gate and the tunnel channel. Electron tunneling also occurs to erase the EEPROM cell through a tunnel oxide layer having a thickness to allow electron tunneling across an entire portion of a tunneling channel upon incurrence of a sufficient voltage potential between the floating gate and the tunneling channel.
摘要翻译：描述了通过遍及分离的晶体管通道的整个部分的电子隧道编程和擦除的EEPROM单元。 EEPROM单元具有形成在半导体衬底中的三个晶体管。三个晶体管是隧道晶体管（PMOS），感测晶体管（NMOS）和读取晶体管（NMOS）。发生电子隧穿，以通过具有厚度的感测隧道氧化物层对EEPROM单元进行编程，以便在浮动栅极和隧道通道之间发生足够的电压电势时允许跨越感测通道的整个部分的电子隧穿。还发生电子隧穿，以通过具有厚度的隧道氧化物层擦除EEPROM电池，以在浮动栅极和隧道通道之间发生足够的电压电势时允许穿过隧道通道的整个部分的电子隧穿。

33. 发明授权

US06294811B1 Two transistor EEPROM cell 失效
标题翻译：两个晶体管EEPROM单元
公开(公告)号：US06294811B1
公开(公告)日：2001-09-25
申请号：US09245813
申请日：1999-02-05
申请人： Steven J. Fong , Xiao-Yu Li
发明人： Steven J. Fong , Xiao-Yu Li
IPC分类号： H01L29788
CPC分类号： H01L27/11521 , G11C16/0433 , H01L27/115 , H01L27/11558 , H01L29/7883
摘要： A two transistor EEPROM cell is described that is erased by electron tunneling across an entire portion of a tunneling channel and programmed by electron tunneling at an edge of a tunneling drain.
摘要翻译：描述了两个晶体管EEPROM单元，其通过穿过隧道通道的整个部分的电子隧穿而被擦除，并且通过在隧道漏极的边缘处的电子隧道编程。

34. 发明授权

US5795627A Method for annealing damaged semiconductor regions allowing for enhanced oxide growth 失效
标题翻译：用于退火损坏的半导体区域以允许增强的氧化物生长的方法
公开(公告)号：US5795627A
公开(公告)日：1998-08-18
申请号：US799236
申请日：1997-02-14
申请人： Sunil Mehta , Emi Ishida , Xiao-Yu Li
发明人： Sunil Mehta , Emi Ishida , Xiao-Yu Li
IPC分类号： H01L21/316 , H01L21/762 , H01L27/115 , C23C14/04
CPC分类号： H01L21/76213 , H01L21/316 , H01L27/115
摘要： A method of forming an oxide enhancing region, such as phosphorus, in a semiconductor substrate with minimal damage is provided. The method includes the steps of forming an oxide enhancing region in the semiconductor substrate to a depth below the semiconductor substrate. A 308 nm excimer laser is then applied to the oxide enhancing region in order to reduce the damage caused by forming the oxide enhancing region. A uniform and reliable oxide layer is then formed on the surface of the substrate over the damage reduced oxide enhancing region.
摘要翻译：提供了在具有最小损伤的半导体衬底中形成诸如磷的氧化物增强区域的方法。该方法包括以下步骤：在半导体衬底中形成半导体衬底下方的深度的氧化物增强区。然后将308nm准分子激光器施加到氧化物增强区域，以便减少由形成氧化物增强区域引起的损伤。然后在损伤还原氧化物增强区域上的衬底的表面上形成均匀且可靠的氧化物层。

35. 发明授权

US5761116A V.sub.pp only scalable EEPROM memory cell having transistors with thin tunnel gate oxide 失效
标题翻译： Vpp仅具有具有薄隧道栅极氧化物的晶体管的可扩展EEPROM存储单元
公开(公告)号：US5761116A
公开(公告)日：1998-06-02
申请号：US726512
申请日：1996-10-07
申请人： Xiao-Yu Li , Radu Barsan
发明人： Xiao-Yu Li , Radu Barsan
IPC分类号： G11C16/04 , H01L27/115 , H01L29/788
CPC分类号： H01L27/115 , G11C16/0441
摘要： An enhanced, scalable EEPROM memory cell is provided with a structure having a plurality of half-height tunnel oxide depletion mode transistors. The structure further has individual wordlines controlling the write and read transistors, respectively. With such a structure, lower voltages are used to program/erase the memory cell. The memory cell is scalable to small dimensions through the use of transistors having half-height tunnel oxide regions.
摘要翻译：提供了具有多个半高隧道氧化物耗尽型晶体管的结构的增强型可扩展EEPROM存储单元。该结构还分别具有控制写和晶体管的单个字线。通过这样的结构，使用较低的电压来对存储单元进行编程/擦除。通过使用具有半高隧道氧化物区域的晶体管，存储单元可缩放到小尺寸。

36. 发明授权

US5672521A Method of forming multiple gate oxide thicknesses on a wafer substrate 失效
标题翻译：在晶圆基板上形成多个栅极氧化物厚度的方法
公开(公告)号：US5672521A
公开(公告)日：1997-09-30
申请号：US561306
申请日：1995-11-21
申请人： Radu M. Barsan , Xiao-Yu Li , Sunil Mehta
发明人： Radu M. Barsan , Xiao-Yu Li , Sunil Mehta
IPC分类号： H01L21/28 , H01L21/8234 , H01L29/51 , H01L21/266
CPC分类号： H01L21/28185 , H01L21/2822 , H01L21/823462 , H01L29/518 , H01L21/28211 , Y10S148/116 , Y10S148/163 , Y10S438/981
摘要： An integrated circuit device and manufacturing process wherein a first region is formed in a substrate with a dopant that enhances oxide formation and a second region is formed in the substrate with a dose of nitrogen that retards oxide formation. An oxide layer is grown over the first and the second regions and over a third region of the substrate such that the first, second, and third regions yield differing thicknesses of the oxide layer.
摘要翻译：一种集成电路器件和制造方法，其中第一区域形成在具有增强氧化物形成的掺杂剂的衬底中，并且在衬底中形成具有延迟氧化物形成的氮的剂量的第二区域。在衬底的第一和第二区域和第三区域上生长氧化物层，使得第一，第二和第三区域产生不同厚度的氧化物层。

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