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31. 发明申请

US20050015688A1 Phase shifter with reduced linear dependency 有权
标题翻译：移相器具有减少的线性依赖性
公开(公告)号：US20050015688A1
公开(公告)日：2005-01-20
申请号：US10911033
申请日：2004-08-03
申请人： Janusz Rajski , Jerzy Tyszer , Nagesh Tamarapalli
发明人： Janusz Rajski , Jerzy Tyszer , Nagesh Tamarapalli
IPC分类号： G01R31/28 , G01R31/3181 , G01R31/3183 , G01R31/3185 , G11B20/20 , G06K5/04 , G11B5/00
CPC分类号： G01R31/318541 , G01R31/31813 , G01R31/318385 , G01R31/318547 , G01R31/318594
摘要： A method is disclosed for the automated synthesis of phase shifters. Phase shifters comprise circuits used to remove effects of structural dependencies featured by pseudo-random test pattern generators driving parallel scan chains. Using a concept of duality, the method relates the logical states of linear feedback shift registers (LFSRs) and circuits spacing their inputs to each of the output channels. The method generates a phase shifter network balancing the loads of successive stages of LFSRs and satisfying criteria of reduced linear dependency, channel separation and circuit complexity.
摘要翻译：公开了用于自动合成移相器的方法。移相器包括用于消除驱动并行扫描链的伪随机测试图形发生器特征的结构依赖性的影响的电路。使用二元性概念，该方法涉及线性反馈移位寄存器（LFSR）的逻辑状态和将输入间隔到每个输出通道的电路。该方法产生平衡LFSR的连续级的负载的移相器网络，并且满足减少的线性依赖性，信道分离和电路复杂度的标准。

32. 发明授权

US5737340A Multi-phase test point insertion for built-in self test of integrated circuits 失效
标题翻译：集成电路内置自检的多相测试点插入
公开(公告)号：US5737340A
公开(公告)日：1998-04-07
申请号：US678376
申请日：1996-07-01
申请人： Nagesh Tamarapalli , Janusz Rajski
发明人： Nagesh Tamarapalli , Janusz Rajski
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G06F11/263 , G01R31/318342 , G06F17/5022 , G06F2217/14
摘要： Method and apparatus for providing high quality Built-in-Self-Test (BIST) of integrated circuits, while guaranteeing convergence and reducing area-overhead and power dissipation during test mode. A divide and conquer approach is used to partition the test into multiple phases during which a number of test patterns are applied to a circuit under test (CUT). The design of each phase (the selection of control and observation points) is guided by a progressively reduced list of undetected faults. Within a phase, a set of control points maximally contributing to the fault coverage achieved so far is identified using a unique probabilistic fault simulation (PFS) technique. The PFS technique accurately computes a propagation profile of the circuit and uses it to determine the impact of a new control point in the presence of control points selected so far. In this manner, in each new phase a group of control points, driven by fixed values and operating synergistically, is enabled. Observation points are selected in a similar fashion to further enhance the fault coverage. The sets of control and observation points are then inserted into the circuit under test and a new, reduced list of undetected faults is determined through exact fault simulation. This process is iterative and continues until the number of undetected faults is less than or equal to an acceptable threshold, a pre-specified number of control and observation points have been inserted, or the maximum number of specified test phases has been reached.
摘要翻译：提供集成电路高质量内置自检（BIST）的方法和设备，同时保证了测试模式下的融合，减少了面积开销和功耗。分割和征服方法用于将测试分成多个阶段，在此阶段将多个测试模式应用于被测电路（CUT）。每个阶段的设计（控制和观测点的选择）都是逐渐减少的未检测到的故障列表。在一个阶段中，使用独特的概率故障模拟（PFS）技术来识别到目前为止所达到的最大限度地有助于故障覆盖的一组控制点。 PFS技术准确地计算电路的传播特性，并使用它来确定在目前为止选择的控制点存在时新控制点的影响。以这种方式，在每个新阶段，启用由固定值驱动并且协同操作的一组控制点。以类似的方式选择观测点，以进一步增强故障覆盖。然后将控制和观测点的集合插入到被测电路中，并通过精确的故障模拟确定未被检测的故障的新的减少的列表。该过程是迭代的，并且持续到未检测到的故障的数量小于或等于可接受的阈值，已经插入了预定数量的控制和观察点，或者达到了指定的测试阶段的最大数目。

33. 发明授权

US08051352B2 Timing-aware test generation and fault simulation 有权
标题翻译：定时识别测试生成和故障模拟
公开(公告)号：US08051352B2
公开(公告)日：2011-11-01
申请号：US11796374
申请日：2007-04-27
申请人： Xijiang Lin , Kun-Han Tsai , Mark Kassab , Chen Wang , Janusz Rajski
发明人： Xijiang Lin , Kun-Han Tsai , Mark Kassab , Chen Wang , Janusz Rajski
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G01R31/318328 , G01R31/3177 , G01R31/31835 , G01R31/318357 , G06F17/5009
摘要： Disclosed herein are exemplary methods, apparatus, and systems for performing timing-aware automatic test pattern generation (ATPG) that can be used, for example, to improve the quality of a test set generated for detecting delay defects or holding time defects. In certain embodiments, timing information derived from various sources (e.g. from Standard Delay Format (SDF) files) is integrated into an ATPG tool. The timing information can be used to guide the test generator to detect the faults through certain paths (e.g., paths having a selected length, or range of lengths, such as the longest or shortest paths). To avoid propagating the faults through similar paths repeatedly, a weighted random method can be used to improve the path coverage during test generation. Experimental results show that significant test quality improvement can be achieved when applying embodiments of timing-aware ATPG to industrial designs.
摘要翻译：这里公开了用于执行定时感知自动测试模式生成（ATPG）的示例性方法，装置和系统，其可以用于例如为了提高用于检测延迟缺陷或保持时间缺陷而产生的测试集的质量。在某些实施例中，从各种源（例如，从标准延迟格式（SDF）文件）导出的定时信息被集成到ATPG工具中。定时信息可用于引导测试发生器通过某些路径（例如，具有选定长度的路径或长度范围，例如最长或最短路径）来检测故障。为了避免重复通过类似路径传播故障，可以使用加权随机方法来提高测试生成过程中的路径覆盖。实验结果表明，当将工业设计应用于定时识别ATPG的实施例时，可以实现显着的测试质量改进。

34. 发明授权

US10509073B2 Timing-aware test generation and fault simulation 有权
公开(公告)号：US10509073B2
公开(公告)日：2019-12-17
申请号：US15664169
申请日：2017-07-31
申请人： Xijiang Lin , Kun-Han Tsai , Mark Kassab , Chen Wang , Janusz Rajski
发明人： Xijiang Lin , Kun-Han Tsai , Mark Kassab , Chen Wang , Janusz Rajski
IPC分类号： G01R31/3183 , G01R31/3177 , G06F17/50
摘要： Disclosed herein are exemplary methods, apparatus, and systems for performing timing-aware automatic test pattern generation (ATPG) that can be used, for example, to improve the quality of a test set generated for detecting delay defects or holding time defects. In certain embodiments, timing information derived from various sources (e.g. from Standard Delay Format (SDF) files) is integrated into an ATPG tool. The timing information can be used to guide the test generator to detect the faults through certain paths (e.g., paths having a selected length, or range of lengths, such as the longest or shortest paths). To avoid propagating the faults through similar paths repeatedly, a weighted random method can be used to improve the path coverage during test generation. Experimental results show that significant test quality improvement can be achieved when applying embodiments of timing-aware ATPG to industrial designs.

35. 发明授权

US08560906B2 Timing-aware test generation and fault simulation 有权
公开(公告)号：US08560906B2
公开(公告)日：2013-10-15
申请号：US13285899
申请日：2011-10-31
申请人： Xijiang Lin , Kun-Han Tsai , Mark Kassab , Chen Wang , Janusz Rajski
发明人： Xijiang Lin , Kun-Han Tsai , Mark Kassab , Chen Wang , Janusz Rajski
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G01R31/318328 , G01R31/3177 , G01R31/31835 , G01R31/318357 , G06F17/5009
摘要： Disclosed herein are exemplary methods, apparatus, and systems for performing timing-aware automatic test pattern generation (ATPG) that can be used, for example, to improve the quality of a test set generated for detecting delay defects or holding time defects. In certain embodiments, timing information derived from various sources (e.g. from Standard Delay Format (SDF) files) is integrated into an ATPG tool. The timing information can be used to guide the test generator to detect the faults through certain paths (e.g., paths having a selected length, or range of lengths, such as the longest or shortest paths). To avoid propagating the faults through similar paths repeatedly, a weighted random method can be used to improve the path coverage during test generation. Experimental results show that significant test quality improvement can be achieved when applying embodiments of timing-aware ATPG to industrial designs.

36. 发明申请

US20120174049A1 TIMING-AWARE TEST GENERATION AND FAULT SIMULATION 有权
标题翻译：定时测试生成和故障模拟
公开(公告)号：US20120174049A1
公开(公告)日：2012-07-05
申请号：US13285899
申请日：2011-10-31
申请人： Xijiang Lin , Kun-Han Tsai , Mark Kassab , Chen Wang , Janusz Rajski
发明人： Xijiang Lin , Kun-Han Tsai , Mark Kassab , Chen Wang , Janusz Rajski
IPC分类号： G06F17/50
CPC分类号： G01R31/318328 , G01R31/3177 , G01R31/31835 , G01R31/318357 , G06F17/5009
摘要： Disclosed herein are exemplary methods, apparatus, and systems for performing timing-aware automatic test pattern generation (ATPG) that can be used, for example, to improve the quality of a test set generated for detecting delay defects or holding time defects. In certain embodiments, timing information derived from various sources (e.g. from Standard Delay Format (SDF) files) is integrated into an ATPG tool. The timing information can be used to guide the test generator to detect the faults through certain paths (e.g., paths having a selected length, or range of lengths, such as the longest or shortest paths). To avoid propagating the faults through similar paths repeatedly, a weighted random method can be used to improve the path coverage during test generation. Experimental results show that significant test quality improvement can be achieved when applying embodiments of timing-aware ATPG to industrial designs.
摘要翻译：这里公开了用于执行定时感知自动测试模式生成（ATPG）的示例性方法，装置和系统，其可以用于例如为了提高用于检测延迟缺陷或保持时间缺陷而产生的测试集的质量。在某些实施例中，从各种源（例如，从标准延迟格式（SDF）文件）导出的定时信息被集成到ATPG工具中。定时信息可用于引导测试发生器通过某些路径（例如，具有选定长度的路径或长度范围，例如最长或最短路径）来检测故障。为了避免重复通过类似路径传播故障，可以使用加权随机方法来提高测试生成过程中的路径覆盖。实验结果表明，当将工业设计应用于定时识别ATPG的实施例时，可以实现显着的测试质量改进。

37. 发明授权

US07984354B2 Generating responses to patterns stimulating an electronic circuit with timing exception paths 有权
标题翻译：产生对具有定时异常路径刺激电子电路的模式的响应
公开(公告)号：US07984354B2
公开(公告)日：2011-07-19
申请号：US12494121
申请日：2009-06-29
申请人： Dhiraj Goswami , Kun-Han Tsai , Mark Kassab , Janusz Rajski
发明人： Dhiraj Goswami , Kun-Han Tsai , Mark Kassab , Janusz Rajski
IPC分类号： G01R31/28
CPC分类号： G01R31/318547 , G01R31/318583
摘要： Improved responses can be generated to scan patterns (e.g., test patterns) for an electronic circuit designs having timing exception paths by more accurately determining the unknown values that propagate to observation points in the circuit, where the response is captured. For instance, the responses are determined more accurately by analyzing the effect of sensitizing a timing exception path during each time frame associated with a scan pattern. Path sensitization can be determined based on observing whether values injected at starting points of the timing exception paths due to signal transitions and glitches propagate to their end points. The response can be updated by masking the affected end points and propagating unknown values further in the circuit to determine whether they are captured at observation points of the circuit. For instance, the methods and systems described herein may result in reduced unknowns, improved test coverage and test compression.
摘要翻译：可以通过更准确地确定传播到电路中观测点的未知值（其中捕获响应）的具有定时异常路径的电子电路设计来扫描模式（例如，测试模式）的改进的响应。例如，通过分析在与扫描模式相关联的每个时间帧期间对定时异常路径敏感的影响，更准确地确定响应。可以基于观察由于信号转换和毛刺传播到它们的端点而在定时异常路径的起始点处注入的值是否可以确定路径敏化。可以通过在电路中屏蔽受影响的端点和进一步传播未知值来更新响应，以确定它们是否在电路的观测点被捕获。例如，本文描述的方法和系统可以导致未知数减少，改进的测试覆盖和测试压缩。

38. 发明申请

US20070288822A1 Timing-aware test generation and fault simulation 有权
标题翻译：定时识别测试生成和故障模拟
公开(公告)号：US20070288822A1
公开(公告)日：2007-12-13
申请号：US11796374
申请日：2007-04-27
申请人： Xijiang Lin , Kun-Han Tsai , Mark Kassab , Chen Wang , Janusz Rajski
发明人： Xijiang Lin , Kun-Han Tsai , Mark Kassab , Chen Wang , Janusz Rajski
IPC分类号： G06F9/455 , G01R31/3183
CPC分类号： G01R31/318328 , G01R31/3177 , G01R31/31835 , G01R31/318357 , G06F17/5009
摘要： Disclosed herein are exemplary methods, apparatus, and systems for performing timing-aware automatic test pattern generation (ATPG) that can be used, for example, to improve the quality of a test set generated for detecting delay defects or holding time defects. In certain embodiments, timing information derived from various sources (e.g. from Standard Delay Format (SDF) files) is integrated into an ATPG tool. The timing information can be used to guide the test generator to detect the faults through certain paths (e.g., paths having a selected length, or range of lengths, such as the longest or shortest paths). To avoid propagating the faults through similar paths repeatedly, a weighted random method can be used to improve the path coverage during test generation. Experimental results show that significant test quality improvement can be achieved when applying embodiments of timing-aware ATPG to industrial designs.
摘要翻译：这里公开了用于执行定时感知自动测试模式生成（ATPG）的示例性方法，装置和系统，其可以用于例如为了提高用于检测延迟缺陷或保持时间缺陷而产生的测试集的质量。在某些实施例中，从各种源（例如，从标准延迟格式（SDF）文件）导出的定时信息被集成到ATPG工具中。定时信息可用于引导测试发生器通过某些路径（例如，具有选定长度的路径或长度范围，例如最长或最短路径）来检测故障。为了避免重复通过类似路径传播故障，可以使用加权随机方法来提高测试生成过程中的路径覆盖。实验结果表明，当将工业设计应用于定时识别ATPG的实施例时，可以实现显着的测试质量改进。

39. 发明申请

US20090327986A1 GENERATING RESPONSES TO PATTERNS STIMULATING AN ELECTRONIC CIRCUIT WITH TIMING EXCEPTION PATHS 有权
标题翻译：对具有定时异常电位的电子电路刺激模式的响应
公开(公告)号：US20090327986A1
公开(公告)日：2009-12-31
申请号：US12494121
申请日：2009-06-29
申请人： Dhiraj Goswami , Kun-Han Tsai , Mark Kassab , Janusz Rajski
发明人： Dhiraj Goswami , Kun-Han Tsai , Mark Kassab , Janusz Rajski
IPC分类号： G06F17/50
CPC分类号： G01R31/318547 , G01R31/318583
摘要： Improved responses can be generated to scan patterns (e.g., test patterns) for an electronic circuit designs having timing exception paths by more accurately determining the unknown values that propagate to observation points in the circuit, where the response is captured. For instance, the responses are determined more accurately by analyzing the effect of sensitizing a timing exception path during each time frame associated with a scan pattern. Path sensitization can be determined based on observing whether values injected at starting points of the timing exception paths due to signal transitions and glitches propagate to their end points. The response can be updated by masking the affected end points and propagating unknown values further in the circuit to determine whether they are captured at observation points of the circuit. For instance, the methods and systems described herein may result in reduced unknowns, improved test coverage and test compression.
摘要翻译：可以通过更准确地确定传播到电路中观测点的未知值（其中捕获响应）的具有定时异常路径的电子电路设计来扫描模式（例如，测试模式）的改进的响应。例如，通过分析在与扫描模式相关联的每个时间帧期间对定时异常路径敏感的影响，更准确地确定响应。可以基于观察由于信号转换和毛刺传播到它们的端点而在定时异常路径的起始点处注入的值是否可以确定路径敏化。可以通过在电路中屏蔽受影响的端点和进一步传播未知值来更新响应，以确定它们是否在电路的观测点被捕获。例如，本文描述的方法和系统可以导致未知数减少，改进的测试覆盖和测试压缩。

40. 发明申请

US20180045780A1 TIMING-AWARE TEST GENERATION AND FAULT SIMULATION 审中-公开
公开(公告)号：US20180045780A1
公开(公告)日：2018-02-15
申请号：US15664169
申请日：2017-07-31
申请人： Xijiang Lin , Kun-Han Tsai , Mark Kassab , Chen Wang , Janusz Rajski
发明人： Xijiang Lin , Kun-Han Tsai , Mark Kassab , Chen Wang , Janusz Rajski
IPC分类号： G01R31/3183 , G01R31/3177 , G06F17/50
CPC分类号： G01R31/318328 , G01R31/3177 , G01R31/31835 , G01R31/318357 , G06F17/5009
摘要： Disclosed herein are exemplary methods, apparatus, and systems for performing timing-aware automatic test pattern generation (ATPG) that can be used, for example, to improve the quality of a test set generated for detecting delay defects or holding time defects. In certain embodiments, timing information derived from various sources (e.g. from Standard Delay Format (SDF) files) is integrated into an ATPG tool. The timing information can be used to guide the test generator to detect the faults through certain paths (e.g., paths having a selected length, or range of lengths, such as the longest or shortest paths). To avoid propagating the faults through similar paths repeatedly, a weighted random method can be used to improve the path coverage during test generation. Experimental results show that significant test quality improvement can be achieved when applying embodiments of timing-aware ATPG to industrial designs.

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