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31. 发明授权

US5432115A Process for making a contact betwen a capacitor electrode disposed in a trench and an MOS transistor source/drain region disposed outside the trench 失效
标题翻译：在设置在沟槽中的电容器电极和设置在沟槽外部的MOS晶体管源极/漏极区之间进行接触的工艺
公开(公告)号：US5432115A
公开(公告)日：1995-07-11
申请号：US284502
申请日：1994-08-04
申请人： Wolfgang Rosner , Franz Hofmann , Lothar Risch
发明人： Wolfgang Rosner , Franz Hofmann , Lothar Risch
IPC分类号： H01L21/76 , H01L21/8242 , H01L27/10 , H01L27/108
CPC分类号： H01L27/10861 , H01L27/10829
摘要： To make a contact between a capacitor electrode (13) disposed in a trench (11) and an MOS transistor source/drain region disposed outside the trench, a shallow etching is carried out in a self-aligned manner with respect to a field-oxide region insulating the MOS transistor by producing the trench (11) in a substrate (1). After forming an Si.sub.3 N.sub.4 spacer (10) at the edge (8), laid bare during the etching, of the substrate (1) the part laid bare of the field-oxide region (2) is first removed with the aid of a mask and the trench (11) is completed in a further etching. The contact is produced after the formation of an SiO.sub.2 layer (12) at the surface of the trench (11) after removing the Si.sub.3 N.sub.4 spacer (10) and producing the capacitor electrode (13) at the edge (8), laid bare by removing the Si.sub.3 N.sub.4 spacer (10), of the substrate (1).
摘要翻译： PCT No.PCT / DE93 / 00078 Sec。 371日期：1994年8月4日 102（e）日期1994年8月4日PCT提交1993年2月1日PCT公布。出版物WO93 / 16490 日期：1993年8月19日。为了在布置在沟槽（11）中的电容器电极（13）和设置在沟槽外部的MOS晶体管源/漏区之间进行接触，以自对准的方式进行浅蚀刻相对于通过在衬底（1）中产生沟槽（11）来绝缘MOS晶体管的场氧化物区域。在蚀刻过程中在边缘（8）处形成Si3N4间隔物（10）之后，在衬底（1）上放置裸露的场氧化物区域（2）的部分首先借助掩模去除，在另外的蚀刻中完成沟槽（11）。在除去Si 3 N 4间隔物（10）之后在沟槽（11）的表面形成SiO 2层（12）并在边缘（8）处产生电容器电极（13），在通过去除（1）的Si 3 N 4间隔物（10）。

32. 发明授权

US06459123B1 Double gated transistor 有权
标题翻译：双门控晶体管
公开(公告)号：US06459123B1
公开(公告)日：2002-10-01
申请号：US09302768
申请日：1999-04-30
申请人： Gerhard Enders , Thomas Schulz , Dietrich Widmann , Lothar Risch
发明人： Gerhard Enders , Thomas Schulz , Dietrich Widmann , Lothar Risch
IPC分类号： H01L2994
CPC分类号： H01L27/11 , H01L21/823885 , H01L27/092 , H01L27/1104 , H01L27/1203
摘要： A semiconductor body having a pair of vertical, double-gated CMOS transistors. An insulating layer extending horizontally beneath the surface of the semiconductor body such insulating layer being disposed beneath the pair of transistors. The transistors, together with additional such transistors, are arranged to form a Synchronous Dynamic Random Access Memory (SRAM) array. The array includes a plurality of SRAM cells arranged in rows and columns, each one of the cells having a WORDLINE connected to a WORLDINE CONTACT. The WORDLINE CONTACT is common to four contiguous one of the cells. One of the cells having a plurality of electrically interconnected MOS transistors arranged to provide an SRAM circuit. Each one of the cells has a VDD CONTACT and a VSS CONTACT. One of such CONTACTs is disposed centrally within each one of the cells and the other one of the CONTACTs being common to four contiguous ones of the cells. Each one of the cells has the common one of the CONTACTs and the WORDLINE CONTACT disposed at peripheral, corner regions of the cell.
摘要翻译：具有一对垂直双门控CMOS晶体管的半导体本体。在半导体本体的表面下水平延伸的绝缘层，该绝缘层设置在该对晶体管的下方。晶体管与附加的这种晶体管一起被布置成形成同步动态随机存取存储器（SRAM）阵列。阵列包括以行和列排列的多个SRAM单元，每个单元都具有连接到WORLDINE CONTACT的WORDLINE。 WORDLINE CONTACT是四个连续的一个单元格共同的。具有多个电互连的MOS晶体管的单元之一被布置成提供SRAM电路。每个单元都有一个VDD CONTACT和一个VSS CONTACT。这种CONTACT之一被布置在每个单元格的中心并且另一个CONTACT被四个相邻的单元共同。每个单元格具有共同的一个CONTACT和WORDLINE CONTACT放置在单元的外围角区域。

33. 发明授权

US06503784B1 Double gated transistor 有权
标题翻译：双门控晶体管
公开(公告)号：US06503784B1
公开(公告)日：2003-01-07
申请号：US09670742
申请日：2000-09-27
申请人： Gerhard Enders , Thomas Schulz , Dietrich Widmann , Lothar Risch
发明人： Gerhard Enders , Thomas Schulz , Dietrich Widmann , Lothar Risch
IPC分类号： H01L218238
CPC分类号： H01L27/11 , H01L21/823885 , H01L27/092 , H01L27/1104 , H01L27/1203
摘要： A semiconductor body-having a pair of vertical, double-gated CMOS transistors. An insulating layer extending horizontally beneath the surface of the semiconductor body such insulating layer being disposed beneath the pair of transistors. The transistors, together with additional such transistors, are arranged to form a Synchronous Dynamic Random Access Memory (SRAM) array. The array includes a plurality of SRAM cells arranged in rows and columns, each one of the cells having a WORDLINE connected to a WORLDINE CONTACT. The WORDLINE CONTACT is common to four contiguous one of the cells. One of the cells having a plurality of electrically interconnected MOS transistors arranged to provide an SRAM circuit. Each one of the cells has a VDD CONTACT and a VSS CONTACT. One of such CONTACTs is disposed centrally within each one of the cells and the other one of the CONTACTs being common to four contiguous ones of the cells. Each one of the cells has the common one of the CONTACTs and the WORDLINE CONTACT disposed at peripheral, corner regions of the cell.
摘要翻译：一种具有一对垂直双门控CMOS晶体管的半导体体。在半导体本体的表面下水平延伸的绝缘层，该绝缘层设置在该对晶体管的下方。晶体管与附加的这种晶体管一起被布置成形成同步动态随机存取存储器（SRAM）阵列。阵列包括以行和列排列的多个SRAM单元，每个单元都具有连接到WORLDINE CONTACT的WORDLINE。 WORDLINE CONTACT是四个连续的一个单元格共同的。具有多个电互连的MOS晶体管的单元之一被布置成提供SRAM电路。每个单元都有一个VDD CONTACT和一个VSS CONTACT。这种CONTACT之一被布置在每个单元格的中心并且另一个CONTACT被四个相邻的单元共同。每个单元格具有共同的一个CONTACT和WORDLINE CONTACT放置在单元的外围角区域。

34. 发明授权

US06472767B1 Static random access memory (SRAM) 有权
标题翻译：静态随机存取存储器（SRAM）
公开(公告)号：US06472767B1
公开(公告)日：2002-10-29
申请号：US09302757
申请日：1999-04-30
申请人： Gerhard Enders , Thomas Schulz , Dietrich Widmann , Lothar Risch
发明人： Gerhard Enders , Thomas Schulz , Dietrich Widmann , Lothar Risch
IPC分类号： H01L2711
CPC分类号： H01L27/11 , H01L27/1104
摘要： A semiconductor body having a pair of vertical, double-gated CMOS transistors. An insulating layer extending horizontally beneath the surface of the semiconductor body such insulating layer being disposed beneath the pair of transistors. The transistors, together with additional such transistors, are arranged to form a Synchronous Dynamic Random Access Memory (SRAM) array. The array includes a plurality of SRAM cells arranged in rows and columns, each one of the cells having a WORDLINE connected to a WORLDINE CONTACT. The WORDLINE CONTACT is common to four contiguous one of the cells. One of the cells having a plurality of electrically interconnected MOS transistors arranged to provide an SRAM circuit. Each one of the cells has a VDD CONTACT and a VSS CONTACT. One of such CONTACTs is disposed centrally within each one of the cells and the other one of the CONTACTs being common to four contiguous ones of the cells. Each one of the cells has the common one of the CONTACTs and the WORDLINE CONTACT disposed at peripheral, corner regions of the cell.
摘要翻译：具有一对垂直双门控CMOS晶体管的半导体本体。在半导体本体的表面下水平延伸的绝缘层，该绝缘层设置在该对晶体管的下方。晶体管与附加的这种晶体管一起被布置成形成同步动态随机存取存储器（SRAM）阵列。阵列包括以行和列排列的多个SRAM单元，每个单元都具有连接到WORLDINE CONTACT的WORDLINE。 WORDLINE CONTACT是四个连续的一个单元格共同的。具有多个电互连的MOS晶体管的单元之一被布置成提供SRAM电路。每个单元都有一个VDD CONTACT和一个VSS CONTACT。这种CONTACT之一被布置在每个单元格的中心并且另一个CONTACT被四个相邻的单元共同。每个单元格具有共同的一个CONTACT和WORDLINE CONTACT放置在单元的外围角区域。

35. 发明授权

US6038164A SRAM cell configuration and method for its fabrication 有权
标题翻译： SRAM单元配置及其制造方法
公开(公告)号：US6038164A
公开(公告)日：2000-03-14
申请号：US200071
申请日：1998-11-25
申请人： Thomas Schulz , Thomas Aeugle , Wolfgang Rosner , Lothar Risch
发明人： Thomas Schulz , Thomas Aeugle , Wolfgang Rosner , Lothar Risch
IPC分类号： H01L21/8244 , H01L27/11 , G11C11/00
CPC分类号： H01L27/11 , H01L27/1104
摘要： The SRAM cell configuration has at least six transistors in each memory cell. Four of the transistors form a flip-flop and they are arranged at the corners of a quadrilateral. The flip-flop is driven by two of the transistors, which are disposed so as to adjoin diagonally opposite corners of the quadrilateral and outside the quadrilateral. Adjacent memory cells along a word line can be arranged in such a way that a first bit line and a second bit line of the adjacent memory cells coincide. The transistors are preferably vertical and are arranged at semiconductor structures (St1, St2, St3, St4, St5, St6) produced from a layer sequence. Two of the transistors having n-doped channel regions are preferably formed in each case on two semiconductor structures.
摘要翻译： SRAM单元配置在每个存储单元中具有至少六个晶体管。四个晶体管形成触发器，并且它们被布置在四边形的角部。触发器由两个晶体管驱动，这些晶体管被设置为邻接四边形的对角线相对的角部并且在四边形之外。沿着字线的相邻存储器单元可以以相邻存储器单元的第一位线和第二位线重合的方式布置。晶体管优选是垂直的，并且被布置在从层序列产生的半导体结构（St1，St2，St3，St4，St5，St6）处。在每种情况下，优选在两个半导体结构上形成具有n掺杂沟道区的两个晶体管。

36. 发明授权

US6060911A Circuit arrangement with at least four transistors, and method for the manufacture thereof 有权
标题翻译：具有至少四个晶体管的电路布置及其制造方法
公开(公告)号：US6060911A
公开(公告)日：2000-05-09
申请号：US138160
申请日：1998-08-21
申请人： Thomas Schulz , Thomas Aeugle , Wolfgang Roesner , Lothar Risch
发明人： Thomas Schulz , Thomas Aeugle , Wolfgang Roesner , Lothar Risch
IPC分类号： G11C16/04 , H01L21/8238 , H01L27/092 , H01L29/78 , H03K19/094 , H01L29/76
CPC分类号： H01L27/092 , H01L21/823885
摘要： In the circuit arrangement two of the four vertical transistors are complementary to the remaining two transistors. Two of the transistors are respectively arranged at the same level. For this purpose, layer structures (St1, St2, St3, St4) are structured that respectively have at least a channel layer and a source/drain region of one of the transistors. All the layer structures (St1, St2, St3, St4) can be produced from a layer sequence with only four layers. In order to avoid leakage currents due to a parasitic bipolar transistor, the layer structures (St1, St2, St3, St4) can be realized very thinly, using spacer-type masks. Electrical connections between parts of the four transistors can take place via layers of the layer sequence. The contacting to the output voltage terminal can take place via a step that is formed by two layers of the layer sequence.
摘要翻译：在电路布置中，四个垂直晶体管中的两个与剩余的两个晶体管互补。两个晶体管分别布置在相同的电平上。为此，层结构（St1，St2，St3，St4）被构造成分别具有至少一个晶体管的沟道层和源极/漏极区域。所有的层结构（St1，St2，St3，St4）可以仅由四层制成。为了避免由寄生双极型晶体管引起的漏电流，使用间隔型掩模，可以非常薄地实现层结构（St1，St2，St3，St4）。四个晶体管的部分之间的电连接可以通过层序列的层进行。与输出电压端子的接触可以通过由层序列的两层形成的步骤进行。

37. 发明授权

US06600200B1 MOS transistor, method for fabricating a MOS transistor and method for fabricating two complementary MOS transistors 有权
标题翻译： MOS晶体管，制造MOS晶体管的方法和制造两个互补MOS晶体管的方法
公开(公告)号：US06600200B1
公开(公告)日：2003-07-29
申请号：US09645762
申请日：2000-08-25
申请人： Bernhard Lustig , Herbert Schäfer , Lothar Risch
发明人： Bernhard Lustig , Herbert Schäfer , Lothar Risch
IPC分类号： H01L2906
CPC分类号： H01L21/823807 , H01L21/74 , H01L29/1083
摘要： A MOS transistor and a method for fabricating the same include producing a well doped by a first conductivity type in a semiconductor substrate. An epitaxial layer having a dopant concentration of less than 1017 cm−3 is disposed on a surface of the doped well. Source/drain regions doped by a second conductivity type, opposite to the first conductivity type, and a channel region, are disposed in the epitaxial layer, and their depth is less than or equal to the thickness of the epitaxial layer. A method for fabricating two complementary MOS transistors is also provided.
摘要翻译： MOS晶体管及其制造方法包括在半导体衬底中制造由第一导电类型掺杂的阱。掺杂浓度小于1017cm-3的外延层设置在掺杂阱的表面上。由第二导电类型掺杂的与第一导电类型相反的源极/漏极区和沟道区设置在外延层中，并且它们的深度小于或等于外延层的厚度。还提供了制造两个互补MOS晶体管的方法。

38. 发明授权

US4966859A Voltage-stable sub-.mu.m MOS transistor for VLSI circuits 失效
标题翻译：用于VLSI电路的稳压亚微米MOS晶体管
公开(公告)号：US4966859A
公开(公告)日：1990-10-30
申请号：US293567
申请日：1989-01-03
申请人： Lothar Risch , Reinhard Tielert , Wolfgang Mueller , Christoph Werner
发明人： Lothar Risch , Reinhard Tielert , Wolfgang Mueller , Christoph Werner
IPC分类号： H01L21/265 , H01L29/10 , H01L29/78
CPC分类号： H01L29/1083 , H01L29/105 , H01L29/78 , Y10S148/126
摘要： A voltage-stable sub-.mu.m-MOS transistor for VLSI circuits consist of a low-resistant silicon substrate of a first conductivity type with a high-resistant, thin, epitaxial layer of the first conductivity type situated thereon and on which a gate electrode consisting of polysilicon is disposed. Highly doped source/drain zones of the second conductivity type form a channel region of the first conductivity type. A doping substance concentration, rising in the direction of the substrate, is generated by means of double implantation, whereby the concentration maximum extends to behind the source/drain zones. A method for manufacturing same incorporates steps of forming the several layers, applying a mask, executing a double implantation in the channel region, and forming the gate electrode.
摘要翻译：用于VLSI电路的稳压子MOS-MOS晶体管由具有第一导电类型的低电阻硅衬底和位于其上的第一导电类型的高电阻，薄外延层组成，栅电极由多晶硅组成。第二导电类型的高掺杂源/漏区形成第一导电类型的沟道区。通过双重注入产生沿衬底方向上升的掺杂物质浓度，由此浓度最大值延伸到源极/漏极区之后。其制造方法包括形成几层的步骤，施加掩模，在沟道区域中执行双注入，以及形成栅电极。

39. 发明授权

US4823180A Photo-transistor in MOS thin-film technology and method for production and operation thereof 失效
标题翻译： MOS薄膜技术中的光电晶体管及其生产和操作方法
公开(公告)号：US4823180A
公开(公告)日：1989-04-18
申请号：US437302
申请日：1982-10-28
申请人： Armin Wieder , Lothar Risch
发明人： Armin Wieder , Lothar Risch
IPC分类号： H01L31/10 , H01L29/04 , H01L31/113 , H01L27/14
CPC分类号： H01L29/04 , H01L31/1136
摘要： A photo-transistor in MOS thin-film technology operable with alternating voltages is comprised of a semiconductor body (3) composed of polycrystalline silicon having source (4) and drain (5) zones therein spaced apart by an undoped channel region (13) and having a gate electrode (1, 10) separated from the semiconductor body (3) by a SiO.sub.2 layer (2) produced by thermal oxidation. These phototransistors are easily and reproducably produced and are characterized by low threshold voltages and a good transistor characteristic curve. Thus, these photo-transistors are well suited for use as sensor elements, opto-couplers, time-delay elements and as photo-transistors in VLSI circuits.
摘要翻译：可以用交流电压工作的MOS薄膜技术的光电晶体管由半导体本体（3）组成，半导体本体（3）由多晶硅构成，多晶硅具有由未掺杂沟道区（13）间隔的源极（4）和漏极（5）具有通过由热氧化产生的SiO 2层（2）与半导体本体（3）分离的栅电极（1,10）。这些光电晶体管容易且可再生产，其特征在于低阈值电压和良好的晶体管特性曲线。因此，这些光电晶体管非常适合用作VLSI电路中的传感器元件，光耦合器，延时元件和光电晶体管。

40. 发明授权

US06262448B1 Memory cell having trench capacitor and vertical, dual-gated transistor 失效
标题翻译：存储单元具有沟槽电容器和垂直双门控晶体管
公开(公告)号：US06262448B1
公开(公告)日：2001-07-17
申请号：US09302756
申请日：1999-04-30
申请人： Gerhard Enders , Matthias Ilg , Lothar Risch , Dietrich Widmann
发明人： Gerhard Enders , Matthias Ilg , Lothar Risch , Dietrich Widmann
IPC分类号： H01L27108
CPC分类号： H01L27/10864 , H01L27/10841 , H01L27/10876
摘要： A DRAM cell is disposed in an electrically isolated region of a semiconductor body. The cell includes a storage capacitor disposed in a trench. The capacitor is disposed entirely within the isolated region of the semiconductor body. The cell includes a transistor disposed in the isolated region. The transistor has a pair of gates. A word line is provided for addressing the cell. The word line has an electrical contact region to the transistor. The word line contact region is disposed entirely within the isolated region of the semiconductor body. The transistor has an active area. The active area has source, drain, and channel regions. The active area is disposed entirely within the isolated region of the semiconductor body. A bit line is provided for the cell. The bit line is in electrical contact with the gates of the transistor at a pair of bit line contact regions. Both such bit line contact regions are disposed entirely within the isolated region of the cell. With such an arrangement a DRAM cell is provided having a relatively occupies a relatively small amount of surface area of the semiconductor body.
摘要翻译： DRAM单元设置在半导体本体的电隔离区域中。电池包括设置在沟槽中的存储电容器。电容器完全设置在半导体本体的隔离区域内。电池包括设置在隔离区域中的晶体管。晶体管有一对门。提供字线用于寻址单元。字线具有到晶体管的电接触区域。字线接触区域完全设置在半导体本体的隔离区域内。晶体管有一个有源区。有源区域有源极，漏极和沟道区域。有源区域完全设置在半导体本体的隔离区域内。为单元提供位线。位线在一对位线接触区域与晶体管的栅极电接触。两个这样的位线接触区域完全设置在电池的隔离区域内。通过这样的布置，提供了DRAM单元，其具有相对占据半导体本体的较小量的表面积。

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