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31. 发明授权

US06521524B1 Via filled dual damascene structure with middle stop layer and method for making the same 有权
标题翻译：通过填充中间停止层的双镶嵌结构和制作相同的方法
公开(公告)号：US06521524B1
公开(公告)日：2003-02-18
申请号：US09778070
申请日：2001-02-07
申请人： Fei Wang , Lynne A. Okada , Ramkumar Subramanian , Calvin T. Gabriel
发明人： Fei Wang , Lynne A. Okada , Ramkumar Subramanian , Calvin T. Gabriel
IPC分类号： H01L214763
CPC分类号： H01L21/76835 , H01L21/76808 , H01L2221/1031
摘要： An interconnect structure and method of forming the same in which an inorganic low k dielectric material is deposited over a conductive layer to form a first dielectric layer. An etch stop layer is formed on the first dielectric layer. The etch stop layer and the first dielectric layer are etched to form a via in the first dielectric layer. An organic low k dielectric material is deposited within the via and over the etch stop layer to form a second dielectric layer over the via and the etch stop layer. The re-filled via is simultaneously etched with the second dielectric layer in which a trench is formed. A portion of the trench is directly over the via. The re-opened via and the trench are filled with a conductive material.
摘要翻译：一种互连结构及其形成方法，其中无机低k电介质材料沉积在导电层上以形成第一介电层。在第一电介质层上形成蚀刻停止层。蚀刻停止层和第一介电层被蚀刻以在第一介电层中形成通孔。有机低k介电材料沉积在通孔内和蚀刻停止层上方，以在通孔和蚀刻停止层上方形成第二电介质层。再次填充的通孔与其中形成沟槽的第二电介质层同时蚀刻。沟槽的一部分直接在通孔的上方。重新打开的通孔和沟槽填充有导电材料。

32. 发明授权

US06380092B1 Gas phase planarization process for semiconductor wafers 失效
标题翻译：半导体晶圆的气相平面化处理
公开(公告)号：US06380092B1
公开(公告)日：2002-04-30
申请号：US09516333
申请日：2000-03-01
申请人： Rao V. Annapragada , Calvin T. Gabriel , Milind G. Weling
发明人： Rao V. Annapragada , Calvin T. Gabriel , Milind G. Weling
IPC分类号： H01L21302
CPC分类号： B24B7/228 , B24D13/14 , H01L21/31053
摘要： A gas phase planarization process for semiconductor wafers. The present invention comprises a system and method of dry planarization for a semiconductor wafer. For instance, the present invention includes a system adapted to effectively remove all, or a portion of, a layer of dielectric material of a semiconductor wafer through the application of dry abrasion and dry chemistry. As such, a present invention system flattens out height differences of the dielectric material, since high areas of topography are removed faster than low areas. Specifically, one embodiment of the present invention utilizes a dry abrasive polishing pad to abrade the desired surface of the semiconductor wafer within a vacuum planarization chamber. As a result of abrading the surface, the abrasive polishing pad breaks the chemical bonds of a thin layer of the dielectric surface material. Once the chemical bonds are broken, reactive radicals within a plasma gas chemically react with the surface material thereby forming a gaseous species which is highly volatile. In other words, the plasma gas is used to remove previously mechanically polished material from the dielectric layer. Subsequently, the newly formed gaseous species is removed from the vacuum planarization chamber. This process of removing material from the surface of the semiconductor wafer continues until the surface is sufficiently planarized. In this manner, the present invention provides a dry process for planarizing a surface of a semiconductor wafer.
摘要翻译：一种用于半导体晶片的气相平面化工艺。本发明包括用于半导体晶片的干式平坦化的系统和方法。例如，本发明包括适于通过施加干磨和干化学来有效地去除半导体晶片的电介质材料层的全部或一部分的系统。因此，本发明的系统平坦化电介质材料的高度差异，因为比低面积更快地除去高面积的形貌。具体地，本发明的一个实施例利用干研磨抛光垫在真空平坦化室内研磨半导体晶片的期望表面。研磨抛光垫的结果是磨损表面，破坏了电介质表面材料薄层的化学键。一旦化学键断裂，等离子体气体内的反应性基团就会与表面材料发生化学反应，从而形成高挥发性的气态物质。换句话说，等离子体气体用于从电介质层去除先前机械抛光的材料。随后，将新形成的气态物质从真空平坦化室中除去。从半导体晶片的表面去除材料的过程继续进行，直到表面被充分平坦化。以这种方式，本发明提供了用于使半导体晶片的表面平坦化的干法。

33. 发明授权

US6103457A Method for reducing faceting on a photoresist layer during an etch process 失效
标题翻译：在蚀刻过程中减少光致抗蚀剂层上的刻面的方法
公开(公告)号：US6103457A
公开(公告)日：2000-08-15
申请号：US86700
申请日：1998-05-28
申请人： Calvin T. Gabriel
发明人： Calvin T. Gabriel
IPC分类号： G03F7/40 , H01L21/027 , H01L21/3105 , H01L21/3213 , H01L23/532 , G03F7/26
CPC分类号： G03F7/40 , H01L21/0273 , H01L21/0276 , H01L21/3105 , H01L21/32139 , H01L23/53223 , H01L2924/0002
摘要： Disclosed is a method for reducing faceting of a photoresist layer during an etch process. The method includes depositing a metallization layer on a semiconductor substrate, and forming a photoresist layer over at least a portion of the metallization layer. The method also includes treating the photoresist layer with a first plasma so as to harden the photoresist layer against a metal etching plasma. The method further includes exposing the metallization layer and the photoresist layer to the metal etching plasma. The metal etching plasma etches the metallization layer at a substantially faster rate than the treated photoresist layer so that faceting on the photoresist layer is substantially reduced.
摘要翻译：公开了一种在蚀刻过程中减少光致抗蚀剂层的刻面的方法。该方法包括在半导体衬底上沉积金属化层，并在金属化层的至少一部分上形成光致抗蚀剂层。该方法还包括用第一等离子体处理光致抗蚀剂层，以使光致抗蚀剂层硬化以抵抗金属蚀刻等离子体。该方法还包括将金属化层和光致抗蚀剂层暴露于金属蚀刻等离子体。金属蚀刻等离子体以比经处理的光致抗蚀剂层快得多的速度蚀刻金属化层，使得光刻胶层上的刻面显着减少。

34. 发明授权

US5420796A Method of inspecting planarity of wafer surface after etchback step in integrated circuit fabrication 失效
标题翻译：在集成电路制造中的回蚀步骤之后检查晶片表面的平面度的方法
公开(公告)号：US5420796A
公开(公告)日：1995-05-30
申请号：US173581
申请日：1993-12-23
申请人： Milind Weling , Calvin T. Gabriel
发明人： Milind Weling , Calvin T. Gabriel
IPC分类号： G01Q60/00 , H01L21/66 , G06F15/46 , H01J3/14
CPC分类号： B82Y15/00 , H01L22/12 , Y10S977/854
摘要： An integrated circuit (IC) fabrication process involves forming electronic devices on a semiconductor substrate. A metal layer is deposited thereover and then patterned to interconnect the semiconductor devices. A dielectric layer is deposited over the metal layer and substrate. The dielectric layer is etched back to prepare for the deposition of additional metal and dielectric layers. The etched surface is scanned by an atomic force microscope (AFM) to gather data representing the wafer surface roughness. The data is evaluated by a computer to generate at least one surface roughness signal. Depending on the value of the surface roughness signal, the IC fabrication process continues with the next step, a remedial action is taken, the IC fabrication process is adjusted for subsequent wafers, or the wafer is discarded.
摘要翻译：集成电路（IC）制造工艺涉及在半导体衬底上形成电子器件。金属层沉积在其上，然后被图案化以使半导体器件互连。电介质层沉积在金属层和衬底上。回蚀电介质层以准备附加的金属和电介质层的沉积。蚀刻的表面被原子力显微镜（AFM）扫描以收集表示晶片表面粗糙度的数据。数据由计算机评估以产生至少一个表面粗糙度信号。根据表面粗糙度信号的值，IC制造工艺继续下一步，采取补救措施，为随后的晶片调整IC制造工艺，或丢弃晶片。

35. 发明授权

US5405488A System and method for plasma etching endpoint detection 失效
标题翻译：等离子体蚀刻终点检测的系统和方法
公开(公告)号：US5405488A
公开(公告)日：1995-04-11
申请号：US120619
申请日：1993-09-13
申请人： Dimitrios Dimitrelis , Calvin T. Gabriel , Samuel V. Dunton
发明人： Dimitrios Dimitrelis , Calvin T. Gabriel , Samuel V. Dunton
IPC分类号： H01J37/32 , H01L21/306
CPC分类号： H01J37/32935 , H01J37/32963
摘要： A plasma etching endpoint detection system monitors two optical wavelengths during etching of a non-opaque dielectric film. A controller coupled to the optical monitoring equipment generates an endpoint detection signal corresponding to a predefined mathematical combination of the monitored intensity of light at the first wavelength and the monitored intensity of light at the second wavelength. When the endpoint detection signal crosses a threshold level, the etching of the dielectric layer is stopped. In a preferred embodiment the two monitored wavelengths differ by approximately a factor of two. More generally, the two monitored wavelengths are selected such that the combined intensity signal has a proportionally smaller false endpoint peak than either of the individual monitored intensity signals. The present invention is beneficial primarily for plasma etching systems in which the optical path of the optical monitoring equipment is not parallel to the surface of wafer being etched, which results in a premature or false endpoint signal produced by alternating constructive and destructive interference between reflected and refracted light.
摘要翻译：等离子体蚀刻终点检测系统在蚀刻非不透明电介质膜期间监测两个光学波长。耦合到光学监测设备的控制器产生对应于在第一波长处监测的光强度和第二波长的被监视光强度的预定数学组合的端点检测信号。当端点检测信号跨越阈值电平时，电介质层的蚀刻停止。在优选实施例中，两个被监测的波长相差大约二分之一。更一般地，选择两个被监测的波长，使得组合强度信号具有比任一个监视的强度信号成比例地较小的假端点峰值。本发明主要用于等离子体蚀刻系统，其中光学监测设备的光路不平行于被蚀刻的晶片的表面，这导致由反射和/或反射之间的交替的建构性和相消干涉产生的过早或错误的端点信号折射光

36. 发明授权

US07427457B1 Methods for designing grating structures for use in situ scatterometry to detect photoresist defects 有权
标题翻译：设计光栅结构的方法用于原位散射检测光刻胶缺陷
公开(公告)号：US07427457B1
公开(公告)日：2008-09-23
申请号：US10934277
申请日：2004-09-03
申请人： Marina V. Plat , Calvin T. Gabriel , Christopher F. Lyons , Anna M. Minvielle
发明人： Marina V. Plat , Calvin T. Gabriel , Christopher F. Lyons , Anna M. Minvielle
IPC分类号： G03F9/00
CPC分类号： G03F7/70783 , G03F1/44 , G03F7/70491 , G03F7/70533 , G03F7/7065
摘要： The present invention discloses a system and method for designing grating structures for use in situ scatterometry during the photolithography process to detect a photoresist defect (e.g., photoresist erosion, pattern collapse or pattern bending). In one embodiment, a grating structure may be designed with a pitch or critical dimensional smaller than the one used for the semiconductor device. The pitch and the critical dimension of the grating structure may be varied. In another embodiment, the present invention provides for a feedback mechanism between the in situ scatterometry process and the photolithography process to provide an early warning of the existence of a photoresist defect. If a defect is detected on the wafer, the wafer may be sent to be re-worked or re-patterned, thereby avoiding scrapping the entire wafer.
摘要翻译：本发明公开了一种用于在光刻工艺期间用于原位散射测量的光栅结构的系统和方法，用于检测光致抗蚀剂缺陷（例如，光致抗蚀剂侵蚀，图案崩溃或图案弯曲）。在一个实施例中，可以设计具有小于用于半导体器件的间距或临界尺寸的光栅结构。光栅结构的间距和临界尺寸可以变化。在另一个实施例中，本发明提供了原位散射测量过程和光刻工艺之间的反馈机制，以提供光刻胶缺陷的存在的早期警告。如果在晶片上检测到缺陷，则可以将晶片发送以进行再加工或重新图案化，从而避免报废整个晶片。

37. 发明授权

US07279429B1 Method to improve ignition in plasma etching or plasma deposition steps 失效
标题翻译：在等离子体蚀刻或等离子体沉积步骤中改善点火的方法
公开(公告)号：US07279429B1
公开(公告)日：2007-10-09
申请号：US10957340
申请日：2004-10-01
申请人： Calvin T. Gabriel , Tzu-Yen Hsieh
发明人： Calvin T. Gabriel , Tzu-Yen Hsieh
IPC分类号： H01L21/302
CPC分类号： C23C16/505 , H01J37/32082 , H01J37/32165
摘要： In one embodiment, the present invention relates to a method for increasing the ignition reliability of a plasma in a plasma reactor, the method comprising: supplying a source gas to the plasma reactor, the source gas comprising: (a) at least one reactive compound; and (b) at least one ignition gas, wherein the at least one ignition gas increases the ignitability of the source gas as compared to the ignitability of the source gas lacking the at least one ignition gas.
摘要翻译：在一个实施方案中，本发明涉及一种用于提高等离子体反应器中的等离子体的点火可靠性的方法，所述方法包括：将源气体供应至所述等离子体反应器，所述源气体包括：（a）至少一种反应性化合物 ; 和（b）至少一种点燃气体，其中与不含至少一种点燃气体的源气体的点火性相比，所述至少一种点火气体增加了源气体的点火性。

38. 发明授权

US06645679B1 Attenuated phase shift mask for use in EUV lithography and a method of making such a mask 有权
标题翻译：用于EUV光刻的衰减相移掩模和制造这种掩模的方法
公开(公告)号：US06645679B1
公开(公告)日：2003-11-11
申请号：US09803853
申请日：2001-03-12
申请人： Bruno M. La Fontaine , Calvin T. Gabriel , Harry J. Levinson , Kouros Ghandehari
发明人： Bruno M. La Fontaine , Calvin T. Gabriel , Harry J. Levinson , Kouros Ghandehari
IPC分类号： G03F900
CPC分类号： B82Y10/00 , B82Y40/00 , G03F1/24 , G03F1/26 , G03F1/32
摘要： An attenuated phase shift mask utilizes a multilayer which has been locally modified. Heat treatment or e-beam treatment can locally modify the multilayer to provide different reflective characteristics. The attenuated phase shift mask can be utilized in EUV applications.
摘要翻译：衰减相移掩模利用已被局部修改的多层。热处理或电子束处理可以局部改变多层以提供不同的反射特性。衰减相移掩模可用于EUV应用。

39. 发明授权

US06534397B1 Pre-treatment of low-k dielectric for prevention of photoresist poisoning 有权
标题翻译：预处理低k电介质以防止光致抗蚀剂中毒
公开(公告)号：US06534397B1
公开(公告)日：2003-03-18
申请号：US09903758
申请日：2001-07-13
申请人： Lynne A. Okada , Fei Wang , Calvin T. Gabriel
发明人： Lynne A. Okada , Fei Wang , Calvin T. Gabriel
IPC分类号： H01L214763
CPC分类号： H01L21/76826 , H01L21/76807
摘要： Deleterious poisoning of patterned photoresist masking layers accompanying plasma ashing/etching of photoresist and/or low-k dielectric layers is eliminated, or at least substantially reduced, by pretreating exposed surfaces of the low-k dielectric layer(s) with hydrogen, e.g., by contact with a hydrogen plasma prior to plasma ashing/etching. The invention enjoys particular utility in the formation of dual damascene openings in dielectric layers as part of metallization processing of semiconductor IC devices.
摘要翻译：通过用氢气预处理低k电介质层的暴露表面，消除了或至少大大减少了伴随等离子体灰度/蚀刻光刻胶和/或低k电介质层的图案化光刻胶掩模层的有害中毒，通过在等离子体灰化/蚀刻之前与氢等离子体接触。本发明在形成作为半导体IC器件的金属化处理的一部分的电介质层中的双镶嵌开口中具有特别的用途。

40. 发明授权

US06472231B1 Dielectric layer with treated top surface forming an etch stop layer and method of making the same 有权
标题翻译：具有处理的顶表面形成蚀刻停止层的介电层及其制造方法
公开(公告)号：US06472231B1
公开(公告)日：2002-10-29
申请号：US09770469
申请日：2001-01-29
申请人： Calvin T. Gabriel , Lynne A. Okada
发明人： Calvin T. Gabriel , Lynne A. Okada
IPC分类号： H01L2348
CPC分类号： H01L21/76829 , H01L21/76801 , H01L21/76807 , H01L21/76826 , H01L2221/1036
摘要： A metal interconnect arrangement provides a dielectric layer that has its upper surface treated to provide an etch stop etch stop layer. The upper surface is subjected to a plasma etch that treats, such as by carbonization, the dielectric material in a manner that alters the etch characteristics of the dielectric material. After a second dielectric layer is formed over the treated surface of the first dielectric layer, an etching may be performed through the second dielectric layer that stops on the treated surface of the first dielectric layer in a damascene interconnect process.
摘要翻译：金属互连装置提供了其上表面被处理以提供蚀刻停止蚀刻停止层的电介质层。对上表面进行等离子体蚀刻，其以改变介电材料的蚀刻特性的方式例如通过碳化处理电介质材料。在第一电介质层的经处理的表面上形成第二电介质层之后，可以通过在大马士革互连工艺中在第一介电层的处理表面上停止的第二介电层进行蚀刻。

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