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31. 发明申请

US20130297981A1 LOW COST HIGH THROUGHPUT TSV/MICROBUMP PROBE 审中-公开
标题翻译：低成本高通量TSV / MICROBUMP探头
公开(公告)号：US20130297981A1
公开(公告)日：2013-11-07
申请号：US13537528
申请日：2012-06-29
申请人： Shiqun Gu , Michael Laisne , Matthew M. Nowak , Glen T. Kim , Mark C. Chan , Hongjun Yao
发明人： Shiqun Gu , Michael Laisne , Matthew M. Nowak , Glen T. Kim , Mark C. Chan , Hongjun Yao
IPC分类号： G01R31/3177
CPC分类号： G01R31/3177 , H01L22/34 , H01L23/3128 , H01L2224/16227 , H01L2924/15192 , H01L2924/15311
摘要： A first apparatus, such as a die or a semiconductor package, has signal paths extending through the apparatus. The signal paths can include through vias and other components. The signal paths are operable to communicate with a second apparatus when the second apparatus is stacked with the first apparatus. The first apparatus also has pass gates. Each pass gate is configurable in response to a signal, to short a pair of the signal paths to enable substantially simultaneous testing of the signal paths. The pass gates may be configurable to isolate the signal paths during operation of the first apparatus.
摘要翻译：诸如裸片或半导体封装的第一装置具有延伸穿过该装置的信号路径。信号路径可以包括通孔和其它组件。当第二装置与第一装置堆叠时，信号路径可操作以与第二装置通信。第一个装置也有通过门。每个通过门可以响应于信号而配置，以缩短一对信号路径以实现信号路径的基本上同时的测试。通过门可以被配置为在第一设备的操作期间隔离信号路径。

32. 发明授权

US08508301B2 Three dimensional inductor, transformer and radio frequency amplifier 有权
标题翻译：三维电感，变压器和射频放大器
公开(公告)号：US08508301B2
公开(公告)日：2013-08-13
申请号：US13294351
申请日：2011-11-11
申请人： Jonghae Kim , Shiqun Gu , Brian Matthew Henderson , Thomas R. Toms , Lew G. Chua-Eoan , Seyfollah S. Bazarjani , Matthew Nowak
发明人： Jonghae Kim , Shiqun Gu , Brian Matthew Henderson , Thomas R. Toms , Lew G. Chua-Eoan , Seyfollah S. Bazarjani , Matthew Nowak
IPC分类号： H03F3/14
CPC分类号： H01L28/10 , H01F17/0013 , H01F19/04 , H01F2017/002 , H01L23/481 , H01L23/5227 , H01L27/0207 , H01L2224/16145 , H01L2924/3011
摘要： A three dimensional on-chip radio frequency amplifier is disclosed that includes first and second transformers and a first transistor. The first transformer includes first and second inductively coupled inductors. The second transformer includes third and fourth inductively coupled inductors. Each inductor includes multiple first segments in a first metal layer; multiple second segments in a second metal layer; first and second inputs, and multiple through vias coupling the first and second segments to form a continuous path between the first and second inputs. The first input of the first inductor is coupled to an amplifier input; the first input of the second inductor is coupled to the first transistor gate; the first input of the third inductor is coupled to the first transistor drain, the first input of the fourth inductor is coupled to an amplifier output. The second inductor inputs and the first transistor source are coupled to ground.
摘要翻译：公开了一种三维片上射频放大器，其包括第一和第二变压器和第一晶体管。第一变压器包括第一和第二电感耦合电感器。第二变压器包括第三和第四电感耦合电感器。每个电感器包括在第一金属层中的多个第一段; 第二金属层中的多个第二段; 第一和第二输入以及耦合第一和第二段的多通孔，以形成第一和第二输入之间的连续路径。第一电感器的第一输入耦合到放大器输入端; 第二电感器的第一输入耦合到第一晶体管栅极; 第三电感器的第一输入耦合到第一晶体管漏极，第四电感器的第一输入耦合到放大器输出端。第二电感器输入和第一晶体管源耦合到地。

33. 发明申请

US20120112312A1 Integrated Circuit Chip Customization Using Backside Access 有权
标题翻译：集成电路芯片定制使用背面访问
公开(公告)号：US20120112312A1
公开(公告)日：2012-05-10
申请号：US12939439
申请日：2010-11-04
申请人： Daniel W. Perry , Shiqun Gu
发明人： Daniel W. Perry , Shiqun Gu
IPC分类号： H01L27/00 , H01L21/44
CPC分类号： H01L21/76898 , G11C11/16 , G11C13/0002 , G11C17/16 , H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit, a method for making an integrated circuit product, and methods for customizing an integrated circuit are disclosed. Integrated circuit elements including programmable elements, such as fuses, PROMs, RRAMs, MRAMs, or the like, are formed on the frontside of a substrate. Vias are formed through the substrate from its frontside to its backside to establish conduction paths to at least some of the programmable elements from the backside. A programming stimulus is applied to at least some of the vias from the backside to program at least some of the frontside programmable elements.
摘要翻译：公开了集成电路，制造集成电路产品的方法以及用于定制集成电路的方法。包括诸如保险丝，PROM，RRAM，MRAM等可编程元件的集成电路元件形成在衬底的前侧。通孔从其前侧到其背面通过衬底形成，从背面建立至少一些可编程元件的传导路径。编程刺激从后侧应用于至少一些通孔，以编程前端可编程元件中的至少一些。

34. 发明申请

US20120054423A1 Load Balancing Scheme In Multiple Channel DRAM Systems 有权
标题翻译：多通道DRAM系统中的负载平衡方案
公开(公告)号：US20120054423A1
公开(公告)日：2012-03-01
申请号：US12872282
申请日：2010-08-31
申请人： Feng Wang , Shiqun Gu , Jonghae Kim , Matthew Michael Nowak
发明人： Feng Wang , Shiqun Gu , Jonghae Kim , Matthew Michael Nowak
IPC分类号： G06F12/02
CPC分类号： G06F13/1647 , G06F12/0607 , G06F13/1642 , G06F13/1657 , G06F2213/0064
摘要： A load balancing in a multiple DRAM system comprises interleaving memory data across two or more memory channels. Access to the memory channels is controlled by memory controllers. Bus masters are coupled to the memory controllers via an interconnect system and memory requests are transmitted from the bus masters to the memory controller. If congestion is detected in a memory channel, congestion signals are generated and transmitted to the bus masters. Memory requests are accordingly withdrawn or rerouted to less congested memory channels based on the congestion signals.
摘要翻译：多个DRAM系统中的负载平衡包括跨两个或多个存储器通道交织存储器数据。内存通道的访问由内存控制器控制。总线主机通过互连系统耦合到存储器控制器，并且存储器请求从总线主机传送到存储器控制器。如果在存储器通道中检测到拥塞，则产生拥塞信号并将其发送到总线主机。因此，基于拥塞信号，存储器请求被相应地撤回或重新路由到较不拥塞的存储器通道。

35. 发明申请

US20120040509A1 Techniques for Placement of Active and Passive Devices within a Chip 有权
标题翻译：主动和被动设备放置在芯片内的技术
公开(公告)号：US20120040509A1
公开(公告)日：2012-02-16
申请号：US13279570
申请日：2011-10-24
申请人： Jonghae Kim , Shiqun Gu , Brian Matthew Henderson , Thomas R. Toms , Matthew Nowak
发明人： Jonghae Kim , Shiqun Gu , Brian Matthew Henderson , Thomas R. Toms , Matthew Nowak
IPC分类号： H01L21/02
CPC分类号： H01L27/0617 , H01L23/481 , H01L23/5223 , H01L23/5227 , H01L27/0688 , H01L28/10 , H01L28/40 , H01L2924/0002 , H01L2924/00
摘要： A method for manufacturing a semiconductor device includes fabricating an active layer on a first side of a semiconductor substrate. The method also includes fabricating a metal layer on a second side of the semiconductor substrate. The metal layer includes a passive device embedded within the metal layer. The passive device can electrically couple to the active layer with through vias.
摘要翻译：一种制造半导体器件的方法包括在半导体衬底的第一侧上制造有源层。该方法还包括在半导体衬底的第二侧上制造金属层。金属层包括嵌入金属层内的无源器件。无源器件可以通过通孔电耦合到有源层。

36. 发明申请

US20110229687A1 Through Glass Via Manufacturing Process 审中-公开
标题翻译：通过玻璃制造工艺
公开(公告)号：US20110229687A1
公开(公告)日：2011-09-22
申请号：US12727775
申请日：2010-03-19
申请人： Shiqun Gu , Xia Li , Yiming Li
发明人： Shiqun Gu , Xia Li , Yiming Li
IPC分类号： B32B3/10 , B44C1/22
CPC分类号： H01L23/15 , H01L21/486 , H01L23/49827 , H01L2924/0002 , H05K3/0041 , Y10T428/24273 , H01L2924/00
摘要： Fabrication of a through glass via in a relatively thick glass substrate includes patterning a through glass via hard mask on a surface of the glass substrate. The fabrication also includes wet etching a portion of the glass substrate, through the hard mask, to create a partial through glass via. The wet etching may involve applying a vapor of an oxide etch chemical, such as HF and XeF6, or applying a wet oxide etch chemical, such as HF and XeF6. The fabrication further includes passivating the etched partial through glass via, removing bottom passivation from the partial through glass via, and repeating the etching, passivating and removing to create the through glass via. The resulting through glass via has a scalloped side wall, a vertical profile and a high aspect ratio.
摘要翻译：在相对厚的玻璃基板中制造直通玻璃通孔包括在玻璃基板的表面上通过硬掩模图案化通孔玻璃。该制造还包括通过硬掩模湿法蚀刻玻璃基底的一部分，以产生部分透过玻璃通孔。湿蚀刻可以包括施加氧化物蚀刻化学品的蒸气，例如HF和XeF 6，或者施加湿氧化物蚀刻化学品，例如HF和XeF 6。该制造还包括钝化蚀刻的部分通过玻璃通孔，从部分通过玻璃通孔去除底部钝化，并重复蚀刻，钝化和去除以产生通孔玻璃通孔。所产生的通过玻璃通孔具有扇形侧壁，垂直轮廓和高纵横比。

37. 发明申请

US20110227230A1 THROUGH-SILICON VIA FABRICATION WITH ETCH STOP FILM 审中-公开
标题翻译：通过硅胶制成的薄膜
公开(公告)号：US20110227230A1
公开(公告)日：2011-09-22
申请号：US12727750
申请日：2010-03-19
申请人： Shiqun Gu , Yiming Li , Urmi Ray
发明人： Shiqun Gu , Yiming Li , Urmi Ray
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L21/76898
摘要： For a semiconductor wafer substrate having an inter layer dielectric, a through-silicon via may be formed in the substrate by first depositing an etch stop film on top of the inter layer dielectric, followed by etching an opening through the etch stop film, the interlayer dielectric, and into the substrate. A dielectric liner is then deposited over the etch stop film and into the opening. For some embodiments, the dielectric liner may be etched away except for those portions adhering to the sidewall of the opening. Then a conductive material may be deposited into the opening and on the etch stop film. The excess conductive material may then be removed, and for some embodiments the etch stop film may also be removed.
摘要翻译：对于具有层间电介质的半导体晶片衬底，可以在衬底中形成通硅通孔，首先在层间电介质的顶部上沉积蚀刻停止膜，然后蚀刻通过蚀刻停止膜，中间层电介质，并进入衬底。然后将电介质衬垫沉积在蚀刻停止膜上并进入开口中。对于一些实施例，除了粘附到开口的侧壁上的那些部分之外，电介质衬垫可被蚀刻掉。然后可以将导电材料沉积到开口中和蚀刻停止膜上。然后可以除去过量的导电材料，并且对于一些实施例，也可以去除蚀刻停止膜。

38. 发明授权

US08004881B2 Magnetic tunnel junction device with separate read and write paths 有权
标题翻译：具有独立读写路径的磁隧道结设备
公开(公告)号：US08004881B2
公开(公告)日：2011-08-23
申请号：US11959797
申请日：2007-12-19
申请人： Xiaochun Zhu , Shiqun Gu , Xia Li , Seung H. Kang
发明人： Xiaochun Zhu , Shiqun Gu , Xia Li , Seung H. Kang
IPC分类号： G11C11/00
CPC分类号： G11C11/1675 , G11C11/161 , G11C11/1655 , G11C11/1659 , G11C11/1673 , Y10S977/933 , Y10S977/935
摘要： In an embodiment, a device is disclosed that includes a magnetic tunnel junction (MTJ) structure. The device also includes a read path coupled to the MTJ structure and a write path coupled to the MTJ structure. The write path is separate from the read path.
摘要翻译：在一个实施例中，公开了一种包括磁隧道结（MTJ）结构的装置。该设备还包括耦合到MTJ结构的读取路径和耦合到MTJ结构的写入路径。写入路径与读取路径分开。

39. 发明申请

US20110139497A1 Via Structure Integrated in Electronic Substrate 有权
标题翻译：电子基板集成电路结构
公开(公告)号：US20110139497A1
公开(公告)日：2011-06-16
申请号：US12637104
申请日：2009-12-14
申请人： Xia Li , Wei Zhao , Yu Cao , Shiqun Gu , Seung H. Kang , Ming-Chu King
发明人： Xia Li , Wei Zhao , Yu Cao , Shiqun Gu , Seung H. Kang , Ming-Chu King
IPC分类号： H05K1/09 , B05D5/12 , H01R13/648 , H01R43/00
CPC分类号： H01L23/552 , H01L23/14 , H01L23/49827 , H01L23/645 , H01L23/66 , H01L2223/6616 , H01L2223/6622 , H01L2223/6638 , H01L2924/0002 , H01L2924/3011 , H05K1/0222 , H05K1/0245 , H05K3/4602 , H05K3/4644 , H05K2201/09809 , Y10T29/49117 , H01L2924/00
摘要： A system of via structures disposed in a substrate. The system includes a first via structure that comprises an outer conductive layer, an inner insulating layer, and an inner conductive layer disposed in the substrate. The outer conductive layer separates the inner insulating layer and the substrate and the inner insulating layer separates the inner conductive layer and the outer conductive layer. A first signal of a first complementary pair passes through the inner conductive layer and a second signal of the first complementary pair passes through the outer conductive layer. In different embodiments, a method of forming a via structure in an electronic substrate is provided.
摘要翻译：设置在基板中的通孔结构的系统。该系统包括第一通孔结构，其包括外导电层，内绝缘层和设置在基板中的内导电层。外部导电层分离内部绝缘层和基板，内部绝缘层分离内部导电层和外部导电层。第一互补对的第一信号通过内导电层，第一互补对的第二信号通过外导电层。在不同的实施例中，提供了一种在电子衬底中形成通孔结构的方法。

40. 发明申请

US20110084765A1 Three Dimensional Inductor and Transformer 有权
标题翻译：三维电感和变压器
公开(公告)号：US20110084765A1
公开(公告)日：2011-04-14
申请号：US12576033
申请日：2009-10-08
申请人： Jonghae Kim , Shiqun Gu , Brian Matthew Henderson , Thomas R. Toms , Lew G. Chua-Eoan , Seyfollah S. Bazarjani , Matthew Nowak
发明人： Jonghae Kim , Shiqun Gu , Brian Matthew Henderson , Thomas R. Toms , Lew G. Chua-Eoan , Seyfollah S. Bazarjani , Matthew Nowak
IPC分类号： H03F3/16 , H01F5/00
CPC分类号： H01L28/10 , H01F17/0013 , H01F19/04 , H01F2017/002 , H01L23/481 , H01L23/5227 , H01L27/0207 , H01L2224/16145 , H01L2924/3011
摘要： A three dimensional on-chip inductor, transformer and radio frequency amplifier are disclosed. The radio frequency amplifier includes a pair of transformers and a transistor. The transformers include at least two inductively coupled inductors. The inductors include a plurality of segments of a first metal layer, a plurality of segments of a second metal layer, a first inductor input, a second inductor input, and a plurality of through silicon vias coupling the plurality of segments of the first metal layer and the plurality of segments of the second metal layer to form a continuous, non-intersecting path between the first inductor input and the second inductor input. The inductors can have a symmetric or asymmetric geometry. The first metal layer can be a metal layer in the back-end-of-line section of the chip. The second metal layer can be located in the redistributed design layer of the chip.
摘要翻译：公开了三维片上电感器，变压器和射频放大器。射频放大器包括一对变压器和晶体管。变压器包括至少两个电感耦合电感器。电感器包括第一金属层的多个段，第二金属层的多个段，第一电感器输入端，第二电感器输入端和耦合第一金属层的多个段的多个穿通硅通孔以及第二金属层的多个段，以在第一电感器输入端和第二电感器输入端之间形成连续的，不相交的路径。电感器可以具有对称或不对称的几何形状。第一金属层可以是芯片的后端部分中的金属层。第二金属层可以位于芯片的再分布设计层中。

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