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1. 发明授权

US08633562B2 Voltage switchable dielectric for die-level electrostatic discharge (ESD) protection 有权
标题翻译：用于芯片级静电放电（ESD）保护的电压可切换电介质
公开(公告)号：US08633562B2
公开(公告)日：2014-01-21
申请号：US13078672
申请日：2011-04-01
申请人： Shiqun Gu , Ratibor Radojcic , Yiming Li
发明人： Shiqun Gu , Ratibor Radojcic , Yiming Li
IPC分类号： H01L23/58
CPC分类号： H01L23/62 , H01L23/29 , H01L23/60 , H01L24/05 , H01L24/06 , H01L24/16 , H01L25/0657 , H01L2224/0401 , H01L2224/05567 , H01L2224/0557 , H01L2224/06181 , H01L2224/16145 , H01L2225/06513 , H01L2225/06541 , H01L2924/00014 , H01L2924/12042 , H01L2924/14 , H01L2224/05552 , H01L2924/00
摘要： A voltage-switchable dielectric layer may be employed on a die for electrostatic discharge (ESD) protection. The voltage-switchable dielectric layer functions as a dielectric layer between terminals of the die during normal operation of the die. When ESD events occur at the terminals of the die, a high voltage between the terminals switches the voltage-switchable dielectric layer into a conducting layer to allow current to discharge to a ground terminal of the die without the current passing through circuitry of the die. Thus, damage to the circuitry of the die is reduced or prevented during ESD events on dies with the voltage-switchable dielectric layer. The voltage-switchable dielectric layer may be deposited on the back side of a die for protection during stacking with a second die to form a stacked IC.
摘要翻译：可以在用于静电放电（ESD）保护的管芯上使用电压可切换电介质层。电压切换介电层在芯片的正常操作期间用作模具的端子之间的介电层。当在芯片的端子处发生ESD事件时，端子之间的高电压将可切换电压的电介质层切换成导电层，以允许电流放电到裸片的接地端子，而不会流过电流通过电路的电路。因此，在具有可电压切换介电层的管芯上的ESD事件期间，对管芯电路的损坏被减小或防止。电压可切换电介质层可以沉积在管芯的背面上，用于在与第二管芯堆叠期间进行保护以形成堆叠的IC。

2. 发明申请

US20120248582A1 Voltage Switchable Dielectric for Die-Level Electrostatic Discharge (ESD) Protection 有权
标题翻译：用于芯片级静电放电（ESD）保护的电压可切换介质
公开(公告)号：US20120248582A1
公开(公告)日：2012-10-04
申请号：US13078672
申请日：2011-04-01
申请人： Shiqun Gu , Ratibor Radojcic , Yiming Li
发明人： Shiqun Gu , Ratibor Radojcic , Yiming Li
IPC分类号： H01L23/58 , H01L21/50 , H01L21/31
CPC分类号： H01L23/62 , H01L23/29 , H01L23/60 , H01L24/05 , H01L24/06 , H01L24/16 , H01L25/0657 , H01L2224/0401 , H01L2224/05567 , H01L2224/0557 , H01L2224/06181 , H01L2224/16145 , H01L2225/06513 , H01L2225/06541 , H01L2924/00014 , H01L2924/12042 , H01L2924/14 , H01L2224/05552 , H01L2924/00
摘要： A voltage-switchable dielectric layer may be employed on a die for electrostatic discharge (ESD) protection. The voltage-switchable dielectric layer functions as a dielectric layer between terminals of the die during normal operation of the die. When ESD events occur at the terminals of the die, a high voltage between the terminals switches the voltage-switchable dielectric layer into a conducting layer to allow current to discharge to a ground terminal of the die without the current passing through circuitry of the die. Thus, damage to the circuitry of the die is reduced or prevented during ESD events on dies with the voltage-switchable dielectric layer. The voltage-switchable dielectric layer may be deposited on the back side of a die for protection during stacking with a second die to form a stacked IC.
摘要翻译：可以在用于静电放电（ESD）保护的管芯上使用电压可切换电介质层。电压切换介电层在芯片的正常操作期间用作模具的端子之间的介电层。当在芯片的端子处发生ESD事件时，端子之间的高电压将可切换电压的电介质层切换成导电层，以允许电流放电到裸片的接地端，而不会流过电流通过电路的电路。因此，在具有可电压切换介电层的管芯上的ESD事件期间，对管芯电路的损坏被减小或防止。电压可切换电介质层可以沉积在管芯的背面上，用于在与第二管芯堆叠期间进行保护以形成堆叠的IC。

3. 发明申请

US20110248405A1 Selective Patterning for Low Cost through Vias 审中-公开
标题翻译：通过Vias实现低成本的选择性图案化
公开(公告)号：US20110248405A1
公开(公告)日：2011-10-13
申请号：US12757570
申请日：2010-04-09
申请人： Yiming Li , Mario Francisco Velez , Shiqun Gu
发明人： Yiming Li , Mario Francisco Velez , Shiqun Gu
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H05K3/002 , H01L21/486 , H01L21/76898 , H01L23/15 , H01L23/49827 , H01L2924/0002 , H05K1/0306 , H05K3/386 , H05K2201/0394 , H01L2924/00
摘要： A block layer deposited on a substrate before deposition of metal lines and etching of a through via enables low cost fabrication of through vias in a substrate using isotropic etching processes. For example, wet etching of a glass substrate may be used to fabricate through glass vias without undercut from the wet etching shorting metal lines on the glass substrate. The block layer prevents contact between a conductive layer lining the through via with more than one metal line on the substrate. The manufacturing process allows stacking of devices on substrates such as glass substrates and connecting the devices with through vias.
摘要翻译：在沉积金属线和蚀刻通孔之前沉积在基板上的阻挡层使用各向同性蚀刻工艺可以在基板中实现通孔中的通孔的低成本制造。例如，可以使用玻璃基板的湿式蚀刻来通过玻璃基板进行制造，而不会从玻璃基板上的湿法蚀刻短路金属线上进行底切。阻挡层防止衬底上的导电层与衬底上的多于一条金属线的接触。制造过程允许在诸如玻璃基板的基板上堆叠设备并且将设备与通孔连接。

4. 发明授权

US09390174B2 Search result ranking and presentation 有权
标题翻译：搜索结果排名和演示
公开(公告)号：US09390174B2
公开(公告)日：2016-07-12
申请号：US13570043
申请日：2012-08-08
申请人： Chen Zhou , Chen Ding , David Francois Huynh , JinYu Lou , Yanlai Huang , Hongda Shen , Guanghua Li , Yiming Li , Yangyang Chai
发明人： Chen Zhou , Chen Ding , David Francois Huynh , JinYu Lou , Yanlai Huang , Hongda Shen , Guanghua Li , Yiming Li , Yangyang Chai
IPC分类号： G06F17/30
CPC分类号： G06F17/3053 , G06F17/30554 , G06F17/30864 , G06F17/30958 , G06F17/30991
摘要： Methods and systems are provided for ranking search results and generating a presentation. In some implementations, a search system generates a presentation based on a search query. In some implementations, a search system ranks search results based on data stored in a knowledge graph. In some implementations, a search system identifies a modifying concept such as a superlative in a received search query, and determines ranking properties based on the modifying concept.
摘要翻译：提供了方法和系统，用于对搜索结果进行排名并生成演示文稿。在一些实现中，搜索系统基于搜索查询生成呈现。在一些实现中，搜索系统基于存储在知识图中的数据来排列搜索结果。在一些实现中，搜索系统识别修改概念，例如在接收到的搜索查询中的最高级，并且基于修改概念来确定排序属性。

5. 发明授权

US08713535B2 Reliable and accurate usage detection of a software application 有权
标题翻译：软件应用的可靠和准确的使用检测
公开(公告)号：US08713535B2
公开(公告)日：2014-04-29
申请号：US12165603
申请日：2008-06-30
申请人： Nipoon Malhotra , Ram Viswanathan , Vikram Kakumani , Mauktik H. Gandhi , Sarath Madakasira , Yiming Li , Kiran Sagi
发明人： Nipoon Malhotra , Ram Viswanathan , Vikram Kakumani , Mauktik H. Gandhi , Sarath Madakasira , Yiming Li , Kiran Sagi
IPC分类号： G06F9/44
CPC分类号： G06F15/173 , G06F11/30 , G06Q30/02
摘要： Use of software applications is detected by categorizing components of applications into a usage manifest and implementing a usage detection background service on a client PC that monitors the components according to the usage manifest. The application components are categorized based on the mode of user interaction as well as the component's correlation to active use of an application. The background service tracks events and activities associated with the application components to generate usage metrics that include the frequency of unique launches of an application and the duration of each unique use. A usage manager for the background service may utilize the usage metrics for a component independently, or combine metrics for multiple components in cases where applications work in an interactive manner (such as a plug-in to a web browser) in order to compute application usage by comparing the metrics against predefined thresholds.
摘要翻译：通过将应用程序的组件分类为使用清单并在客户端PC上实施使用检测后台服务来检测软件应用程序的使用，该客户端PC根据使用情况清单来监视组件。应用程序组件根据用户交互模式以及组件与应用程序的主动使用的相关性进行分类。后台服务跟踪与应用程序组件相关联的事件和活动，以生成包括应用程序独特启动频率和每个独特使用持续时间的使用指标。用于后台服务的使用管理器可以独立地利用组件的使用度量，或者在应用以交互方式工作的情况下（诸如Web浏览器的插件）来组合多个组件的度量，以便计算应用使用通过将度量与预定义的阈值进行比较。

6. 发明申请

US20140046934A1 Search Result Ranking and Presentation 有权
标题翻译：搜索结果排名和演示
公开(公告)号：US20140046934A1
公开(公告)日：2014-02-13
申请号：US13570043
申请日：2012-08-08
申请人： Chen Zhou , Chen Ding , David Francois Huynh , JinYu Lou , Yanlai Huang , Hongda Shen , Guanghua Li , Yiming Li , Yangyang Chai
发明人： Chen Zhou , Chen Ding , David Francois Huynh , JinYu Lou , Yanlai Huang , Hongda Shen , Guanghua Li , Yiming Li , Yangyang Chai
IPC分类号： G06F17/30
CPC分类号： G06F17/3053 , G06F17/30554 , G06F17/30864 , G06F17/30958 , G06F17/30991
摘要： Methods and systems are provided for ranking search results and generating a presentation. In some implementations, a search system generates a presentation based on a search query. In some implementations, a search system ranks search results based on data stored in a knowledge graph. In some implementations, a search system identifies a modifying concept such as a superlative in a received search query, and determines ranking properties based on the modifying concept.
摘要翻译：提供了方法和系统，用于对搜索结果进行排名并生成演示文稿。在一些实现中，搜索系统基于搜索查询生成呈现。在一些实现中，搜索系统基于存储在知识图中的数据来排列搜索结果。在一些实现中，搜索系统识别修改概念，例如在接收到的搜索查询中的最高级，并且基于修改概念来确定排序属性。

7. 发明申请

US20110229687A1 Through Glass Via Manufacturing Process 审中-公开
标题翻译：通过玻璃制造工艺
公开(公告)号：US20110229687A1
公开(公告)日：2011-09-22
申请号：US12727775
申请日：2010-03-19
申请人： Shiqun Gu , Xia Li , Yiming Li
发明人： Shiqun Gu , Xia Li , Yiming Li
IPC分类号： B32B3/10 , B44C1/22
CPC分类号： H01L23/15 , H01L21/486 , H01L23/49827 , H01L2924/0002 , H05K3/0041 , Y10T428/24273 , H01L2924/00
摘要： Fabrication of a through glass via in a relatively thick glass substrate includes patterning a through glass via hard mask on a surface of the glass substrate. The fabrication also includes wet etching a portion of the glass substrate, through the hard mask, to create a partial through glass via. The wet etching may involve applying a vapor of an oxide etch chemical, such as HF and XeF6, or applying a wet oxide etch chemical, such as HF and XeF6. The fabrication further includes passivating the etched partial through glass via, removing bottom passivation from the partial through glass via, and repeating the etching, passivating and removing to create the through glass via. The resulting through glass via has a scalloped side wall, a vertical profile and a high aspect ratio.
摘要翻译：在相对厚的玻璃基板中制造直通玻璃通孔包括在玻璃基板的表面上通过硬掩模图案化通孔玻璃。该制造还包括通过硬掩模湿法蚀刻玻璃基底的一部分，以产生部分透过玻璃通孔。湿蚀刻可以包括施加氧化物蚀刻化学品的蒸气，例如HF和XeF 6，或者施加湿氧化物蚀刻化学品，例如HF和XeF 6。该制造还包括钝化蚀刻的部分通过玻璃通孔，从部分通过玻璃通孔去除底部钝化，并重复蚀刻，钝化和去除以产生通孔玻璃通孔。所产生的通过玻璃通孔具有扇形侧壁，垂直轮廓和高纵横比。

8. 发明申请

US20110227230A1 THROUGH-SILICON VIA FABRICATION WITH ETCH STOP FILM 审中-公开
标题翻译：通过硅胶制成的薄膜
公开(公告)号：US20110227230A1
公开(公告)日：2011-09-22
申请号：US12727750
申请日：2010-03-19
申请人： Shiqun Gu , Yiming Li , Urmi Ray
发明人： Shiqun Gu , Yiming Li , Urmi Ray
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L21/76898
摘要： For a semiconductor wafer substrate having an inter layer dielectric, a through-silicon via may be formed in the substrate by first depositing an etch stop film on top of the inter layer dielectric, followed by etching an opening through the etch stop film, the interlayer dielectric, and into the substrate. A dielectric liner is then deposited over the etch stop film and into the opening. For some embodiments, the dielectric liner may be etched away except for those portions adhering to the sidewall of the opening. Then a conductive material may be deposited into the opening and on the etch stop film. The excess conductive material may then be removed, and for some embodiments the etch stop film may also be removed.
摘要翻译：对于具有层间电介质的半导体晶片衬底，可以在衬底中形成通硅通孔，首先在层间电介质的顶部上沉积蚀刻停止膜，然后蚀刻通过蚀刻停止膜，中间层电介质，并进入衬底。然后将电介质衬垫沉积在蚀刻停止膜上并进入开口中。对于一些实施例，除了粘附到开口的侧壁上的那些部分之外，电介质衬垫可被蚀刻掉。然后可以将导电材料沉积到开口中和蚀刻停止膜上。然后可以除去过量的导电材料，并且对于一些实施例，也可以去除蚀刻停止膜。

9. 发明申请

US20110012239A1 Barrier Layer On Polymer Passivation For Integrated Circuit Packaging 审中-公开
标题翻译：聚合物钝化阻挡层用于集成电路封装
公开(公告)号：US20110012239A1
公开(公告)日：2011-01-20
申请号：US12758311
申请日：2010-04-12
申请人： Shiqun Gu , Urmi Ray , Yiming Li , Arvind Chandrasekaran
发明人： Shiqun Gu , Urmi Ray , Yiming Li , Arvind Chandrasekaran
IPC分类号： H01L29/06 , H01L21/768 , H01L21/311
CPC分类号： H01L23/3192 , H01L21/6836 , H01L23/3142 , H01L24/11 , H01L24/13 , H01L24/94 , H01L2221/6834 , H01L2224/10126 , H01L2224/1147 , H01L2224/1191 , H01L2224/13022 , H01L2224/13099 , H01L2224/16225 , H01L2224/94 , H01L2924/0001 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01033 , H01L2924/14 , H01L2924/1433 , H01L2224/11 , H01L2224/03
摘要： A barrier layer deposited on the passivation layer of a semiconductor die decreases adhesion of glue used during stacking of semiconductor dies by altering chemical or structural properties of the passivation layer. During detachment of a carrier wafer from a wafer, the barrier layer reduces glue residue on the wafer by modifying the surface of the passivation layer. The barrier layer may be insulating films such as silicon dioxide, silicon nitride, silicon carbide, polytetrafluoroethylene, organic layers, or epoxy and may be less than two micrometers in thickness. Additionally, the barrier layer may be used to reduce topography of the semiconductor die to decrease adhesion of glues.
摘要翻译：沉积在半导体管芯的钝化层上的阻挡层通过改变钝化层的化学或结构特性来降低在半导体管芯堆叠期间使用的胶粘附力。在从晶片分离载体晶片时，阻挡层通过改变钝化层的表面来减少晶片上的胶残余物。阻挡层可以是诸如二氧化硅，氮化硅，碳化硅，聚四氟乙烯，有机层或环氧树脂之类的绝缘膜，并且其厚度可以小于2微米。此外，阻挡层可以用于减少半导体管芯的形貌以降低胶粘剂的粘附。

10. 发明申请

US20100314725A1 Stress Balance Layer on Semiconductor Wafer Backside 审中-公开
标题翻译：半导体晶片背面的应力平衡层
公开(公告)号：US20100314725A1
公开(公告)日：2010-12-16
申请号：US12483759
申请日：2009-06-12
申请人： Shiqun Gu , Arvind Chandrasekaran , Urmi Ray , Yiming Li
发明人： Shiqun Gu , Arvind Chandrasekaran , Urmi Ray , Yiming Li
IPC分类号： H01L23/00 , H01L21/306 , H01L21/31
CPC分类号： H01L25/0657 , H01L21/76898 , H01L23/562 , H01L2224/16 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2924/00011 , H01L2924/00014 , H01L2224/0401
摘要： A semiconductor component (such as a semiconductor wafer or semiconductor die) includes a substrate having a front side and a back side. The semiconductor die/wafer also includes a stress balance layer on the back side of the substrate. An active layer deposited on the front side of the substrate creates an unbalanced stress in the semiconductor wafer/die. The stress balance layer balances stress in the semiconductor wafer/die. The stress in the stress balance layer approximately equals the stress in the active layer. Balancing stress in the semiconductor component prevents warpage of the semiconductor wafer/die.
摘要翻译：半导体元件（例如半导体晶片或半导体晶片）包括具有正面和背面的基板。半导体管芯/晶片还包括在衬底背面的应力平衡层。沉积在基板的正面上的有源层在半导体晶片/管芯中产生不平衡的应力。应力平衡层平衡半导体晶片/模具中的应力。应力平衡层中的应力大致等于有源层中的应力。在半导体部件中平衡应力可以防止半导体晶片/裸片翘曲。

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