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    • 32. 发明授权
    • Multithread processor and register control method
    • 多线程处理器和寄存器控制方法
    • US07805594B2
    • 2010-09-28
    • US10986142
    • 2004-11-12
    • Toshio Yoshida
    • Toshio Yoshida
    • G06F9/34G06F9/38G06F9/46
    • G06F9/3851G06F9/30127
    • The present invention relates to a multithread processor, and this multithread processor comprises a plurality of register windows each provided for each of threads and capable of storing data to be used for instruction processing in an arithmetic unit, a work register capable of mutually transferring data with respect to the plurality of register windows and the arithmetic unit and a multithread control unit for controlling data transfer among the plurality of register windows, the work register and the arithmetic unit on the basis of an execution thread identifier for identifying the thread to be executed in the arithmetic unit. This enables conducting the multithread processing at a high speed.
    • 多线程处理器本发明涉及一种多线程处理器,该多线程处理器包括多个寄存器窗口,每个寄存器窗口分别为每个线程提供,并能够存储用于在算术单元中进行指令处理的数据,能够与 涉及多个寄存器窗口和算术单元;以及多线程控制单元,用于基于用于识别要执行的线程的执行线程标识符来控制多个寄存器窗口,工作寄存器和运算单元之间的数据传送 算术单元。 这使得能够高速进行多线程处理。
    • 34. 发明申请
    • INFORMATION PROCESSING DEVICE AND LOAD ARBITRATION CONTROL METHOD
    • 信息处理装置和负载仲裁控制方法
    • US20100095304A1
    • 2010-04-15
    • US12635801
    • 2009-12-11
    • Takashi SUZUKIToshio Yoshida
    • Takashi SUZUKIToshio Yoshida
    • G06F9/46
    • G06F9/3851
    • The information processing device in the simultaneous multi-threading system is operated in an inter-thread performance load arbitration control method, and includes: an instruction input control unit for sharing among threads control of inputting an instruction in an arithmetic unit for acquiring the instruction from memory and performing an operation on the basis of the instruction; a commit stack entry provided for each thread for holding information obtained by decoding the instruction; an instruction completion order control unit for updating the memory and a general purpose register depending on an arithmetic result obtained by the arithmetic unit in an order of the instructions input from the instruction input control unit; and a performance load balance analysis unit for detecting the information registered in the commit stack entry and controlling the instruction input control unit.
    • 同时多线程系统中的信息处理装置以线程间性能负载仲裁控制方式进行操作,包括:指令输入控制单元,用于在线程之间共享输入用于获取指令的算术单元中的指令的控制 存储器并基于该指令执行操作; 为每个线程提供的用于保存通过解码指令而获得的信息的提交栈条目; 指令完成顺序控制单元,用于根据从指令输入控制单元输入的指令的顺序,根据运算单元获得的运算结果来更新存储器和通用寄存器; 以及性能负载平衡分析单元,用于检测在提交堆栈条目中登记的信息并控制指令输入控制单元。
    • 38. 发明授权
    • Elongated rib for cassette and substrate cassette
    • 用于盒式磁带和衬底盒的细长肋骨
    • US06523701B1
    • 2003-02-25
    • US09655872
    • 2000-09-06
    • Toshio YoshidaYuji AmanoTaimi OketaniMasayuki TsujiIsao Saraoka
    • Toshio YoshidaYuji AmanoTaimi OketaniMasayuki TsujiIsao Saraoka
    • A47G1908
    • H01L21/6734H01L21/67343
    • A cassette for supporting substrates and an elongated rib therefor is described and represents a further improvement in the previously proposed elongated rib systems of the prior art and is designed particularly to preclude deflection and dampen vibrations of loaded substrates. The elongated ribs for the cassette project from side panels utilizing an elongated rib structure including three segments; namely, a base resin body, a bar-like intermediate resin body extending from the base resin body, and a terminal resin body disposed at the forward end of the intermediate resin body. Preferably, the elongated rib structure includes a linearreinforcing member inserted fromthe base resin body to the intermediate resin body or, alternatively, from the base resin body through the intermediate resin body to the terminal resin body.
    • 描述了用于支撑基板的盒和用于其的细长肋,并且表示了先前提出的现有技术的细长肋系统的进一步改进,并且被特别设计用于防止加载的基板的偏转和阻尼振动。 用于盒的细长肋条利用包括三个段的细长肋结构从侧板突出; 即基体树脂体,从基体树脂体延伸的棒状中间树脂体,以及设置在中间树脂体的前端的端子树脂体。 优选地,细长肋结构包括从基体树脂体向中间树脂体插入的线性增强部件,或者从基体树脂体通过中间树脂体向端子树脂体插入。
    • 39. 发明授权
    • Flat cells
    • 扁平细胞
    • US06203938B1
    • 2001-03-20
    • US09357790
    • 1999-07-21
    • Toshio YoshidaKazuo Omine
    • Toshio YoshidaKazuo Omine
    • H01M1040
    • H01M10/0525H01M4/04H01M4/0402H01M4/0404H01M4/0416H01M4/043H01M4/0435H01M4/0438H01M4/045H01M4/0471H01M4/13H01M6/10H01M10/0431H01M10/0587Y10T29/49108Y10T29/4911Y10T29/49115
    • The present invention provides a flat cell that employs strip-shaped electrode plates on which an active material layer has been formed by coating paste or by electrolytic deposition on both sides or one side of a core material consisting of a metal foil. By constructing an electrode group having an oval cross section by spirally winding in a manner folding, a strip-shaped positive plate having a striped recessed portion of a predetermined width of which the center is positioned on the line of folding formed on the active material layer at least the inner side of at least the inner-most folded portion close to a core portion, and a strip-shaped negative plate with a separator interposed, reduction in the battery capacity due to breakage of the electrode plates and/or peeling off and dropping of the active material layers and failure due to internal short circuit as has previously been caused when assembling an electrode group having an oval cross section can be completely eliminated, thus drastically improving the reliability of flat cells, especially flat type lithium-ion secondary batteries.
    • 本发明提供一种扁平电池,其采用带状电极板,其上通过涂覆糊剂或通过电解沉积在由金属箔构成的芯材的两侧或一侧上形成活性物质层。 通过以折叠的方式螺旋卷绕构造具有椭圆形横截面的电极组,将具有预定宽度的条形凹部的条形正极板,其中心位于活性材料层上形成的折叠线上 至少最靠近芯部的最内折叠部分的内侧和插入有隔膜的带状负极板,由于电极板的断裂和/或剥离而导致的电池容量的降低和 可以完全消除组装具有椭圆形横截面的电极组时活性物质层的下降和内部短路导致的故障,从而大大提高了平板电池,特别是扁平型锂离子二次电池的可靠性 。