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    • 5. 发明授权
    • Extended register addressing using prefix instruction
    • 使用前缀指令进行扩展寄存器寻址
    • US08601239B2
    • 2013-12-03
    • US12827238
    • 2010-06-30
    • Toshio YoshidaYasunobu AkizukiRyuichi Sunayama
    • Toshio YoshidaYasunobu AkizukiRyuichi Sunayama
    • G06F9/30
    • G06F9/30145G06F9/30101G06F9/30185
    • A processor includes a storage unit storing an instruction, an instruction extension information register that includes a first area and a second area, an instruction decoding unit that decodes a first prefix instruction including first extension information extending an immediately following instruction written to the first area when the first prefix instruction is executed, and that decodes a second prefix instruction including the first extension information and a second extension information extending an instruction immediately following two instructions of the second prefix instruction, an instruction packing unit that generates a packed instruction including at least one of the first prefix instruction or the second prefix instruction, and the instruction immediately following the first prefix instruction or the second prefix instruction when the instruction decoding unit decodes the first prefix instruction or the second prefix instruction, an instruction execution unit that executes the packed instruction generated by the instruction packing unit.
    • 处理器包括存储指令的存储单元,包括第一区域和第二区域的指令扩展信息寄存器,指令解码单元,其对包含第一扩展信息的第一前缀指令进行解码,所述第一前缀指令包括第一扩展信息, 执行第一前缀指令,并且解码包括第一扩展信息的第二前缀指令和扩展紧跟在第二前缀指令的两个指令之后的指令的第二扩展信息;指令打包单元,其生成包括至少一个 第一前缀指令或第二前缀指令的指令,以及当指令解码单元解码第一前缀指令或第二前缀指令时紧跟在第一前缀指令或第二前缀指令之后的指令,执行指令执行单元, 剪切由指令包装单元生成的打包指令。
    • 6. 发明授权
    • Multithread processor and method of controlling multithread processor
    • 多线程处理器和控制多线程处理器的方法
    • US08447959B2
    • 2013-05-21
    • US12805630
    • 2010-08-10
    • Toshio Yoshida
    • Toshio Yoshida
    • G06F9/48
    • G06F9/3851G06F9/30127
    • A plurality of register windows in a multithread processor are each provided for a corresponding thread and capable of storing data to be used for instruction processing in an arithmetic unit. A work register in the multithread processor is capable of mutually transferring data with respect to the register windows and the arithmetic unit. A multithread control unit in the multithread processor controls data transfer among the register windows, the work register and the arithmetic unit on the basis of an execution thread identifier identifying the thread to be executed in the arithmetic unit. This enables conducting the multithread processing at a high speed.
    • 多线程处理器中的多个寄存器窗口分别被提供给相应的线程并且能够存储用于在算术单元中进行指令处理的数据。 多线程处理器中的工作寄存器能够相对于寄存器窗口和算术单元相互传送数据。 多线程处理器中的多线程控制单元基于识别要在运算单元中执行的线程的执行线程标识符来控制寄存器窗口,工作寄存器和运算单元之间的数据传送。 这使得能够高速进行多线程处理。
    • 9. 发明授权
    • Processing unit
    • 处理单元
    • US08001362B2
    • 2011-08-16
    • US12633108
    • 2009-12-08
    • Atsushi FusejimaTakashi SuzukiToshio YoshidaYasunobu Akizuki
    • Atsushi FusejimaTakashi SuzukiToshio YoshidaYasunobu Akizuki
    • G06F9/38G06F9/46
    • G06F9/3851G06F9/3013G06F9/3857G06F11/3466G06F2201/88
    • A processing unit includes a plurality of thread execution units each provided with a performance analysis circuit for measuring various types of events resulting from execution of instructions and a commit stack entry unit for controlling the completion of executed instructions and each executing a thread having a plurality of instructions, a commit scope register for storing instructions of completion candidates stored in each commit stack entry unit by execution by each thread execution unit and performing processing for completion of instructions included in the thread, and a thread selecting means for sending commit events of the instructions to a performance analysis circuit provided in each thread execution unit corresponding to the instructions when performing commit processing for instructions stored in the commit scope register.
    • 处理单元包括多个线程执行单元,每个线程执行单元具有用于测量执行指令的各种类型的事件的性能分析电路和用于控制执行指令完成的提交堆栈输入单元,并且每个线程执行单元执行具有多个 指令,用于通过每个线程执行单元的执行来存储存储在每个提交栈输入单元中的完成候选的指令的提交范围寄存器,并且执行用于完成包括在该线程中的指令的处理;线程选择装置,用于发送指令的提交事件 涉及在对存储在提交范围寄存器中的指令执行提交处理时对应于指令的每个线程执行单元中提供的性能分析电路。
    • 10. 发明申请
    • Instruction processing apparatus
    • 指令处理装置
    • US20100106945A1
    • 2010-04-29
    • US12654311
    • 2009-12-16
    • Toshio Yoshida
    • Toshio Yoshida
    • G06F9/30G06F9/38G06F9/312
    • G06F9/3851G06F9/3004G06F9/30087G06F9/3802G06F9/382G06F9/3838
    • The present invention includes a decode section for simultaneously holding a plurality of instructions in one thread at a time and for decoding the held instructions; an execution pipeline capable of simultaneously executing each processing represented by the respective instructions belonging to different threads and decoded by the decode section; a reservation station for receiving the instructions decoded by the decode section and holding the instructions, if the decoded instructions are of sync attribute, until executable conditions are ready and thereafter dispatching the decoded instructions to the execution pipeline; a pre-decode section for confirming by a simple decoding, prior to decoding by the decode section, whether or not the instructions are of sync attribute; and an instruction buffer for suspending issuance to the decode section and holding the instructions subsequent to an instruction of sync attribute.
    • 本发明包括一个解码部分,用于一次同时在一个线程中保持多个指令并解码所保持的指令; 能够同时执行由属于不同线程并由解码部解码的各个指令所表示的每个处理的执行流水线; 如果所述解码指令是同步属性,则在所述可执行条件就绪之前,接收由所述解码部解码的指令并保持所述指令的保留站,并且此后将解码的指令分派到所述执行管线; 预解码部分,用于在由解码部分解码之前通过简单解码来确认指令是否是同步属性; 以及指令缓冲器,用于暂停向解码部分发布并保持在sync属性指令之后的指令。