专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

31. 发明授权

US08898504B2 Parallel data communications mechanism having reduced power continuously calibrated lines 有权
标题翻译：并行数据通信机制具有降低功率的连续校准线路
公开(公告)号：US08898504B2
公开(公告)日：2014-11-25
申请号：US13325478
申请日：2011-12-14
申请人： Steven J. Baumgartner , Frank D. Ferraiolo , Susan M. Eickhoff , Michael B. Spear
发明人： Steven J. Baumgartner , Frank D. Ferraiolo , Susan M. Eickhoff , Michael B. Spear
IPC分类号： G06F11/00
CPC分类号： H04L1/22
摘要： A communications link includes multiple continuously calibrated parallel lines, wherein one or more lines are at least partially powered down while being continuously calibrated to reduce power consumption. In one aspect, at least N+1 lines (where N is the logical bus width) are periodically recalibrated, and at least one redundant line is powered down between calibrations. The redundant line could be either a true spare available for use as a replacement, or an extra line which carries functional data while other lines are being calibrated in turn. In another aspect, the logical bus width is variable, but does not exceed NMAX. When N
摘要翻译：通信链路包括多个连续校准的并行线路，其中一个或多个线路被至少部分断电，同时连续校准以减少功率消耗。在一个方面，至少N + 1行（其中N是逻辑总线宽度）被周期性地重新校准，并且至少一个冗余线路在校准之间断电。冗余线路可以是可用作替代的真实备用，也可以是携带功能数据的额外线路，而其他线路依次校准。另一方面，逻辑总线宽度是可变的，但不超过NMAX。当N

32. 发明授权

US08681839B2 Calibration of multiple parallel data communications lines for high skew conditions 失效
标题翻译：多个并行数据通信线路的校准用于高偏斜条件
公开(公告)号：US08681839B2
公开(公告)日：2014-03-25
申请号：US12912883
申请日：2010-10-27
申请人： John F. Bulzacchelli , Timothy O. Dickson , Frank D. Ferraiolo , Robert J. Reese , Michael B. Spear
发明人： John F. Bulzacchelli , Timothy O. Dickson , Frank D. Ferraiolo , Robert J. Reese , Michael B. Spear
IPC分类号： H04B1/38 , H04L5/16
CPC分类号： H04L25/14 , G06F2213/0038 , H04L7/0025 , H04L7/0337
摘要： A parallel data link includes a redundant line. A bank of switches permits any arbitrary line of the link to be enabled or disabled for carrying functional data, each line being dynamically calibrated in turn by disabling the line and allowing other lines to carry the functional data. The switches are located downstream of alignment mechanisms so that data input to the switches is compensated for data skew. Preferably, receiver synchronization circuitry in each line operates in a respective independent clock domain, while the switches and calibration mechanism operate in a common clock domain. Preferably, the receiver synchronization circuits provide an adjustable delay corresponding to a variable number of clock cycles to align the outputs of the receiver synchronization circuits with respect to one another, which can accommodate high data skew.
摘要翻译：并行数据链路包括冗余线路。一组交换机允许链路的任意任意行被启用或禁用以承载功能数据，每行通过禁用线路并允许其他线路携带功能数据依次被动态地校准。开关位于对准机构的下游，以便数据输入到开关的数据偏移。优选地，每行中的接收器同步电路在相应的独立时钟域中操作，而开关和校准机构在公共时钟域中操作。优选地，接收机同步电路提供对应于可变数量的时钟周期的可调节延迟，以使接收机同步电路的输出相对于彼此对准，这可以适应高数据偏移。

33. 发明申请

US20130159761A1 Parallel Data Communications Mechanism Having Reduced Power Continuously Calibrated Lines 有权
标题翻译：并行数据通信机制具有连续校准线路功耗
公开(公告)号：US20130159761A1
公开(公告)日：2013-06-20
申请号：US13325478
申请日：2011-12-14
申请人： Steven J. Baumgartner , Frank D. Ferraiolo , Susan M. Eickhoff , Michael B. Spear
发明人： Steven J. Baumgartner , Frank D. Ferraiolo , Susan M. Eickhoff , Michael B. Spear
IPC分类号： G06F13/36 , G06F11/20
CPC分类号： H04L1/22
摘要： A communications link includes multiple continuously calibrated parallel lines, wherein one or more lines are at least partially powered down while being continuously calibrated to reduce power consumption. In one aspect, at least N+1 lines (where N is the logical bus width) are periodically recalibrated, and at least one redundant line is powered down between calibrations. The redundant line could be either a true spare available for use as a replacement, or an extra line which carries functional data while other lines are being calibrated in turn. In another aspect, the logical bus width is variable, but does not exceed NMAX. When N
摘要翻译：通信链路包括多个连续校准的并行线路，其中一个或多个线路被至少部分断电，同时连续校准以减少功率消耗。在一个方面，至少N + 1行（其中N是逻辑总线宽度）被周期性地重新校准，并且至少一个冗余线路在校准之间断电。冗余线路可以是可用作替代的真实备用，也可以是携带功能数据的额外线路，而其他线路依次被校准。另一方面，逻辑总线宽度是可变的，但不超过NMAX。当N

34. 发明申请

US20100005335A1 MICROPROCESSOR INTERFACE WITH DYNAMIC SEGMENT SPARING AND REPAIR 审中-公开
标题翻译：微处理器接口与动态分段交换和修复
公开(公告)号：US20100005335A1
公开(公告)日：2010-01-07
申请号：US12165858
申请日：2008-07-01
申请人： Frank D. Ferraiolo , Daniel M. Dreps , Kevin C. Gower , Robert J. Reese
发明人： Frank D. Ferraiolo , Daniel M. Dreps , Kevin C. Gower , Robert J. Reese
IPC分类号： G06F11/00 , G06F13/40
CPC分类号： G06F11/2007
摘要： A processing device, system, method, and design structure for providing a microprocessor interface with dynamic segment sparing and repair. The processing device includes drive-side switching logic including driver multiplexers to select driver data for transmitting on link segments of a bus, and receive-side switching logic including receiver multiplexers to select received data from the link segments of the bus. The bus includes multiple data link segments, a clock link segment, and at least two spare link segments selectable by the drive-side switching logic and the receive-side switching logic to replace one or more of the data link segments and the clock link segment.
摘要翻译：一种处理设备，系统，方法和设计结构，用于提供具有动态段保存和修复的微处理器接口。处理装置包括驱动侧切换逻辑，包括驱动器多路复用器，用于选择用于在总线的链路段上发送的驱动器数据，以及包括接收机多路复用器的接收侧切换逻辑，以从总线的链路段选择接收的数据。该总线包括多个数据链路段，一个时钟链路段，以及由驱动器侧切换逻辑和接收侧切换逻辑选择的至少两个备用链路段，用于替换一个或多个数据链路段和时钟链路段。

35. 发明授权

US07478259B2 System, method and storage medium for deriving clocks in a memory system 失效
标题翻译：用于在存储器系统中导出时钟的系统，方法和存储介质
公开(公告)号：US07478259B2
公开(公告)日：2009-01-13
申请号：US11263344
申请日：2005-10-31
申请人： Frank D. Ferraiolo , Kevin C. Gower , Martin L. Schmatz
发明人： Frank D. Ferraiolo , Kevin C. Gower , Martin L. Schmatz
IPC分类号： G06F1/00
CPC分类号： G06F13/4234 , G06F13/1689
摘要： A system, method and storage medium for deriving clocks in a memory system. The method includes receiving a reference oscillator clock at a hub device. The hub device is in communication with a controller channel via a controller interface and in communication with a memory device via a memory interface. A base clock operating at a base clock frequency is derived from the reference oscillator clock. A memory interface clock is derived by multiplying the base clock by a memory multiplier. A controller interface clock is derived by multiplying the base clock by a controller multiplier. The memory interface clock is applied to the memory interface and the controller interface clock is applied to the controller interface.
摘要翻译：一种用于在存储器系统中导出时钟的系统，方法和存储介质。该方法包括在集线器装置处接收参考振荡器时钟。集线器设备经由控制器接口与控制器通道通信，并且经由存储器接口与存储器设备通信。以基准时钟频率工作的基本时钟从参考振荡器时钟导出。通过将基本时钟乘以存储器乘法器导出存储器接口时钟。控制器接口时钟是通过将基本时钟与控制器乘法器相乘得出的。存储器接口时钟应用于存储器接口，控制器接口时钟应用于控制器接口。

36. 发明授权

US07440531B2 Dynamic recalibration mechanism for elastic interface 失效
标题翻译：弹性界面的动态重新校准机制
公开(公告)号：US07440531B2
公开(公告)日：2008-10-21
申请号：US11055865
申请日：2005-02-11
申请人： Daniel M. Dreps , Frank D. Ferraiolo , Gary A. Peterson , Robert J. Reese
发明人： Daniel M. Dreps , Frank D. Ferraiolo , Gary A. Peterson , Robert J. Reese
IPC分类号： H04L25/00
CPC分类号： H04L7/005 , G11C19/287 , H03K5/133 , H03K2005/00058 , H04L7/0338
摘要： A method and apparatus for de-skewing and aligning digital data received over an elastic interface bus is disclosed. Upon receiving the data, it is sent through a programmable delay line. While in the programmable delay line, the data is sampled at three points within the data's eye pattern. The three sampling points are dynamically adjusted to maximize coverage of the data's eye pattern. During the adjustment of the sampling points to optimally cover the data's eye pattern, delayed data is sampled from an alternate sampler to prevent sampling from the functional sampler while the delay in the primary sampler is adjusted. Sampling from the alternate sampler while changing the sampling points of the functional sampler serves to reduce glitches that may occur by sampling the functional sampler while its sampling parameters are changed. The method and apparatus allow for alternate eye tracking and wrap around eye tracking.
摘要翻译：公开了一种用于使在弹性接口总线上接收的数字数据去偏斜和对准的方法和装置。在接收到数据后，通过可编程延迟线发送。在可编程延迟线中，数据在数据眼图中的三个点进行采样。动态调整三个采样点，以最大化数据眼图的覆盖范围。在调整采样点以最佳地覆盖数据的眼图时，延迟数据从备用采样器采样，以防止在采样器中的延迟调整时从功能采样器采样。在更换功能采样器的采样点时，从备用采样器进行采样可以减少在采样参数变化时采样功能采样器可能发生的毛刺。所述方法和装置允许替代眼睛跟踪并包裹眼睛跟踪。

37. 发明申请

US20080201599A1 COMBINED ALIGNMENT SCRAMBLER FUNCTION FOR ELASTIC INTERFACE 有权
标题翻译：用于弹性界面的组合对齐功能
公开(公告)号：US20080201599A1
公开(公告)日：2008-08-21
申请号：US12048405
申请日：2008-03-14
申请人： Frank D. Ferraiolo , Robert J. Reese , Michael B. Spear
发明人： Frank D. Ferraiolo , Robert J. Reese , Michael B. Spear
IPC分类号： H04L7/00
CPC分类号： H04L25/14 , H04L7/0008 , H04L7/0037 , H04L7/005 , H04L7/044 , H04L7/046 , H04L7/10
摘要： An interface alignment pattern for de-skewing data bits received on an elastic interface is disclosed. The interface alignment pattern is “busy” in that it has a high number of logic state transitions. The busy interface alignment pattern can be used for scrambling and unscrambling operational data. The interface alignment pattern has a unique timing sequence for determining the location of a data bit's first data beat.
摘要翻译：公开了一种用于在弹性接口上接收的用于去偏斜数据比特的接口对准模式。接口对齐模式是“忙”，因为它具有大量的逻辑状态转换。忙接口对准模式可用于加扰和解扰操作数据。接口对准模式具有用于确定数据位的第一数据节拍位置的唯一定时序列。

38. 发明授权

US06922789B2 Apparatus and method for recalibrating a source-synchronous pipelined self-timed bus interface 有权
标题翻译：用于重新校准源同步流水线自定时总线接口的装置和方法
公开(公告)号：US06922789B2
公开(公告)日：2005-07-26
申请号：US09960023
申请日：2001-09-21
申请人： Patrick J. Meaney , Jonathan Chen , Frank D. Ferraiolo , Kevin C. Gower , Glenn E. Holmes
发明人： Patrick J. Meaney , Jonathan Chen , Frank D. Ferraiolo , Kevin C. Gower , Glenn E. Holmes
IPC分类号： G06F11/00 , H04L7/10 , H04L7/00 , G06F13/00
CPC分类号： H04L7/10 , G06F11/00 , H04L7/0008
摘要： An SMP computer system has an apparatus and method for recalibrating a self-timed, source-synchronous, pipelined interface while the computer system is running. The apparatus allows for quiescing the interface (ie. idling the processors to allow for no data transfers), raising fences (blocking interfaces), allowing for a quick clock centering recalibration step, and then unfencing and unquiescing to allow for the use of the interface again. The recalibration allows for compensating for drift over time on the interface to compensate for temperature, voltage, cycle time, and end-of-life degradation without bringing down and restarting the system.
摘要翻译： SMP计算机系统具有在计算机系统运行时重新校准自定时，源同步，流水线接口的装置和方法。该设备允许停顿接口（即空闲处理器以允许不进行数据传输），提高栅栏（阻塞接口），允许快速的时钟定心重新校准步骤，然后解码和解码以允许使用接口再次。重新校准可以补偿接口上随时间的漂移，以补偿温度，电压，循环时间和使用寿命结束后的降低，而不会导致系统重新启动和重新启动。

39. 发明授权

US06807125B2 Circuit and method for reading data transfers that are sent with a source synchronous clock signal 失效
标题翻译：用于读取与源同步时钟信号一起发送的数据传输的电路和方法
公开(公告)号：US06807125B2
公开(公告)日：2004-10-19
申请号：US10225871
申请日：2002-08-22
申请人： Paul W. Coteus , Frank D. Ferraiolo , Kevin C. Gower
发明人： Paul W. Coteus , Frank D. Ferraiolo , Kevin C. Gower
IPC分类号： G11C1100
CPC分类号： G11C7/106 , G11C7/1045 , G11C7/1051 , G11C7/1066
摘要： A circuit and method for reading data transfers that are sent with a source synchronous clock signal. The circuit has a data input for receiving data signals carrying data being transferred, a clock input for receiving synchronous clock signals, and a delay circuit connected to the clock input for generating a delayed clock signal which is delayed from said synchronous clock signal a predetermined time period. The circuit also includes a pipeline connected to the data input for sampling the data on the data input in response to said delayed clock signal thereby stretching the sampling of incoming data.
摘要翻译：用于读取与源同步时钟信号一起发送的数据传输的电路和方法。该电路具有数据输入端，用于接收承载传送数据的数据信号，用于接收同步时钟信号的时钟输入端和连接到时钟输入端的延迟电路，用于产生从所述同步时钟信号延迟预定时间的延迟时钟信号期。电路还包括连接到数据输入端的流水线，用于响应于所述延迟的时钟信号对数据输入上的数据进行采样，从而延伸输入数据的采样。

40. 发明授权

US06285229B1 Digital delay line with low insertion delay 失效
标题翻译：具有低插入延迟的数字延迟线
公开(公告)号：US06285229B1
公开(公告)日：2001-09-04
申请号：US09471898
申请日：1999-12-23
申请人： Albert M. Chu , Frank D. Ferraiolo , John A. Fifield , Teresa Thi Nguyen , Michael Sofranko
发明人： Albert M. Chu , Frank D. Ferraiolo , John A. Fifield , Teresa Thi Nguyen , Michael Sofranko
IPC分类号： H03H1126
CPC分类号： H03K5/131 , H03K5/133 , H03K2005/00058
摘要： A variable digital delay line with an insertion delay as low as a single delay element yet capable of providing a large programmable delay with a small simple control mechanism. A loop connects an input to an output through selectable first delay elements such as 2:1 muxes and selectable second delay elements such as pairs of inverters by way of a plurality of intermediate nodes having a tap. A plurality of sneak paths are available wherein the loop by passes a remainder of first delay elements and/or second delay elements by way of the taps at the intermediate nodes.
摘要翻译：一种可变数字延迟线，其插入延迟低至单个延迟元件，但能够利用小的简单控制机制提供大的可编程延迟。环路通过可选择的第一延迟元件（例如2：1多路复用器）和可选择的第二延迟元件（例如成对的反相器）通过具有抽头的多个中间节点将输入连接到输出。多个潜行路径是可用的，其中循环通过中间节点处的抽头通过第一延迟元件的剩余部分和/或第二延迟元件。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式