会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 31. 发明授权
    • Display driving circuit for displaying character on display panel
    • 显示面板显示字符显示驱动电路
    • US06246388B1
    • 2001-06-12
    • US09309035
    • 1999-05-10
    • Syuji MotegiHiroyuki AraiTetsuya Tokunaga
    • Syuji MotegiHiroyuki AraiTetsuya Tokunaga
    • G09G336
    • G09G5/222G09G3/04G09G3/20G09G2310/0278
    • For changing the content of a display RAM (38) or an accessory RAM (39), various data SDI, such as an instruction code, address data, display data, is initially transferred to a shift register (11). Then, the display data in the shift register (11) is latched by a latch circuit (62). A write operation is carried out during a period from the completion of a shift operation by the shift register (11) using various data SDI in connection with the current display to the completion of a shift operation using various data SDI in connection with the next display, i.e., a period with an operation enable signal CE remaining at an L or H level. As a result, time allowance for writing is ensured, which contributes to reduction of software processing load by an external device.
    • 为了更改显示RAM(38)或附件RAM(39)的内容,初始地将诸如指令代码,地址数据,显示数据的各种数据SDI传送到移位寄存器(11)。 然后,移位寄存器(11)中的显示数据由锁存电路(62)锁存。 在使用与当前显示相关联的各种数据SDI的移位寄存器(11)完成移位操作期间执行写入操作,使用与下一个显示相关联的各种数据SDI的移位操作完成 ,即具有操作使能信号CE保持在L或H电平的周期。 结果,确保写入的时间容许,这有助于减少外部设备的软件处理负担。
    • 32. 发明授权
    • System for prioritizing slave input register to receive data
transmission via bi-directional data line from master
    • 用于优先从属输入寄存器的系统,用于通过双向数据线从主机接收数据传输
    • US5938746A
    • 1999-08-17
    • US805682
    • 1997-02-25
    • Toshiyuki OzawaShuji MotegiTetsuya Tokunaga
    • Toshiyuki OzawaShuji MotegiTetsuya Tokunaga
    • G06F13/38G06F13/42G06F13/18
    • G06F13/423
    • A master (1) and a slave (3) are connected via a transmission line (5) for sending a clock CL; another transmission line (6) for bidirectionally sending data DT; and still another transmission line (7) for sending a control signal CE. Having turned a control signal CE into "L," the master (1) transmits an address code as data DT to the slave (3). Referring to the content of the transmitted address code, the slave (3) detects whether it is a data transmission from the master (1) to the slave (3) or vice versa. While a control signal CE remains "H," data transmission takes place. Data output from the slave (3) to the data line (6) is managed by a bus driver (22). The bus driver (22) is turned off during a period from when the clock CL became "H" to when a control signal CE becomes "L" after data transmission so that data transmission from the master (1) will not be adversely affected.
    • 主机(1)和从机(3)经由用于发送时钟CL的传输线(5)连接; 用于双向发送数据DT的另一传输线(6); 以及用于发送控制信号CE的又一传输线(7)。 将控制信号CE转换为“L”后,主机(1)将地址码作为数据DT发送到从机(3)。 参照发送的地址码的内容,从机(3)检测是否是从主机(1)到从机(3)的数据传输,反之亦然。 当控制信号CE保持“H”时,发生数据传输。 从总线驱动器(22)管理从从机(3)到数据线(6)的数据输出。 在从时钟CL变为“H”到数据传输之后的控制信号CE变为“L”的期间,总线驱动器(22)被关闭,从而不会对来自主机(1)的数据传输产生不利影响。
    • 35. 发明申请
    • Interface Circuit and a Clock Output Method Therefor
    • 接口电路及其时钟输出方法
    • US20070241797A1
    • 2007-10-18
    • US11736913
    • 2007-04-18
    • Tetsuya TokunagaHiroyuki AraiShuji MotegiTakeshi Hibino
    • Tetsuya TokunagaHiroyuki AraiShuji MotegiTakeshi Hibino
    • H03L7/00
    • G06F1/04
    • An interface circuit outputting a clock signal and data to a data register configured to serially read in the data synchronously with the clock signal, in response to a change of a control signal for outputting the clock signal and the data from one logic level to the other logic level, the interface circuit comprising a clock output circuit configured to: detect a logic level of the clock signal when the control signal changes from the one logic level to the other logic level; output the clock signal on an as-is basis to the data register, when detecting one logic level of the clock signal; and output the clock signal after having changed from the other logic level to the one logic level, to the data register, when detecting the other logic level of the clock signal.
    • 一个接口电路,响应于用于输出时钟信号的控制信号和从一个逻辑电平到另一个逻辑电平的数据的变化,输出时钟信号和数据到数据寄存器,配置为与时钟信号同步地串行读取数据 逻辑电平,所述接口电路包括时钟输出电路,所述时钟输出电路被配置为:当所述控制信号从所述一个逻辑电平改变到另一逻辑电平时,检测所述时钟信号的逻辑电平; 当检测到时钟信号的一个逻辑电平时,将时钟信号原样输出到数据寄存器; 并且当检测到时钟信号的另一个逻辑电平时,在从另一个逻辑电平变为一个逻辑电平之后输出时钟信号到数据寄存器。
    • 36. 发明授权
    • Integrated circuit for driving liquid crystal
    • 用于驱动液晶的集成电路
    • US06633271B1
    • 2003-10-14
    • US09455856
    • 1999-12-07
    • Shuji MotegiHiroyuki AraiTetsuya Tokunaga
    • Shuji MotegiHiroyuki AraiTetsuya Tokunaga
    • G09G336
    • G09G3/3696G09G2320/0606G09G2320/066
    • A liquid crystal driving integrated circuit capable of adjusting display contrast and requiring no externally attached components. Transmission gates TG0-TG10 are provided at respective connection points of twelve resistor elements connected in series between a power supply and the ground. One of the voltages V0-V10 derived from the transmission gates TG0-TG10 in accordance with control signals CA0-CA10 is applied to an operational amplifier 8, and used as a reference voltage VLCD0. The control signals CA0-CA10 are obtained by decoding control data D0-D3 supplied from an external source by a decoder 19. Therefore, the reference voltage VLCD0 can be set in a plurality of stages simply by changing control data D0-D3 to a user specified value. As the twelve resistor elements connected in series are formed on the same semiconductor substrate, display contrast can be adjusted without requiring any external components attached to a liquid crystal driving integrated circuit 1.
    • 一种液晶驱动集成电路,能够调节显示对比度并且不需要外部连接的部件。 传输门TG 0 -TG 10 分别连接在电源 和地面。 从传输门TG 0导出的电压V 0 -V 10 根据控制信号CA 0 -CA 10 > -TG 应用于运算放大器 8, ,并用作参考电压VLCD 0 。 通过解码控制数据D 0 获得控制信号CA 0 -CA 10 由解码器 从外部源提供的BOLD> -D 3 。 因此,通过改变控制数据D 0 ,可以在多个阶段中设置参考电压VLCD 0 BOLD> -D 3 到用户指定的值。 由于串联连接的十二个电阻元件形成在相同的半导体基板上,所以可以调节显示对比度,而不需要任何外部元件连接到液晶驱动集成电路 1。