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31. 发明授权

US5867436A Random access memory with a plurality amplifier groups for reading and writing in normal and test modes 失效
标题翻译：具有多个放大器组的随机存取存储器，用于在正常和测试模式下进行读写
公开(公告)号：US5867436A
公开(公告)日：1999-02-02
申请号：US803298
申请日：1997-02-20
申请人： Kiyohiro Furutani , Koichiro Mashiko , Kazutami Arimoto , Noriaki Matsumoto , Yoshio Matsuda
发明人： Kiyohiro Furutani , Koichiro Mashiko , Kazutami Arimoto , Noriaki Matsumoto , Yoshio Matsuda
IPC分类号： G11C11/401 , G06F11/267 , G11C7/10 , G11C11/409 , G11C29/00 , G11C29/26 , G11C29/34 , G11C29/38 , G11C7/00
CPC分类号： G11C7/1057 , G11C29/26 , G11C29/38 , G11C7/10 , G11C7/1006 , G11C7/1051 , G11C7/1078 , G11C7/1084 , G06F11/267
摘要： A semiconductor memory device operable for reading and writing in a normal mode and in a test mode is divided into memory cell sections each having blocks of memory cells. Data bus lines are connected to the respective blocks, and switches interconnect data bus lines connected to blocks of the different sections. The switch are made conductive during reading and writing in the normal mode and during writing in the test mode, and nonconductive during reading in the test mode. Input data are applied onto the data bus lines connected one of the blocks for writing in the blocks of the sections simultaneously during writing in the normal mode and in the test mode. In the normal mode, data are read out of the blocks of the sections through the data bus lines connected to the above-mentioned one of the blocks. In the test mode, the data are read out of the blocks of the sections through the data bus lines connected to the respective blocks.
摘要翻译：可以以正常模式和测试模式读取和写入的半导体存储器件被分成具有存储单元块的存储单元部分。数据总线连接到相应的块，并且交换连接到不同部分的块的数据总线。在正常模式下读写时，在测试模式下写入期间开关导通，在测试模式下读取期间不导通。在正常模式和测试模式下，输入数据被加到连接在一个块上的数据总线上，以便在写入期间同时在这些块中写入。在正常模式下，通过连接到上述一个块的数据总线，从这些部分的块中读出数据。在测试模式中，通过连接到相应块的数据总线，从这些部分的块中读出数据。

32. 发明授权

US5699303A Semiconductor memory device having controllable supplying capability of internal voltage 失效
标题翻译：具有可控的内部电压供应能力的半导体存储器件
公开(公告)号：US5699303A
公开(公告)日：1997-12-16
申请号：US645347
申请日：1996-05-13
申请人： Takeshi Hamamoto , Kiyohiro Furutani , Yoshikazu Morooka
发明人： Takeshi Hamamoto , Kiyohiro Furutani , Yoshikazu Morooka
IPC分类号： G11C11/407 , G11C5/14 , G11C11/403 , G11C11/406 , G11C11/4074 , G11C11/408 , G11C11/409 , G11C13/00
CPC分类号： G11C11/4085 , G11C11/406 , G11C11/4074 , G11C5/146
摘要： When an external RAS and external CAS are input to a RAS buffer and a CAS buffer, an internal RAS and an internal CAS are generated. The internal RAS is input to a clock generating circuit and a CBR mode determination circuit and the internal CAS is input to the CBR mode determination circuit. The clock generating circuit outputs a pump clock to first and second WL pumps upon input of internal RAS, and the first WL pump supplies charge to a Vpp power supply. If CAS is input prior to RAS during refresh operation, CBR mode determination circuit inputs a CBR mode signal to the second WL pump which supplies charge to Vpp power supply together with the first WL pump when the pump clock and the CBR mode signal is input thereto.
摘要翻译：当外部+ E，ovs RAS + EE和外部+ E，ovs CAS + EE输入到RAS缓冲区，CAS缓冲区，内部+ E，ovs RAS + EE和内部+ E，ovs CAS + EE 生成。内部+ E，ovs RAS + EE输入到时钟发生电路和CBR模式确定电路，内部+ E，ovs CAS + EE输入到CBR模式确定电路。时钟发生电路在内部+ E，RAS + EE输入时向第一和第二WL泵输出泵时钟，第一WL泵为Vpp电源供电。如果+ E，则在+ E之前输入ovs CAS + EE，在刷新操作期间输入ovs RAS + EE，CBR模式确定电路将CBR模式信号输入到与第一WL泵一起向Vpp电源提供电荷的第二WL泵当泵时钟和CBR模式信号被输入时。

33. 发明授权

US5642317A Semiconductor memory device incorporating a test mechanism 失效
标题翻译：包含测试机构的半导体存储器件
公开(公告)号：US5642317A
公开(公告)日：1997-06-24
申请号：US551484
申请日：1995-11-01
申请人： Kiyohiro Furutani
发明人： Kiyohiro Furutani
IPC分类号： G11C29/38 , G11C7/00 , G11C29/00
CPC分类号： G11C29/38
摘要： To present a semiconductor memory device incorporating a test mechanism in order to test plural semiconductor memory devices by using a tester having a single data judging circuit. The drain electrode of an N type MOSFET (Q16) is connected to a power source potential (V.sub.CC) through a fuse element (F1) (route cut-off element), and the source electrode is connected to the drain electrode of an N type MOSFET (Q17), and the drain electrode of the N type MOSFET (Q16) is connected to the input of an inverter (G16), and is also connected to a resistance element (R1) connected to a grounding potential (V.sub.SS). Therefore, since the test mechanism is incorporated, parallel tests are conducted by the inexpensive tester having only one data judging circuit, and thereafter by judging the results of comparison individually by using the same tester, the qualification of the semiconductor memory device can be judged.
摘要翻译：提出一种结合有测试机构的半导体存储器件，以便通过使用具有单个数据判断电路的测试器来测试多个半导体存储器件。 N型MOSFET（Q16）的漏电极通过熔丝元件（F1）（路线截止元件）与电源电位（VCC）连接，源电极连接到N型漏极 MOSFET（Q17）和N型MOSFET（Q16）的漏电极连接到逆变器（G16）的输入，并且还连接到连接到接地电位（VSS）的电阻元件（R1）。因此，由于结合了测试机构，所以通过仅具有一个数据判断电路的便宜的测试器进行并行测试，然后通过使用相同的测试器单独判断比较结果，可以判断半导体存储器件的鉴定。

34. 发明授权

US5636163A Random access memory with a plurality amplifier groups for reading and writing in normal and test modes 失效
标题翻译：具有多个放大器组的随机存取存储器，用于在正常和测试模式下进行读写
公开(公告)号：US5636163A
公开(公告)日：1997-06-03
申请号：US632967
申请日：1996-04-16
申请人： Kiyohiro Furutani , Koichiro Mashiko , Kazutami Arimoto , Noriaki Matsumoto , Yoshio Matsuda
发明人： Kiyohiro Furutani , Koichiro Mashiko , Kazutami Arimoto , Noriaki Matsumoto , Yoshio Matsuda
IPC分类号： G11C11/401 , G06F11/267 , G11C7/10 , G11C11/409 , G11C29/00 , G11C29/26 , G11C29/34 , G11C29/38 , G11C7/00
CPC分类号： G11C7/1057 , G11C29/26 , G11C29/38 , G11C7/10 , G11C7/1006 , G11C7/1051 , G11C7/1078 , G11C7/1084 , G06F11/267
摘要： A semiconductor memory device operable for reading and writing in a normal mode and in a test mode is divided into memory cell sections each having blocks of memory cells. Data bus lines are connected to the respective blocks, and switches interconnect data bus lines connected to blocks of the different sections. The switch are made conductive during reading and writing in the normal mode and during writing in the test mode, and nonconductive during reading in the test mode. Input data are applied onto the data bus lines connected one of the blocks for writing in the blocks of the sections simultaneously during writing in the normal mode and in the test mode. In the normal mode, data are read out of the blocks of the sections through the data bus lines connected to the above-mentioned one of the blocks. In the test mode, the data are read out of the blocks of the sections through the data bus lines connected to the respective blocks.
摘要翻译：可以以正常模式和测试模式读取和写入的半导体存储器件被分成具有存储单元块的存储单元部分。数据总线连接到相应的块，并且交换连接到不同部分的块的数据总线。在正常模式下读写时，在测试模式下写入期间开关导通，在测试模式下读取期间不导通。在正常模式和测试模式下，输入数据被加到连接在一个块上的数据总线上，以便在写入期间同时在这些块中写入。在正常模式下，通过连接到上述一个块的数据总线，从这些部分的块中读出数据。在测试模式中，通过连接到相应块的数据总线，从这些部分的块中读出数据。

35. 发明授权

US5434533A Reference voltage generating circuit temperature-compensated without addition of manufacturing step and semiconductor device using the same 失效
标题翻译：在不添加制造步骤的情况下进行温度补偿的基准电压发生电路和使用其的半导体装置
公开(公告)号：US5434533A
公开(公告)日：1995-07-18
申请号：US999067
申请日：1992-12-31
申请人： Kiyohiro Furutani
发明人： Kiyohiro Furutani
IPC分类号： G05F1/56 , G05F1/46 , G05F3/24 , G11C5/14 , G11C11/407 , H01L27/02 , H01L27/10 , H03F1/30 , G05F1/10
CPC分类号： G05F1/463 , G05F3/245 , G11C5/147 , H01L27/0218 , H03F1/301 , Y10S323/907
摘要： In a reference voltage generating circuit having an improved temperature compensation function, a PMOS transistor forming a constant voltage circuit has the same characteristics as a PMOS transistor forming a negative feedback circuit. As an ambient temperature changes, gate-source voltage and drain current characteristics of each transistor are shifted, but temperature compensation is achieved by appropriately setting a drain current of each transistor. Transistors for the temperature compensation can be formed in the same manufacturing steps, so that temperature compensating effect can be obtained without an additional manufacturing step.
摘要翻译：在具有改善的温度补偿功能的参考电压产生电路中，形成恒压电路的PMOS晶体管具有与形成负反馈电路的PMOS晶体管相同的特性。随着环境温度的变化，每个晶体管的栅极 - 源极电压和漏极电流特性被移动，但通过适当地设置每个晶体管的漏极电流来实现温度补偿。用于温度补偿的晶体管可以在相同的制造步骤中形成，使得可以在没有额外的制造步骤的情况下获得温度补偿效果。

36. 发明授权

US5053638A Semiconductor neural circuit device having capacitive coupling and operating method thereof 失效
标题翻译：具有电容耦合的半导体神经电路器件及其操作方法
公开(公告)号：US5053638A
公开(公告)日：1991-10-01
申请号：US489169
申请日：1990-03-06
申请人： Kiyohiro Furutani , Koichiro Mashiko
发明人： Kiyohiro Furutani , Koichiro Mashiko
IPC分类号： G06F15/18 , G06N3/06 , G06N3/063 , G06N99/00
CPC分类号： G06N3/0635 , G06N3/063
摘要： A neural circuit device modeled on vital cells includes a plurality of first signal lines to which signals to be computed are transferred, a plurality of amplifiers serving as the bodies of the vital cells, a plurality of second signal lines arranged to intersect with the first signal lines in correspondence to the respective amplifiers, and a plurality of coupling elements provided in crossings between the first and second signal lines. Each of the coupling elements is adapted to couple an associated first signal line with an associated second signal line in a specific degree of coupling, and includes a first capacitive element storing information of the degree of coupling in the form of charges, and a circuit which converts a signal potential of the associated first signal line along the coupling degree information stored in the first capacitive element to transfer the converted potential to the associated second signal line without feeding current between an operation power source or a ground potential and the associated second signal line. This conversion/transfer circuit includes a circuit which causes potential change on the second signal line through charge pumping function or charging function. The amplifiers as the neuron bodies include a capacitive coupling element at their inputs.
摘要翻译：以生物体细胞为模型的神经电路装置包括多个要被计算的信号被传送的第一信号线，用作生命体的体的多个放大器，多个第二信号线，被布置成与第一信号相交对应于各个放大器的线，以及在第一和第二信号线之间交叉设置的多个耦合元件。每个耦合元件适于将相关的第一信号线与特定耦合度的相关联的第二信号线耦合，并且包括以电荷形式存储耦合程度的信息的第一电容元件，以及电路沿着存储在第一电容元件中的耦合度信息转换相关联的第一信号线的信号电位，以将转换的电位转移到相关联的第二信号线，而不在工作电源或地电位之间馈送电流和相关联的第二信号线。该转换/传送电路包括通过电荷泵浦功能或充电功能引起第二信号线上的电位变化的电路。作为神经元体的放大器在其输入端包括电容耦合元件。

37. 发明授权

US4979013A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US4979013A
公开(公告)日：1990-12-18
申请号：US348188
申请日：1989-05-08
申请人： Kiyohiro Furutani , Koichiro Mashiko , Kazutami Arimoto
发明人： Kiyohiro Furutani , Koichiro Mashiko , Kazutami Arimoto
IPC分类号： H01L27/10 , G11C11/403 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10829 , Y10S257/911 , Y10S257/922
摘要： A semiconductor memory device having a memory cell array of a folded bit line configuration comprises memory cells, two each of which are formed to share a contact hole and surrounded by an isolation trench, and data charge storage capacitance formed on the entire sidewall of the isolation trench except a part of the isolation trench where an isolation oxide film is formed on the sidewall of the isolation trench. The isolation oxide film separates the two memory cells from each other. One word line passes through a region for one bit memory cell, and two bit lines pass through a region for one bit memory cell.
摘要翻译：具有折叠位线配置的存储单元阵列的半导体存储器件包括存储单元，其中的每一个被形成为共享接触孔并被隔离沟槽包围，并且形成在隔离层的整个侧壁上的数据电荷存储电容沟槽，除了在隔离沟槽的侧壁上形成隔离氧化膜的隔离沟槽的一部分。隔离氧化膜将两个存储单元彼此分开。一个字线通过一个位存储单元的区域，两个位线通过一位存储单元的区域。

38. 发明授权

US4849938A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US4849938A
公开(公告)日：1989-07-18
申请号：US76401
申请日：1987-07-22
申请人： Kiyohiro Furutani , Koichiro Mashiko , Kazutami Arimoto , Noriaki Matsumoto , Yoshio Matsuda
发明人： Kiyohiro Furutani , Koichiro Mashiko , Kazutami Arimoto , Noriaki Matsumoto , Yoshio Matsuda
IPC分类号： G11C11/401 , G11C11/408 , G11C29/00 , G11C29/04
CPC分类号： G11C29/844
摘要： In a semiconductor memory device of a redundancy configuration having lines (rows or columns) of main memory cells and a line of spare memory cells made to substitute a defective line responsive to the address of the defective line, a comparator compares an address input to the memory device, with the address of the defective line which has been programmed in it, and a spare line selector selects the spare line when the input address is found to coincide with the programmed address. A line decoder is responsive to the input address for selecting one of the lines of the normal memory cells, and is inactivated by the output of the comparator when the input address is found to coincide with the programmed address. An input address to the line decoder is applied before the same input address is applied to the comparator.
摘要翻译：在具有主存储单元的行（行或列）和响应于缺陷行的地址而替代缺陷行的备用存储单元的行的冗余配置的半导体存储器件中，比较器将输入到存储器件，其中已经编程的缺陷线的地址，并且当发现输入地址与编程地址一致时，备用线选择器选择备用线。行解码器响应于输入地址以选择正常存储器单元的一行，并且当发现输入地址与编程地址一致时，比较器的输出被非激活。在将相同的输入地址应用于比较器之前，施加到线路解码器的输入地址。

39. 发明授权

US4833653A Dynamic random access memory having selectively activated subarrays 失效
标题翻译：具有选择性激活的子阵列的动态随机存取存储器
公开(公告)号：US4833653A
公开(公告)日：1989-05-23
申请号：US94642
申请日：1987-09-09
申请人： Koichiro Mashiko , Kazutami Arimoto , Kiyohiro Furutani , Noriaki Matsumoto , Yoshio Matsuda
发明人： Koichiro Mashiko , Kazutami Arimoto , Kiyohiro Furutani , Noriaki Matsumoto , Yoshio Matsuda
IPC分类号： G11C11/401 , G11C11/409 , G11C11/4091 , G11C11/4097
CPC分类号： G11C11/4091 , G11C11/4097
摘要： A DRAM of a partially activating system, in which, in an active cycle, sense amplifiers (91a, 91b) are inactivated and the potential on each pair of bit lines (BLA1, BLA1, BLA2, BLA2) is equalized early in the active cycle only for a subarray to be accessed while the potential is not equalized and the sense amplifiers are kept to be activated for a subarray not to be accessed. At the time of an inactive cycle, all the sense amplifiers (91a, 91b) are activated, and the bit lines (BLA1, BLA1, BLA2, BLA2) in the memory cell array are at an "H" or "L" level depending on information read out in the previous active cycle.
摘要翻译：部分激活系统的DRAM，其中在有效周期中，感测放大器（91a，91b）被去激活，并且每对位线（BLA1，＆amp; B，BA2，＆amp; B＆B）上的电位在只有当电位不均衡时才对待访问的子阵列进行有效周期，并且为不被访问的子阵列保持激活读出放大器。在非活动周期时，所有读出放大器（91a，91b）都被激活，并且存储单元阵列中的位线（BLA1，＆amp; B，B，BLA2，＆UPBALB和B）处于“H”或“L” 取决于在上一个活动周期中读出的信息。

40. 发明授权

US08675422B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08675422B2
公开(公告)日：2014-03-18
申请号：US13204276
申请日：2011-08-05
申请人： Kiyohiro Furutani , Yoshinori Matsui
发明人： Kiyohiro Furutani , Yoshinori Matsui
IPC分类号： G11C7/06
CPC分类号： G11C11/4074 , G11C5/147
摘要： A semiconductor device includes an internal circuit and an internal voltage generation circuit which generates an internal voltage stabilized with respect to a variation of the power supply voltage supplied from the outside and supplies the internal voltage to the internal circuit. The internal voltage generation circuit performs control so that when the power supply voltage rises to exceed a predetermined value, an operation of stabilizing the internal voltage is stopped to cause the internal voltage to increase with the rise of the power supply voltage.
摘要翻译：半导体器件包括内部电路和内部电压产生电路，其产生相对于从外部提供的电源电压的变化而稳定的内部电压并将内部电压提供给内部电路。内部电压产生电路执行控制，使得当电源电压上升到超过预定值时，停止内部电压稳定的操作，以使内部电压随着电源电压的上升而增加。

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