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31. 发明授权

US06194759B1 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US06194759B1
公开(公告)日：2001-02-27
申请号：US09436225
申请日：1999-11-09
申请人： Toshiaki Sano , Tomoyuki Ishii , Kazuo Yano , Toshiyuki Mine
发明人： Toshiaki Sano , Tomoyuki Ishii , Kazuo Yano , Toshiyuki Mine
IPC分类号： H01L2976
CPC分类号： B82Y10/00 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C11/5671 , G11C16/0416 , G11C16/10 , G11C16/16 , G11C16/26 , G11C2216/08 , H01L27/115 , H01L29/42324 , H01L29/66825 , H01L29/7883 , H01L29/7888
摘要： A memory cell with a small surface area is fabricated by forming source lines and data lines above and below and by running the channels to face up and down. The local data lines for each vertically stacked memory cell are connected to a global data line by way of separate selection by a molecular oxide semiconductor, and use of a large surface area is avoided by making joint use of peripheral circuits such as global data lines and sensing amplifiers by performing read and write operations in a timed multiplex manner. Moreover, data lines in multi-layers and memory cells (floating electrode cell) which are non-destructive with respect to readout are utilized to allow placement of memory cells at all intersecting points of word lines and data lines while having a folded data line structure. An improved noise tolerance is attained by establishing a standard threshold voltage for identical dummy cells even in any of the read verify, write verify and erase verify operations. A register to temporarily hold write data in a memory cell during writing is also used as a register to hold a flag showing that writing has ended during write verify. Also, a circuit comprised of one nMOS transistor is utilized as a means to change values on the write-end flag.
摘要翻译：通过在上下形成源极线和数据线，并且通过使通道正面上下而制造具有小表面积的存储单元。每个垂直堆叠的存储单元的本地数据线通过分子氧化物半导体的单独选择连接到全局数据线，并且通过联合使用诸如全局数据线和外围电路的外围电路来避免使用大的表面积通过以定时复用方式执行读和写操作来感测放大器。此外，利用相对于读出非破坏性的多层和存储单元（浮动电极单元）中的数据线，以允许在字线和数据线的所有交叉点处放置存储单元，同时具有折叠的数据线结构。即使在读取验证，写入验证和擦除验证操作中的任何一个中，通过建立用于相同虚拟单元的标准阈值电压来获得改善的噪声容限。在写入期间暂时保持写入数据在存储单元中的寄存器也被用作寄存器来保存写入验证期间写入结束的标志。此外，由一个nMOS晶体管组成的电路被用作改变写入端标志的值的手段。

32. 发明授权

US6040605A Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US6040605A
公开(公告)日：2000-03-21
申请号：US236630
申请日：1999-01-26
申请人： Toshiaki Sano , Tomoyuki Ishii , Kazuo Yano , Toshiyuki Mine
发明人： Toshiaki Sano , Tomoyuki Ishii , Kazuo Yano , Toshiyuki Mine
IPC分类号： G11C11/56 , G11C16/04 , G11C16/10 , G11C16/16 , G11C16/26 , H01L21/336 , H01L27/115 , H01L29/423 , H01L29/788 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113
CPC分类号： B82Y10/00 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C11/5671 , G11C16/0416 , G11C16/10 , G11C16/16 , G11C16/26 , H01L27/115 , H01L29/42324 , H01L29/66825 , H01L29/7883 , H01L29/7888 , G11C2216/08
摘要： A memory cell with a small surface area is fabricated by forming source lines and data lines above and below and by running the channels to face up and down. The local data lines for each vertically stacked memory cell are connected to a global data line by way of separate selection by a molecular oxide semiconductor, and use of a large surface area is avoided by making joint use of peripheral circuits such as global data lines and sensing amplifiers by performing read and write operations in a timed multiplex manner. Moreover, data lines in multi-layers and memory cells (floating electrode cell) which are non-destructive with respect to readout are utilized to allow placement of memory cells at all intersecting points of word lines and data lines while having a folded data line structure. An improved noise tolerance is attained by establishing a standard threshold voltage for identical dummy cells even in any of the read verify, write verify and erase verify operations. A register to temporarily hold write data in a memory cell during writing is also used as a register to hold a flag showing that writing has ended during write verify. Also, a circuit comprised of one nMOS transistor is utilized as a means to change values on the write-end flag.
摘要翻译：通过在上下形成源极线和数据线，并且通过使通道正面上下而制造具有小表面积的存储单元。每个垂直堆叠的存储单元的本地数据线通过分子氧化物半导体的单独选择连接到全局数据线，并且通过联合使用诸如全局数据线和外围电路的外围电路来避免使用大的表面积通过以定时复用方式执行读和写操作来感测放大器。此外，利用相对于读出非破坏性的多层和存储单元（浮动电极单元）中的数据线，以允许在字线和数据线的所有交叉点处放置存储单元，同时具有折叠的数据线结构。即使在读取验证，写入验证和擦除验证操作中的任何一个中，通过建立用于相同虚拟单元的标准阈值电压来获得改善的噪声容限。在写入期间暂时保持写入数据在存储单元中的寄存器也被用作寄存器来保存写入验证期间写入结束的标志。此外，由一个nMOS晶体管组成的电路被用作改变写入端标志的值的手段。

33. 发明授权

US5960266A Process for manufacturing a quantum memory element device 失效
标题翻译：制造量子存储元件装置的方法
公开(公告)号：US5960266A
公开(公告)日：1999-09-28
申请号：US878206
申请日：1997-06-18
申请人： Tomoyuki Ishii , Kazuo Yano , Koichi Seki , Toshiyuki Mine , Takashi Kobayashi
发明人： Tomoyuki Ishii , Kazuo Yano , Koichi Seki , Toshiyuki Mine , Takashi Kobayashi
IPC分类号： H01L27/115 , H01L27/12 , H01L29/68 , H01L29/788 , H01L21/00 , H01L21/31 , H01L21/469 , H01L21/84
CPC分类号： H01L29/7887 , H01L27/115 , H01L27/1203 , H01L29/685 , H01L29/7883 , Y10S438/962
摘要： A quantum semiconductor memory element is disclosed which can share the terminals easily among a plurality of memory elements and can pass a high current and which is resistant to interference from noises. In order to accomplish this a control electrode is formed to cover the entirety of thin film regions connecting low-resistance regions. As a result, the element can have a small size and can store information with high density. Thus, a highly integrated, low power consumption non-volatile quantum memory device can be realized with reduced size.
摘要翻译：公开了一种量子半导体存储元件，其可以容易地在多个存储元件之间共享端子，并且可以通过高电流并且能够抵抗来自噪声的干扰。为了实现这一点，形成控制电极以覆盖连接低电阻区域的整个薄膜区域。因此，该元件可以具有小尺寸并且可以高密度地存储信息。因此，可以以减小的尺寸实现高度集成的低功耗非易失性量子存储器件。

34. 再颁专利

USRE41868E1 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：USRE41868E1
公开(公告)日：2010-10-26
申请号：US11708145
申请日：2007-02-20
申请人： Toshiaki Sano , Tomoyuki Ishii , Kazuo Yano , Toshiyuki Mine
发明人： Toshiaki Sano , Tomoyuki Ishii , Kazuo Yano , Toshiyuki Mine
IPC分类号： H01L29/76 , H01L29/788
CPC分类号： B82Y10/00 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C11/5671 , G11C16/0416 , G11C16/10 , G11C16/16 , G11C16/26 , G11C2216/08 , H01L21/28273 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L29/42324 , H01L29/66825 , H01L29/7883 , H01L29/7888 , H01L29/7889
摘要： A memory cell with a small surface area is fabricated by forming source lines and data lines above and below and by running the channels to face up and down. The local data lines for each vertically stacked memory cell are connected to a global data line by way of separate selection by a molecular oxide semiconductor, and use of a large surface area is avoided by making joint use of peripheral circuits such as global data lines and sensing amplifiers by performing read and write operations in a timed multiplex manner. Moreover, data lines in multi-layers and memory cells (floating electrode cell) which are non-destructive with respect to readout are utilized to allow placement of memory cells at all intersecting points of word lines and data lines while having a folded data line structure. An improved noise tolerance is attained by establishing a standard threshold voltage for identical dummy cells even in any of the read verify, write verify and erase verify operations. A register to temporarily hold write data in a memory cell during writing is also used as a register to hold a flag showing that writing has ended during write verify. Also, a circuit comprised of one nMOS transistor is utilized as a means to change values on the write-end flag.
摘要翻译：通过在上下形成源极线和数据线，并且通过使通道正面上下而制造具有小表面积的存储单元。每个垂直堆叠的存储单元的本地数据线通过分子氧化物半导体的单独选择连接到全局数据线，并且通过联合使用诸如全局数据线和外围电路的外围电路来避免使用大的表面积通过以定时复用方式执行读和写操作来感测放大器。此外，利用相对于读出非破坏性的多层和存储单元（浮动电极单元）中的数据线，以允许在字线和数据线的所有交叉点处放置存储单元，同时具有折叠的数据线结构。即使在读取验证，写入验证和擦除验证操作中的任何一个中，通过建立用于相同虚拟单元的标准阈值电压来获得改善的噪声容限。在写入期间暂时保持写入数据在存储单元中的寄存器也被用作寄存器来保存写入验证期间写入结束的标志。此外，由一个nMOS晶体管组成的电路被用作改变写入端标志的值的手段。

35. 发明申请

US20080061298A1 SEMICONDUCTOR ELEMENT AND SEMICONDUCTOR MEMORY DEVICE USING THE SAME 审中-公开
标题翻译：半导体元件和半导体存储器件使用它
公开(公告)号：US20080061298A1
公开(公告)日：2008-03-13
申请号：US11931369
申请日：2007-10-31
申请人： Kazuo YANO , Tomoyuki Ishii , Takashi Hashimoto , Koichi Seki , Masakazu Aoki , Takeshi Sakata , Yoshinobu Nakagome , Kan Takeuchi
发明人： Kazuo YANO , Tomoyuki Ishii , Takashi Hashimoto , Koichi Seki , Masakazu Aoki , Takeshi Sakata , Yoshinobu Nakagome , Kan Takeuchi
IPC分类号： H01L29/04 , H01L29/78
CPC分类号： B82Y10/00 , G11C11/22 , G11C11/404 , G11C16/02 , G11C16/0466 , G11C16/10 , G11C16/28 , G11C2216/06 , G11C2216/08 , H01L21/8221 , H01L27/0688 , H01L27/105 , H01L27/115 , H01L27/11526 , H01L27/11546 , H01L27/11551 , H01L27/1203 , H01L29/40114 , H01L29/42328 , H01L29/513 , H01L29/66825 , H01L29/7613 , H01L29/785 , H01L29/7888
摘要： A semiconductor memory device includes a plurality of memory cells, each including, a source region formed of a semiconductor material, a drain region formed of the semiconductor material, and a first region formed of the semiconductor material and located between the source region and the drain region. First and second insulator films sandwich the first region and a first gate electrode is connected to the first region through the first insulator film. In this arrangement, the first region is adapted to accumulate charges corresponding to stored information.
摘要翻译：半导体存储器件包括多个存储器单元，每个存储单元包括由半导体材料形成的源极区域，由半导体材料形成的漏极区域和由半导体材料形成并位于源极区域和漏极之间的第一区域地区。第一和第二绝缘膜夹着第一区域，第一栅电极通过第一绝缘膜连接到第一区域。在这种布置中，第一区域适于累积对应于存储的信息的费用。

36. 发明申请

US20060208315A1 Semiconductor element and semiconductor memory device using the same 失效
公开(公告)号：US20060208315A1
公开(公告)日：2006-09-21
申请号：US11439152
申请日：2006-05-24
申请人： Kazuo Yano , Tomoyuki Ishii , Takashi Hashimoto , Koichi Seki , Masakazu Aoki , Takeshi Sakata , Yoshinobu Nakagome , Kan Takeuchi
发明人： Kazuo Yano , Tomoyuki Ishii , Takashi Hashimoto , Koichi Seki , Masakazu Aoki , Takeshi Sakata , Yoshinobu Nakagome , Kan Takeuchi
IPC分类号： H01L29/76
CPC分类号： B82Y10/00 , G11C11/22 , G11C11/404 , G11C16/02 , G11C16/0466 , G11C16/10 , G11C16/28 , G11C2216/06 , G11C2216/08 , H01L21/28273 , H01L21/8221 , H01L27/0688 , H01L27/105 , H01L27/115 , H01L27/11526 , H01L27/11546 , H01L27/11551 , H01L27/1203 , H01L29/42328 , H01L29/513 , H01L29/66825 , H01L29/7613 , H01L29/785 , H01L29/7888
摘要： A field-effect semiconductor element implemented with a fewer number of elements and a reduced area and capable of storing data by itself without need for cooling at a cryogenic temperature, and a memory device employing the same. Gate-channel capacitance is set so small that whether or not a trap captures one electron or hole can definitely and distinctively be detected in terms of changes of a current of the semiconductor FET element. By detecting a change in a threshold voltage of the semiconductor element brought about by trapping of electron or hole in the trap, data storage can be realized at a room temperature.

37. 发明授权

US06674117B2 Semiconductor element and semiconductor memory device using the same 失效
公开(公告)号：US06674117B2
公开(公告)日：2004-01-06
申请号：US09915588
申请日：2001-07-27
申请人： Kazuo Yano , Tomoyuki Ishii , Takashi Hashimoto , Koichi Seki , Masakazu Aoki , Takeshi Sakata , Yoshinobu Nakagome , Kan Takeuchi
发明人： Kazuo Yano , Tomoyuki Ishii , Takashi Hashimoto , Koichi Seki , Masakazu Aoki , Takeshi Sakata , Yoshinobu Nakagome , Kan Takeuchi
IPC分类号： H01L2976
CPC分类号： B82Y10/00 , G11C11/22 , G11C11/404 , G11C16/02 , G11C16/0466 , G11C16/10 , G11C16/28 , G11C2216/06 , G11C2216/08 , H01L21/28273 , H01L21/8221 , H01L27/0688 , H01L27/105 , H01L27/115 , H01L27/11526 , H01L27/11546 , H01L27/11551 , H01L27/1203 , H01L29/42328 , H01L29/513 , H01L29/66825 , H01L29/7613 , H01L29/785 , H01L29/7888
摘要： A field-effect semiconductor element implemented with a fewer number of elements and a reduced area and capable of storing data by itself without need for cooling at a cryogenic temperature, and a memory device employing the same. Gate-channel capacitance is set so small that whether or not a trap captures one electron or hole can definitely and distinctively be detected in terms of changes of a current of the semiconductor FET element. By detecting a change in a threshold voltage of the semiconductor element brought about by trapping of electron or hole in the trap, data storage can be realized at a room temperature.

38. 发明授权

US06576943B1 Semiconductor device for reducing leak currents and controlling a threshold voltage and using a thin channel structure 失效
标题翻译：用于减少泄漏电流并控制阈值电压并使用薄沟道结构的半导体器件
公开(公告)号：US06576943B1
公开(公告)日：2003-06-10
申请号：US09512827
申请日：2000-02-25
申请人： Tomoyuki Ishii , Kazuo Yano , Toshiyuki Mine
发明人： Tomoyuki Ishii , Kazuo Yano , Toshiyuki Mine
IPC分类号： H01L27108
CPC分类号： G11C16/0433 , H01L27/105 , H01L27/108 , H01L27/10873 , H01L27/12 , H01L27/1203 , H01L29/78642
摘要： A very thin semiconductor film is used for channels of semiconductor memory elements such that leak currents are reduced by the quantum-mechanical containment effect in the direction of film thickness. The amount of electrical charge accumulated in each charge accumulating region is used to change the conductance between a source region and a drain region of each read transistor structure. This conductance change is utilized for data storage. The thickness of the channel of the write transistor structure is preferably no more than 5 nm. According to one embodiment, the channel of the write transistor is formed by a semiconductor film deposited on a surface intersecting a principal plane of the substrate.
摘要翻译：非常薄的半导体膜用于半导体存储元件的通道，使得漏电流通过膜厚度方向的量子力学容纳效应而降低。使用在每个电荷累积区域中累积的电荷量来改变每个读取的晶体管结构的源极区域和漏极区域之间的电导。该电导变化用于数据存储。写入晶体管结构的沟道的厚度优选不大于5nm。根据一个实施例，写入晶体管的沟道由沉积在与衬底的主平面相交的表面上的半导体膜形成。

39. 发明授权

US06291852B1 Semiconductor element and semiconductor memory device using the same 失效
标题翻译：半导体元件和使用其的半导体存储器件
公开(公告)号：US06291852B1
公开(公告)日：2001-09-18
申请号：US09521970
申请日：2000-03-09
申请人： Kazuo Yano , Tomoyuki Ishii , Takashi Hashimoto , Koichi Seki , Masakazu Aoki , Takeshi Sakata , Yoshinobu Nakagome , Kan Takeuchi
发明人： Kazuo Yano , Tomoyuki Ishii , Takashi Hashimoto , Koichi Seki , Masakazu Aoki , Takeshi Sakata , Yoshinobu Nakagome , Kan Takeuchi
IPC分类号： H01L2976
CPC分类号： B82Y10/00 , G11C11/22 , G11C11/404 , G11C16/02 , G11C16/0466 , G11C16/10 , G11C16/28 , G11C2216/06 , G11C2216/08 , H01L21/28273 , H01L21/8221 , H01L27/0688 , H01L27/105 , H01L27/115 , H01L27/11526 , H01L27/11546 , H01L27/11551 , H01L27/1203 , H01L29/42328 , H01L29/513 , H01L29/66825 , H01L29/7613 , H01L29/785 , H01L29/7888
摘要： A field-effect semiconductor element implemented with a reduced number of elements and a reduced area and capable of storing data by itself without need for cooling at a cryogenic temperature, and a memory device employing the same. Gate-channel capacitance is set so small that whether or not a trap captures one electron or hole can definitely and distinctively be detected in terms of changes of a current of the semiconductor FET element. By detecting a change in a threshold voltage of the semiconductor element brought about by trapping of electron or hole in the trap, data storage can be realized at a room temperature. In accordance with one embodiment, a carrier confinement region, isolated from a channel and a gate of the semiconductor FET element, is provided to operate as a storage node for trapping the carrier or carriers.
摘要翻译：一种场效应半导体元件，其具有减少的元件数量和减少的面积，并且能够自身存储数据，而不需要在低温下进行冷却;以及采用该半导体元件的存储器件。栅极沟道电容被设置得如此小，以致捕获捕获一个电子或空穴是否可以根据半导体FET元件的电流的变化来明确且明显地被检测。通过检测通过在陷阱中捕获电子或空穴而导致的半导体元件的阈值电压的变化，可以在室温下实现数据存储。根据一个实施例，提供了从沟道隔离的载流子限制区域和半导体FET元件的栅极，以用作捕获载体或载流子的存储节点。

40. 发明申请

US20050205921A1 Gain cell type non-volatile memory having charge accumulating region charges or discharged by channel current from a thin film channel path 审中-公开
标题翻译：具有电荷累积区域的增益单元型非易失性存储器从薄膜通道路径充电或通过沟道电流放电
公开(公告)号：US20050205921A1
公开(公告)日：2005-09-22
申请号：US11055995
申请日：2005-02-14
申请人： Tomoyuki Ishii , Kazuo Yano , Toshiyuki Mine
发明人： Tomoyuki Ishii , Kazuo Yano , Toshiyuki Mine
IPC分类号： H01L21/8247 , G11C16/04 , H01L21/8242 , H01L21/8244 , H01L27/105 , H01L27/108 , H01L27/11 , H01L27/115 , H01L27/12 , H01L29/66 , H01L29/786 , H01L29/788 , H01L29/792
CPC分类号： G11C16/0433 , H01L27/105 , H01L27/108 , H01L27/10873 , H01L27/12 , H01L27/1203 , H01L29/78642
摘要： A very thin semiconductor film is used for channels of semiconductor memory elements such that leak currents are reduced by the quantum-mechanical containment effect in the direction of film thickness. The amount of electrical charge accumulated in each charge accumulating region is used to change conductance between a source and a drain region of each read transistor structure. The conductance change is utilized for data storage. The thickness of the channel of the write transistor structure is preferably no more than 5 nm. According to one embodiment, the channel of the write transistor is formed by a semiconductor film deposited on a surface intersecting a principal plane of the substrate.
摘要翻译：非常薄的半导体膜用于半导体存储元件的通道，使得漏电流通过膜厚度方向的量子力学容纳效应而降低。每个电荷累积区域中累积的电荷量用于改变每个读取晶体管结构的源区和漏区之间的电导。电导变化用于数据存储。写入晶体管结构的沟道的厚度优选不大于5nm。根据一个实施例，写入晶体管的沟道由沉积在与衬底的主平面相交的表面上的半导体膜形成。

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