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31. 发明授权

US08227787B2 Heterojunction device comprising a semiconductor and a resistivity-switching oxide or nitride 有权
标题翻译：异质结装置包括半导体和电阻率切换氧化物或氮化物
公开(公告)号：US08227787B2
公开(公告)日：2012-07-24
申请号：US13007812
申请日：2011-01-17
申请人： Tanmay Kumar , S. Brad Herner
发明人： Tanmay Kumar , S. Brad Herner
IPC分类号： H01L29/02 , H01L47/00
CPC分类号： H01L29/868 , H01L21/84 , H01L27/1021 , H01L27/2409 , H01L29/165 , H01L29/22 , H01L29/267 , H01L29/417 , H01L29/737 , H01L29/8615 , H01L45/04 , H01L45/1233 , H01L45/146
摘要： In the present invention, a metal oxide or nitride compound which is a wide-band-gap semiconductor abuts a silicon, germanium, or alloy of silicon and/or germanium of the opposite conductivity type to form a p-n heterojunction. This p-n heterojunction can be used to advantage in various devices. In preferred embodiments, one terminal of a vertically oriented p-i-n heterojunction diode is a metal oxide or nitride layer, while the rest of the diode is formed of a silicon or silicon-germanium resistor. For example, a diode may include a heavily doped n-type silicon region, an intrinsic silicon region, and a nickel oxide layer serving as the p-type terminal. Many of these metal oxides and nitrides exhibit resistivity-switching behavior, and such a heterojunction diode can be used in a nonvolatile memory cell, for example in a monolithic three dimensional memory array.
摘要翻译：在本发明中，作为宽带隙半导体的金属氧化物或氮化物化合物与相反导电型的硅和/或锗的硅，锗或合金相接触以形成p-n异质结。该p-n异质结可以用于各种装置中。在优选实施例中，垂直取向的p-i-n异质结二极管的一个端子是金属氧化物或氮化物层，而二极管的其余部分由硅或硅 - 锗电阻器形成。例如，二极管可以包括重掺杂的n型硅区，本征硅区和用作p型端的氧化镍层。这些金属氧化物和氮化物中的许多表现出电阻率切换行为，并且这种异质结二极管可以用在非易失性存储单元中，例如在单片三维存储器阵列中。

32. 发明授权

US07982273B2 Masking of repeated overlay and alignment marks to allow reuse of photomasks in a vertical structure 有权
标题翻译：掩盖重复的覆盖和对准标记，以允许在垂直结构中重复使用光掩模
公开(公告)号：US07982273B2
公开(公告)日：2011-07-19
申请号：US12470886
申请日：2009-05-22
申请人： Yung-Tin Chen , Christopher J. Petti , Steven J. Radigan , Tanmay Kumar
发明人： Yung-Tin Chen , Christopher J. Petti , Steven J. Radigan , Tanmay Kumar
IPC分类号： H01L29/76
CPC分类号： H01L27/0688 , G03F7/70633 , G03F9/7084 , H01L23/544 , H01L2223/5442 , H01L2223/54426 , H01L2223/5446
摘要： A monolithic three dimensional semiconductor device structure includes a first layer including a first occurrence of a first reference mark at a first location, and a second layer including a second occurrence of the first reference mark at a second location, wherein the second location is substantially directly above the first location. The device structure also includes an intermediate layer between the first layer and the second layer, the intermediate layer including a blocking structure, wherein the blocking structure is vertically interposed between the first occurrence of the first reference mark and the second occurrence of the first reference mark. Other aspects are also described.
摘要翻译：单片三维半导体器件结构包括第一层，其包括在第一位置处的第一参考标记的第一次出现，以及包括在第二位置处的第二参考标记的第二次出现的第二层，其中第二位置基本上直接在第一个位置以上。所述器件结构还包括在所述第一层和所述第二层之间的中间层，所述中间层包括阻挡结构，其中所述阻挡结构垂直插入所述第一参考标记的第一次出现和所述第一参考标记的第二次出现之间。还描述了其他方面。

33. 发明授权

US07915164B2 Method for forming doped polysilicon via connecting polysilicon layers 有权
公开(公告)号：US07915164B2
公开(公告)日：2011-03-29
申请号：US12897696
申请日：2010-10-04
申请人： Michael W. Konevecki , Usha Raghuram , Maitreyee Mahajani , Sucheta Nallamothu , Andrew J. Walker , Tanmay Kumar
发明人： Michael W. Konevecki , Usha Raghuram , Maitreyee Mahajani , Sucheta Nallamothu , Andrew J. Walker , Tanmay Kumar
IPC分类号： H01L21/8246 , H01L21/768
CPC分类号： H01L27/12 , H01L21/28282 , H01L21/84 , H01L23/535 , H01L27/0688 , H01L27/115 , H01L27/11521 , H01L27/11551 , H01L27/11568 , H01L27/11578 , H01L29/792 , H01L2924/0002 , H01L2924/00
摘要： The invention provides for polysilicon vias connecting conductive polysilicon layers formed at different heights. Polysilicon vias are advantageously used in a monolithic three dimensional memory array of charge storage transistors. Polysilicon vias according to the present invention can be used, for example, to connect the channel layer of a first device level of charge storage transistor memory cells to the channel layer of a second device layer of such cells formed above the first device level. Similarly, vias according to the present invention can be used to connect the wordline of a first device level of charge storage transistor memory cells to the channel layer of a second device layer of such cells.

34. 发明授权

US07915094B2 Method of making a diode read/write memory cell in a programmed state 有权
标题翻译：使二极管读/写存储单元处于编程状态的方法
公开(公告)号：US07915094B2
公开(公告)日：2011-03-29
申请号：US12588088
申请日：2009-10-02
申请人： Tanmay Kumar , S. Brad Herner
发明人： Tanmay Kumar , S. Brad Herner
IPC分类号： H01L21/82
CPC分类号： G11C13/0069 , G11C11/5692 , G11C17/14 , G11C17/165 , G11C17/18 , G11C2013/0073 , H01L27/101 , H01L27/1021 , H01L29/868
摘要： A method of making a nonvolatile memory device includes fabricating a diode in a low resistivity, programmed state without an electrical programming step. The memory device includes at least one memory cell. The memory cell is constituted by the diode and electrically conductive electrodes contacting the diode.
摘要翻译：制造非易失性存储器件的方法包括在没有电气编程步骤的情况下制造低电阻率编程状态的二极管。存储器件包括至少一个存储单元。存储单元由二极管和与二极管接触的导电电极构成。

35. 发明授权

US07859887B2 Multilevel nonvolatile memory device containing a carbon storage material and methods of making and using same 有权
标题翻译：含有碳储存材料的多层非易失性存储器件及其制造和使用方法
公开(公告)号：US07859887B2
公开(公告)日：2010-12-28
申请号：US12153873
申请日：2008-05-27
申请人： Xiying Chen , Tanmay Kumar
发明人： Xiying Chen , Tanmay Kumar
IPC分类号： G11C11/00
CPC分类号： G11C13/00 , B82Y10/00 , G11C11/56 , G11C13/0069 , G11C13/025 , G11C17/16 , G11C17/165 , G11C2013/0083 , G11C2013/009 , G11C2013/0092 , G11C2213/19 , G11C2213/35 , G11C2213/72
摘要： A method of programming a nonvolatile memory cell includes applying at least one initialization pulse having a duration of at least 1 ms, followed by applying plural programming pulses having a duration of less than 1 ms. The cell includes a steering element located in series with a storage element, and the storage element includes a carbon material.
摘要翻译：非易失性存储单元的编程方法包括施加至少一个具有至少1ms的持续时间的初始化脉冲，然后施加持续时间小于1ms的多个编程脉冲。电池包括与存储元件串联设置的转向元件，并且存储元件包括碳材料。

36. 发明授权

US07800932B2 Memory cell comprising switchable semiconductor memory element with trimmable resistance 有权
标题翻译：存储单元包括具有可调整电阻的可切换半导体存储元件
公开(公告)号：US07800932B2
公开(公告)日：2010-09-21
申请号：US11237167
申请日：2005-09-28
申请人： Tanmay Kumar , S. Brad Herner
发明人： Tanmay Kumar , S. Brad Herner
IPC分类号： G11C11/00 , G11C11/14 , G11C11/15
CPC分类号： G11C11/5692 , G11C11/005 , G11C11/5685 , G11C13/0007 , G11C13/003 , G11C17/14 , G11C2211/5641 , G11C2211/5646 , G11C2213/32 , G11C2213/71 , G11C2213/72 , G11C2213/76 , H01L27/101 , H01L27/2409 , H01L27/2463 , H01L45/08 , H01L45/1233 , H01L45/148
摘要： A nonvolatile memory cell comprising doped semiconductor material and a diode can store memory states by changing the resistance of the doped semiconductor material by application of a set pulse (decreasing resistance) or a reset pulse (increasing resistance.) Set pulses are of short duration and above a threshold voltage, while reset pulses are longer duration and below a threshold voltage. In some embodiments multiple resistance states can be achieved, allowing for a multi-state cell, while restoring a prior high-resistance state allows for an rewriteable cell. In some embodiments, the diode and a switchable memory formed of doped semiconductor material are formed in series, while in other embodiments, the diode itself serves as the semiconductor switchable memory element.
摘要翻译：包括掺杂半导体材料和二极管的非易失性存储单元可以通过施加设置脉冲（降低电阻）或复位脉冲（增加电阻）来改变掺杂半导体材料的电阻来存储存储器状态。设置脉冲的持续时间短，高于阈值电压，而复位脉冲的持续时间更长并低于阈值电压。在一些实施例中，可以实现多个电阻状态，允许多状态单元，同时恢复先前的高电阻状态允许可重写单元。在一些实施例中，二极管和由掺杂半导体材料形成的可切换存储器是串联形成的，而在其它实施例中，二极管本身用作半导体可切换存储元件。

37. 发明授权

US07618850B2 Method of making a diode read/write memory cell in a programmed state 有权
标题翻译：使二极管读/写存储单元处于编程状态的方法
公开(公告)号：US07618850B2
公开(公告)日：2009-11-17
申请号：US11693845
申请日：2007-03-30
申请人： Tanmay Kumar , S. Brad Herner
发明人： Tanmay Kumar , S. Brad Herner
IPC分类号： H01L21/82
CPC分类号： G11C13/0069 , G11C11/5692 , G11C17/14 , G11C17/165 , G11C17/18 , G11C2013/0073 , H01L27/101 , H01L27/1021 , H01L29/868
摘要： A method of making a nonvolatile memory device includes fabricating a diode in a low resistivity, programmed state without an electrical programming step. The memory device includes at least one memory cell. The memory cell is constituted by the diode and electrically conductive electrodes contacting the diode.
摘要翻译：制造非易失性存储器件的方法包括在没有电气编程步骤的情况下制造低电阻率编程状态的二极管。存储器件包括至少一个存储单元。存储单元由二极管和与二极管接触的导电电极构成。

38. 发明申请

US20090085154A1 VERTICAL DIODE BASED MEMORY CELLS HAVING A LOWERED PROGRAMMING VOLTAGE AND METHODS OF FORMING THE SAME 有权
标题翻译：具有降低的编程电压的基于垂直二极管的存储器电池及其形成方法
公开(公告)号：US20090085154A1
公开(公告)日：2009-04-02
申请号：US11864848
申请日：2007-09-28
申请人： S. Brad Herner , Tanmay Kumar
发明人： S. Brad Herner , Tanmay Kumar
IPC分类号： H01L27/102 , H01L21/8229
CPC分类号： H01L27/1021 , G11C17/16 , H01L23/5252 , H01L29/868 , H01L2924/0002 , H01L2924/00
摘要： In a first aspect, a method for forming a non-volatile memory cell is provided. The method includes (1) forming a metal-insulator-metal (MIM) antifuse stack including (a) a first metal layer; (b) a silicon dioxide, oxynitride or silicon nitride antifuse layer formed above the first metal layer; and (c) a second metal layer formed above the antifuse layer. The method also includes (2) forming a contiguous p-i-n diode above the MIM stack, the contiguous p-i-n diode comprising deposited semiconductor material; (3) forming a layer of a silicide, silicide-germanide, or germanide in contact with the deposited semiconductor material; and (4) crystallizing the deposited semiconductor material in contact with the layer of silicide, silicide-germanide, or germanide. The memory cell comprises the contiguous p-i-n diode and the MIM stack. Other aspects are provided.
摘要翻译：在第一方面，提供了一种用于形成非易失性存储单元的方法。该方法包括（1）形成包括（a）第一金属层的金属 - 绝缘体 - 金属（MIM）反熔丝堆叠; （b）形成在第一金属层上方的二氧化硅，氧氮化物或氮化硅反熔层; 和（c）形成在反熔丝层之上的第二金属层。该方法还包括（2）在MIM堆叠之上形成连续的p-i-n二极管，连续的p-i-n二极管包括沉积的半导体材料; （3）形成与沉积的半导体材料接触的硅化物层，硅化锗 - 锗化物或锗化物层; 和（4）使沉积的半导体材料与硅化物，硅化锗 - 锗化物或锗化物层接触。存储单元包括相邻的p-i-n二极管和MIM堆叠。提供其他方面。

39. 发明申请

US20080012065A1 Bandgap engineered charge storage layer for 3D TFT 审中-公开
标题翻译：用于3D TFT的带隙工程电荷存储层
公开(公告)号：US20080012065A1
公开(公告)日：2008-01-17
申请号：US11483671
申请日：2006-07-11
申请人： Tanmay Kumar
发明人： Tanmay Kumar
IPC分类号： H01L29/792
CPC分类号： H01L29/792
摘要： One SONOS-type device contains (a) a charge storage dielectric that includes a band engineered layer that has a wider bandgap facing one of a blocking dielectric and a tunneling dielectric than facing the other one of the blocking dielectric and the tunneling dielectric, and (b) a semiconductor channel region that contains polysilicon. Another SONOS-type device contains a charge storage dielectric that includes a band engineered layer that has a wider bandgap facing one of a blocking dielectric and a tunneling dielectric than facing the other one of the blocking dielectric and the tunneling dielectric. The device is located in a monolithic three dimensional memory array. Yet another SONOS-type device contains a charge storage dielectric that includes a band engineered layer that has a wider bandgap facing one of a blocking dielectric and a tunneling dielectric than facing the other one of the blocking dielectric and the tunneling dielectric and also includes at least one of: (a) a first dielectric layer located between the tunneling dielectric and the band engineered layer, and (b) a second dielectric layer located between the blocking dielectric and the band engineered layer.
摘要翻译：一种SONOS型器件包含（a）电荷存储电介质，其包括带状工程化层，其具有面对阻挡电介质和隧道电介质之一的较宽的带隙，而不是面对阻挡电介质和隧道电介质中的另一个，并且（ b）包含多晶硅的半导体沟道区。另一个SONOS型器件包含电荷存储电介质，其包括带状工程层，其具有面向阻挡电介质和隧道电介质之一的较宽的带隙，而不是面对阻挡电介质和隧道电介质的另一个。该器件位于单片三维存储器阵列中。另一种SONOS型器件包含电荷存储电介质，其包括带状工程化层，其具有面向隔离电介质和隧道电介质之一的宽带隙，而不是面对阻挡电介质和隧道电介质中的另一个，并且还包括至少以下之一：（a）位于隧道电介质和带工程化层之间的第一介电层，和（b）位于阻挡电介质和带工程化层之间的第二电介质层。

40. 发明申请

US20070164309A1 METHOD OF MAKING A DIODE READ/WRITE MEMORY CELL IN A PROGRAMMED STATE 有权
标题翻译：在编程状态下制作二极管读/写存储单元的方法
公开(公告)号：US20070164309A1
公开(公告)日：2007-07-19
申请号：US11693845
申请日：2007-03-30
申请人： Tanmay Kumar , S. Brad Herner
发明人： Tanmay Kumar , S. Brad Herner
IPC分类号： H01L29/43
CPC分类号： G11C13/0069 , G11C11/5692 , G11C17/14 , G11C17/165 , G11C17/18 , G11C2013/0073 , H01L27/101 , H01L27/1021 , H01L29/868
摘要： A method of making a nonvolatile memory device includes fabricating a diode in a low resistivity, programmed state without an electrical programming step. The memory device includes at least one memory cell. The memory cell is constituted by the diode and electrically conductive electrodes contacting the diode.
摘要翻译：制造非易失性存储器件的方法包括在没有电气编程步骤的情况下制造低电阻率编程状态的二极管。存储器件包括至少一个存储单元。存储单元由二极管和与二极管接触的导电电极构成。

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