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31. 发明申请

US20060212652A1 Information processing device and data control method in information processing device 有权
标题翻译：信息处理装置中的信息处理装置和数据控制方法
公开(公告)号：US20060212652A1
公开(公告)日：2006-09-21
申请号：US11169858
申请日：2005-06-30
申请人： Takaharu Ishizuka , Daisuke Itou , Takashi Yamamoto
发明人： Takaharu Ishizuka , Daisuke Itou , Takashi Yamamoto
IPC分类号： G06F12/00 , G06F13/28
CPC分类号： G06F12/0822
摘要： An information processing device of a multiprocessor configuration that can increase significantly the processing capability of read requests. The information processing device comprises a plurality of processing units, a plurality of cache memories for storing temporarily the data read by the plurality of processing units from respective main memories in combination with tag information indicating the state of the data that will be stored, and a system controller for controlling the access of the plurality of processing units to the main memories. The system controller comprises a tag copy unit for holding a copy of the tag information that will be stored in the cache memory, a plurality of write cues for storing write requests, and a store buffer for storing the arbitration results relating to a plurality of write requests that will be stored in the plurality of write cues.
摘要翻译：多处理器配置的信息处理设备可以显着增加读请求的处理能力。信息处理装置包括多个处理单元，多个高速缓存存储器，用于暂时存储来自各个主存储器的多个处理单元读取的数据与表示将被存储的数据的状态的标签信息，以及系统控制器，用于控制多个处理单元对主存储器的访问。系统控制器包括用于保存将被存储在高速缓冲存储器中的标签信息的副本的标签复制单元，用于存储写入请求的多个写入提示，以及用于存储与多个写入有关的仲裁结果的存储缓冲器将存储在多个写入提示中的请求。

32. 发明授权

US07783840B2 Method and apparatus for controlling memory system 有权
标题翻译：用于控制存储器系统的方法和装置
公开(公告)号：US07783840B2
公开(公告)日：2010-08-24
申请号：US10999972
申请日：2004-12-01
申请人： Makoto Hataida , Takao Matsui , Daisuke Itoh , Seishi Okada , Takaharu Ishizuka
发明人： Makoto Hataida , Takao Matsui , Daisuke Itoh , Seishi Okada , Takaharu Ishizuka
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/0833 , G06F12/0811 , G06F12/0817 , G06F2212/507
摘要： A cache-status maintaining unit stores address information of data stored in each entry of a cache memory, and maintains a status of each entry as any one of “strongly modified”, “weakly modified”, “shared”, and “Invalid”. A data-fetching-procedure selecting unit selects, upon receiving a data read request, at least one data fetching procedure based on the address information and the status. A read-data delivering unit selects latest data from among the data fetched, and delivers the latest data to a processor that issued the data read request. A cache-status updating unit updates, when registering the address information of the data, updates the status of the entry based on a type of the data read request.
摘要翻译：高速缓存状态维持单元存储存储在高速缓冲存储器的每个条目中的数据的地址信息，并将每个条目的状态保持为“强修改”，“弱修改”，“共享”和“无效”中的任何一个。数据获取过程选择单元在接收到数据读取请求时，基于地址信息和状态来选择至少一个数据获取过程。读取数据传送单元从获取的数据中选择最新数据，并将最新数据传送到发出数据读取请求的处理器。缓存状态更新单元在注册数据的地址信息时根据数据读取请求的类型来更新条目的状态。

33. 发明申请

US20060031641A1 Method and apparatus for controlling memory system 有权
标题翻译：用于控制存储器系统的方法和装置
公开(公告)号：US20060031641A1
公开(公告)日：2006-02-09
申请号：US10999972
申请日：2004-12-01
申请人： Makoto Hataida , Takao Matsui , Daisuke Itoh , Seishi Okada , Takaharu Ishizuka
发明人： Makoto Hataida , Takao Matsui , Daisuke Itoh , Seishi Okada , Takaharu Ishizuka
IPC分类号： G06F12/00
CPC分类号： G06F12/0833 , G06F12/0811 , G06F12/0817 , G06F2212/507
摘要： A cache-status maintaining unit stores address information of data stored in each entry of a cache memory, and maintains a status of each entry as any one of “strongly modified”, “weakly modified”, “shared”, and “Invalid”. A data-fetching-procedure selecting unit selects, upon receiving a data read request, at least one data fetching procedure based on the address information and the status. A read-data delivering unit selects latest data from among the data fetched, and delivers the latest data to a processor that issued the data read request. A cache-status updating unit updates, when registering the address information of the data, updates the status of the entry based on a type of the data read request.
摘要翻译：高速缓存状态维持单元存储存储在高速缓冲存储器的每个条目中的数据的地址信息，并将每个条目的状态保持为“强修改”，“弱修改”，“共享”和“无效”中的任何一个。数据获取过程选择单元在接收到数据读取请求时，基于地址信息和状态来选择至少一个数据获取过程。读取数据传送单元从获取的数据中选择最新数据，并将最新数据传送到发出数据读取请求的处理器。缓存状态更新单元在注册数据的地址信息时根据数据读取请求的类型来更新条目的状态。

34. 发明授权

US06615304B1 Processing unit in which access to system memory is controlled 失效
标题翻译：其中控制对系统存储器的访问的处理单元
公开(公告)号：US06615304B1
公开(公告)日：2003-09-02
申请号：US09603880
申请日：2000-06-26
申请人： Takaharu Ishizuka
发明人： Takaharu Ishizuka
IPC分类号： G06F948
CPC分类号： G06F9/30029 , G06F9/3834 , G06F9/3836 , G06F9/3857
摘要： Has an instruction issuing unit that monitors a change in a memory access sequencing model as well as monitoring a change in an interruption level. When the memory access sequencing model has been changed following a change in the interruption level, the instruction issuing unit restricts the issuing of memory access instructions corresponding to the interruption level after the change until when the execution of all the instructions issued before the change in the interruption level has been finished.
摘要翻译：具有指令发布单元，用于监视存储器访问排序模型的变化以及监视中断级别的变化。当存储器访问顺序模型在中断级别改变之后被改变时，指令发布单元限制在更改之后发出与中断级别相对应的存储器访问指令，直到执行在更改之前发生的所有指令中断级别已经完成。

35. 发明授权

US06292870B1 Information processing system in which memory devices and copies of tags are accessed in response to access requests issued from plurality of processing units 失效
标题翻译：信息处理系统，其中响应于从多个处理单元发出的访问请求来访问存储器件和标签副本
公开(公告)号：US06292870B1
公开(公告)日：2001-09-18
申请号：US09020678
申请日：1998-02-09
申请人： Takaharu Ishizuka , Takato Noda , Yasuhide Shibata , Takumi Takeno , Katsunori Takeshita , Fumitake Sugano
发明人： Takaharu Ishizuka , Takato Noda , Yasuhide Shibata , Takumi Takeno , Katsunori Takeshita , Fumitake Sugano
IPC分类号： G06F1208
CPC分类号： G06F12/0822
摘要： Processing units each having a first memory and a system controller are interconnected over a bus. The system controller includes access control units for controlling access to copies of tags of the first memories in the processing units and access to second memories to which a plurality of ways lead, and thus controls access to memories or memory access requested by the processing units. In the information processing system, a plurality of memory interfaces are included for enabling access to the second memories on an interleaving basis. Furthermore, the same numbers of copies of tags and memory access control units as the number of memory interfaces are included for enabling access to tags on the interleaving basis. Since access to the memories and tags on the interleaving basis is thus enabled, even if the number of processing units increases, competition for the memory access control units subsides and the efficiency of memory access improves.
摘要翻译：每个具有第一存储器和系统控制器的处理单元通过总线互连。系统控制器包括访问控制单元，用于控制对处理单元中的第一存储器的标签的拷贝的访问以及访问多个通路所引导的第二存储器，从而控制对由处理单元请求的存储器或存储器访问的访问。在信息处理系统中，包括多个存储器接口，用于在交织的基础上访问第二存储器。此外，包括与存储器接口的数量相同数量的标签和存储器访问控制单元的副本，以使得能够在交织的基础上访问标签。由于因此能够进行基于交织的存储器和标签的访问，即使处理单元的数量增加，对存储器访问控制单元的竞争减少，并且存储器访问的效率提高。

36. 发明申请

US20050125634A1 Processor and instruction control method 审中-公开
标题翻译：处理器和指令控制方法
公开(公告)号：US20050125634A1
公开(公告)日：2005-06-09
申请号：US11028338
申请日：2005-01-04
申请人： Takaharu Ishizuka
发明人： Takaharu Ishizuka
IPC分类号： G06F9/38 , G06F15/00
CPC分类号： G06F9/3861 , G06F9/30072 , G06F9/3842
摘要： The processor issues instructions including a branch instruction under a first identifier (ID=0) and speculatively executes the instructions by branch prediction. In the event of the detection of a branch error, the processor issues instructions in the correct direction under a second identifier (ID=1) subsequently to the erroneously issued instructions. After the completion of all the instructions prior to the branch error, the processor cancels the instructions erroneously issued by branch prediction to resume the issuance of instructions in the correct direction. The processor updates the identifiers (IDs) attached to the instructions after the occurrence of a branch error. This allows the processor to issue instructions in the correct direction without waiting for the completion of all the instructions prior to the branch instruction that caused the branch error, thus ensuring enhanced processing performance. Moreover, the processor needs only at least two identifiers to be attached to the instructions. This allows reduction in hardware volume.
摘要翻译：处理器发出包括在第一标识符（ID = 0）下的分支指令的指令，并通过分支预测推测地执行指令。在检测到分支错误的情况下，处理器在错误发出的指令之后的第二标识符（ID = 1）下以正确的方向发出指令。在分支错误之前完成所有指令之后，处理器取消由分支预测错误地发出的指令，以恢复正确方向的指令的发布。在发生分支错误之后，处理器更新附加到指令的标识符（ID）。这允许处理器以正确的方向发出指令，而不等待导致分支错误的分支指令之前的所有指令的完成，从而确保增强的处理性能。此外，处理器仅需要至少两个附加到指令的标识符。这允许减少硬件体积。

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