专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

31. 发明授权

US06262568B1 Common mode bias generator 有权
标题翻译：共模偏置发生器
公开(公告)号：US06262568B1
公开(公告)日：2001-07-17
申请号：US09734191
申请日：2000-12-12
申请人： Yoshihide Komatsu , Hironori Akamatsu , Takashi Hirata , Satoshi Takahashi , Yutaka Terada
发明人： Yoshihide Komatsu , Hironori Akamatsu , Takashi Hirata , Satoshi Takahashi , Yutaka Terada
IPC分类号： G05F304
CPC分类号： G05F3/205
摘要： An inventive potential generator generates a predetermined potential and includes first operational amplifier, current supply circuit and current sink circuit. A first reference potential is applied to the non-inverting input terminal of the first amplifier and a potential at the output node of the first amplifier is not only applied to the inverting input terminal of the first amplifier but also used as the output of the generator. The current supply circuit supplies a current to the output node of the first amplifier if the potential at the output node of the first amplifier is lower than a predefined level. And the current sink circuit drains a current from the output node of the first amplifier if the potential at the output node of the first amplifier is higher than the predefined level.
摘要翻译：本发明的潜在发生器产生预定电位并且包括第一运算放大器，电流供应电路和电流吸收电路。第一参考电位被施加到第一放大器的非反相输入端，并且第一放大器的输出节点处的电位不仅被施加到第一放大器的反相输入端，而且还用作发生器的输出。如果第一放大器的输出节点处的电位低于预定义电平，则电流供应电路向第一放大器的输出节点提供电流。并且如果第一放大器的输出节点处的电位高于预定义电平，则电流吸收电路从第一放大器的输出节点漏出电流。

32. 发明授权

US06163459A Semiconductor mounting system and semiconductor chip 失效
标题翻译：半导体安装系统和半导体芯片
公开(公告)号：US06163459A
公开(公告)日：2000-12-19
申请号：US122566
申请日：1998-07-24
申请人： Yutaka Terada , Hironori Akamatsu
发明人： Yutaka Terada , Hironori Akamatsu
IPC分类号： H01L25/10 , H05K1/14
CPC分类号： H05K1/14 , H01L25/105 , H01L2224/05554 , H01L2224/48091 , H01L2224/49175 , H01L2225/1029 , H01L2924/01055 , H01L2924/14 , H05K1/145 , H01L2924/00014
摘要： A semiconductor mounting system of the present invention includes a first semiconductor chip in which a first semiconductor integrated circuit is packaged and a second semiconductor chip in which a second semiconductor integrated circuit is packaged. The first semiconductor chip includes a plurality of first pins provided on a first surface and a plurality of second pins provided on a second surface. The second semiconductor chip includes a plurality of third pins provided on a third surface and a plurality of fourth pins provided on a fourth surface. The semiconductor mounting system further includes: a plurality of first lines for electrically connecting the first pins with the third pins; and a plurality of second lines for electrically connecting the second pins with the fourth pins. A length of the first lines is substantially equal to a length of the second lines.
摘要翻译：本发明的半导体安装系统包括封装有第一半导体集成电路的第一半导体芯片和封装有第二半导体集成电路的第二半导体芯片。第一半导体芯片包括设置在第一表面上的多个第一引脚和设置在第二表面上的多个第二引脚。第二半导体芯片包括设置在第三表面上的多个第三引脚和设置在第四表面上的多个第四引脚。半导体安装系统还包括：多个用于将第一引脚与第三引脚电连接的第一线; 以及用于将第二引脚与第四引脚电连接的多条第二线。第一行的长度基本上等于第二行的长度。

33. 发明授权

US6009024A Semiconductor memory 失效
标题翻译：半导体存储器
公开(公告)号：US6009024A
公开(公告)日：1999-12-28
申请号：US46880
申请日：1998-03-24
申请人： Takashi Hirata , Hiroyuki Yamauchi , Hironori Akamatsu , Keiichi Kusumoto , Toru Iwata , Satoshi Takahashi , Yutaka Terada
发明人： Takashi Hirata , Hiroyuki Yamauchi , Hironori Akamatsu , Keiichi Kusumoto , Toru Iwata , Satoshi Takahashi , Yutaka Terada
IPC分类号： G11C7/06 , G11C7/00
CPC分类号： G11C7/06
摘要： A semiconductor memory of the present invention includes: a plurality of memory cells; a pair of local bit lines connected to the plurality of memory cells; a local sense amplifier for amplifying a potential difference between the pair of local bit lines; a pair of global bit lines electrically connected to the pair of local bit lines through a switch; and a global sense amplifier for amplifying a potential difference between the pair of global bit lines, wherein the local sense amplifier includes a plurality of transistors, each of the plurality of transistors included in the local sense amplifier is a transistor of a first conductivity type, and the global sense amplifier includes a transistor of a second conductivity type different from the first conductivity type.
摘要翻译：本发明的半导体存储器包括：多个存储单元; 连接到所述多个存储器单元的一对局部位线; 本地读出放大器，用于放大一对局部位线之间的电位差; 一对全局位线通过开关电连接到该对局部位线; 以及用于放大所述一对全局位线之间的电位差的全局读出放大器，其中所述局部读出放大器包括多个晶体管，所述局部读出放大器中包括的所述多个晶体管中的每一个是第一导电类型的晶体管，并且全球感测放大器包括不同于第一导电类型的第二导电类型的晶体管。

34. 发明授权

US5999586A Time counting circuit and pulse signal generating method 失效
标题翻译：时间计数电路和脉冲信号产生方法
公开(公告)号：US5999586A
公开(公告)日：1999-12-07
申请号：US795907
申请日：1997-03-04
申请人： Yutaka Terada , Keiichi Kusumoto , Akira Matsuzawa
发明人： Yutaka Terada , Keiichi Kusumoto , Akira Matsuzawa
IPC分类号： G01D3/00
CPC分类号： G01D3/00
摘要： There is provided a small-size time counting circuit which measures time with high accuracy and low power consumption. Around a differential inverter ring composed of an odd number of differential inverters of identical structure connected in a ring configuration, signal transition is caused to circulate by oscillation. A first signal group is composed of normal output signals from the odd-numbered differential inverters and inverted output signals from the even-numbered differential inverters, which rise and fall sequentially at equal time intervals corresponding to delay times in the individual differential inverters. A second signal group is composed of inverted output signals from the odd-numbered differential inverters and normal output signals from the even-numbered differential inverters, which similarly rise and fall sequentially at equal time intervals. Accordingly, even when the rise time of an output signal from each of the differential inverters composing the differential inverter ring is different from the fall time thereof, the use of the first and second signal groups provides equal increments of time for time measurement.
摘要翻译：提供了一种小型时间计数电路，以高精度和低功耗测量时间。围绕由具有相同结构的奇数差分逆变器组成的差动逆变器环以环形结构连接，使信号转变通过振荡循环。第一信号组由来自奇数编号的差分逆变器的正常输出信号和来自偶数编号的差分逆变器的反相输出信号组成，其以与各个差分逆变器中的延迟时间相对应的等时间间隔顺序上升和下降。第二信号组由来自奇数编号的差分逆变器的反相输出信号和来自偶数编号差动逆变器的正常输出信号组成，其类似地以相等的时间间隔顺序地上升和下降。因此，即使来自构成差分逆变器环的各差分逆变器的输出信号的上升时间与其下降时间不同，所以使用第一和第二信号组提供相等的时间测量时间。

35. 发明授权

US5933384A Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：US5933384A
公开(公告)日：1999-08-03
申请号：US997558
申请日：1997-12-23
申请人： Yutaka Terada , Toru Iwata
发明人： Yutaka Terada , Toru Iwata
IPC分类号： G11C5/14 , H03K19/00 , G11C7/00
CPC分类号： H03K19/0016 , G11C5/147
摘要： In serially connected first and third inverters, the high-level-side source nodes are connected to a first pseudo-power supply line and the low-level-side source nodes are connected to a third pseudo-power supply line. In serially connected second and fourth inverters, the high-level-side source nodes are connected to a second pseudo-power supply line and the low-level-side source nodes are connected to a fourth pseudo-power supply line. The source nodes of transistors which are cut off in the operation mode, are disconnected from the power supply when first to fourth switch transistors are turned off according to an input signal, and these source nodes are short-circuited when either of fifth and sixth switch transistors is turned on.
摘要翻译：在串联连接的第一和第三反相器中，高电平侧源节点连接到第一伪电源线，而低电平侧源节点连接到第三伪电源线。在串联的第二和第四反相器中，高电平侧源极节点连接到第二伪电源线，而低电平侧源极节点连接到第四伪电源线。当第一至第四开关晶体管根据输入信号被切断时，在操作模式中切断的晶体管的源节点与电源断开，并且当第五和第六开关中的任一个切换时，这些源节点短路晶体管导通。

36. 发明授权

US5835552A Time counting circuit and counter circuit 失效
公开(公告)号：US5835552A
公开(公告)日：1998-11-10
申请号：US747129
申请日：1996-11-12
申请人： Keiichi Kusumoto , Shiro Dosho , Yutaka Terada , Akira Matsuzawa
发明人： Keiichi Kusumoto , Shiro Dosho , Yutaka Terada , Akira Matsuzawa
IPC分类号： G01R29/027 , H03D3/04 , H03K9/06 , H03M1/50 , G01B7/00
CPC分类号： G04F10/005 , G01R29/027 , H03D3/04 , H03K9/06
摘要： There is provided a time counting circuit for measuring a pulse spacing of a pulse signal with high accuracy and with low power consumption. An inverter ring composed of an odd number of inverters connected in a ring oscillates and one signal transition occurs after another as though seemingly circulating around the inverter ring. Holding circuits connected to respective output terminals of the inverters composing the inverter ring output, on the rising edge of a pulse signal to be measured, signals outputted from the inverters at the same time. The outputted signals are then converted by a signal converting circuit to numeric data. A counter circuit connected to the output terminal of one of the inverters composing the inverter ring counts the number of circulations of signal transition. A time-difference operating circuit corrects the numeric data outputted from the signal converting circuit based on the number of circulations of signal transition outputted from the counter circuit to provide time data, while calculating and outputting the pulse spacing of the pulse signal to be measured.

37. 发明授权

US4562281A Production of bisphenol derivatives 失效
标题翻译：生产双酚衍生物
公开(公告)号：US4562281A
公开(公告)日：1985-12-31
申请号：US561207
申请日：1983-12-14
申请人： Yukoh Takahashi , Yutaka Terada , Shinichi Yachigo , Tamaki Ishii
发明人： Yukoh Takahashi , Yutaka Terada , Shinichi Yachigo , Tamaki Ishii
IPC分类号： C07C67/08
CPC分类号： C07C67/08
摘要： Bisphenol derivatives of the formula (I), ##STR1## are produced by reacting a carboxylic acid, RCOOH (II), with a bisphenol of the formula (III), ##STR2## adding a halogenating agent in the presence of a dehydrohalogenating agent. The product bisphenol derivatives are useful as antioxidants.
摘要翻译：通过使羧酸RCOOH（II）与式（III）的双酚反应，在脱卤化氢剂的存在下加入卤化剂来制备式（I），（IMAGE）的双酚衍生物。产物双酚衍生物可用作抗氧化剂。

38. 发明授权

US4018739A Tar-urethane composition 失效
标题翻译：焦油 - 氨基甲酸酯组成
公开(公告)号：US4018739A
公开(公告)日：1977-04-19
申请号：US607962
申请日：1975-08-26
申请人： Masahiro Okamoto , Morio Kimura , Teruo Shibuya , Shinji Yamamoto , Shinichi Hasegawa , Yutaka Terada , Teruho Adachi
发明人： Masahiro Okamoto , Morio Kimura , Teruo Shibuya , Shinji Yamamoto , Shinichi Hasegawa , Yutaka Terada , Teruho Adachi
IPC分类号： C08G18/54 , C08G2/28 , C08G2/30
CPC分类号： C08G18/542 , Y10T428/16
摘要： A tar-urethane composition comprising (1) an isocyanate-reactive tar obtained by reacting a tar produced as a by-product in the phenol synthesis via hydroperoxides with a formaldehyde in the presence of a basic catalyst and in the presence or absence of at least one phenol compound and (2) a polyisocyanate, which is useful as coating agents, materials for pavement, floor linings, sealing materials and the like.
摘要翻译：焦油 - 聚氨酯组合物，其包含（1）异氰酸酯反应性焦油，其通过在碱性催化剂的存在下，通过氢过氧化物在苯酚合成中作为副产物生成的焦油与至少存在或不存在一种酚化合物和（2）多异氰酸酯，其可用作涂层剂，路面材料，地板衬里，密封材料等。

39. 发明授权

US08811078B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08811078B2
公开(公告)日：2014-08-19
申请号：US13493671
申请日：2012-06-11
申请人： Yutaka Terada , Masakazu Kurata
发明人： Yutaka Terada , Masakazu Kurata
IPC分类号： G11C16/10 , H01L27/112 , H01L27/115 , G11C16/04 , G11C16/06
CPC分类号： H01L27/112 , G11C16/0408 , G11C16/06 , H01L27/115 , H01L27/11519
摘要： In a semiconductor memory device in which each memory cell is constituted by one transistor, in a memory cell pattern, two adjacent bits form one diffusion pattern, two adjacent transistors share a source region, and two drain regions are separated from each other. A plurality of arrays in each of which at least a column of the diffusion patterns is disposed include bit lines, and the bit lines of the first array are independent of the bit lines of the second array. In an interface between the arrays, ends at one side of the bit lines of each of the arrays are located on an associated one of two drain regions which are separated from each other with the source region which is shared on one diffusion pattern sandwiched therebetween. This configuration can provide a sufficient bit-line separation width, and reduce the area.
摘要翻译：在其中每个存储单元由一个晶体管构成的半导体存储器件中，在存储单元图形中，两个相邻位形成一个扩散图案，两个相邻的晶体管共享源极区域，并且两个漏极区域彼此分离。其中布置有至少一列扩散图案的多个阵列包括位线，并且第一阵列的位线与第二阵列的位线无关。在阵列之间的接口中，每个阵列的位线的一侧的端部位于两个漏极区域中的相关联的一个上，这两个漏极区域彼此分离，其中源区域在夹在其间的一个扩散图案上共享。这种配置可以提供足够的位线分隔宽度，并减少面积。

40. 发明申请

US20090180306A1 SEMICONDUCTOR MEMORY DEVICE 审中-公开
标题翻译：半导体存储器件
公开(公告)号：US20090180306A1
公开(公告)日：2009-07-16
申请号：US12243299
申请日：2008-10-01
申请人： Yutaka Terada , Yasuhiro Agata , Wataru Abe , Masakazu Kurata , Kenji Misumi
发明人： Yutaka Terada , Yasuhiro Agata , Wataru Abe , Masakazu Kurata , Kenji Misumi
IPC分类号： G11C5/06
CPC分类号： G11C5/06 , G11C5/063 , G11C7/18 , H01L27/0207 , H01L27/112 , H01L27/11253
摘要： A circuit on an end column of a divided memory array is formed by a block selection transistor having the same shape as that of a memory cell transistor. As the pattern of the connecting section between the main bit line and the sub-bit line is made in the same shape as that of the memory cell, it is possible to realize a pattern uniformity and to eliminate the need for using memory array dummy patterns.
摘要翻译：分割存储器阵列的末端列上的电路由具有与存储单元晶体管相同形状的块选择晶体管形成。由于主位线和子位线之间的连接部分的图形与存储单元的形状相同，所以可以实现图案均匀性，并且不需要使用存储器阵列虚拟图案。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式