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31. 发明申请

US20070001975A1 Integrated circuit device and electronic instrument 审中-公开
标题翻译：集成电路器件和电子仪器
公开(公告)号：US20070001975A1
公开(公告)日：2007-01-04
申请号：US11270747
申请日：2005-11-10
申请人： Takashi Kumagai , Hisanobu Ishiyama , Kazuhiro Maekawa , Satoru Ito , Takashi Fujise , Junichi Karasawa , Satoru Kodaira
发明人： Takashi Kumagai , Hisanobu Ishiyama , Kazuhiro Maekawa , Satoru Ito , Takashi Fujise , Junichi Karasawa , Satoru Kodaira
IPC分类号： G09G3/36
CPC分类号： G09G3/20 , G09G2300/0426 , H01L27/12
摘要： An integrated circuit device, including first to Nth circuit blocks CB1 to CBN disposed along a first direction D1, when the first direction D1 is a direction from a first side of the integrated circuit device toward a third side which is opposite to the first side, the first side being a short side, and when a second direction D2 is a direction from a second side of the integrated circuit device toward a fourth side which is opposite to the second side, the second side being a long side. The circuit blocks CB1 to CBN include a scan driver block SB, a power supply circuit block PB, a data driver block DB, and a memory block MB. The scan driver block SB and the power supply circuit block PB are disposed adjacent to each other along the direction D1; and the data driver block DB and the memory block MB are disposed adjacent to each other along the direction D1.
摘要翻译：一种集成电路装置，包括沿着第一方向D 1布置的第一至第N电路块CB 1至CBN，当第一方向D1是从集成电路装置的第一侧向与第三方向相反的第三侧的方向时第一侧，第一侧为短边，当第二方向D 2为从集成电路器件的第二侧向与第二侧相反的第四侧的方向时，第二侧为长边。电路块CB 1至CBN包括扫描驱动器块SB，电源电路块PB，数据驱动器块DB和存储器块MB。扫描驱动器块SB和电源电路块PB沿着方向D1彼此相邻配置; 并且数据驱动块DB和存储块MB沿着方向D1彼此相邻地布置。

32. 发明授权

US07782694B2 Integrated circuit device and electronic instrument 有权
标题翻译：集成电路器件和电子仪器
公开(公告)号：US07782694B2
公开(公告)日：2010-08-24
申请号：US11477716
申请日：2006-06-30
申请人： Satoru Kodaira , Noboru Itomi , Shuji Kawaguchi , Takashi Kumagai , Junichi Karasawa , Satoru Ito , Masahiko Moriguchi , Kazuhiro Maekawa
发明人： Satoru Kodaira , Noboru Itomi , Shuji Kawaguchi , Takashi Kumagai , Junichi Karasawa , Satoru Ito , Masahiko Moriguchi , Kazuhiro Maekawa
IPC分类号： G11C7/00
CPC分类号： G09G3/20 , G09G2310/027 , G09G2360/18
摘要： An integrated circuit device includes a display memory and a data read control circuit. The data read control circuit controls data reading so that data of pixels corresponding to a plurality of signal lines is read out by N-time reading in one horizontal scan period of a display panel (N is an integer larger than 1). The display memory includes a plurality of sense amplifier cells respectively connected with a plurality of bitlines. L sense amplifier cells (L is an integer larger than 1) respectively connected with the bitlines of L memory cells adjacent in a first direction (wordline direction) in which wordlines extend are disposed along a second direction (bitline direction) in which the bitlines extend.
摘要翻译：集成电路装置包括显示存储器和数据读取控制电路。数据读取控制电路控制数据读取，使得通过在显示面板的一个水平扫描周期（N是大于1的整数）中的N次读取来读出与多条信号线相对应的像素的数据。显示存储器包括分别与多个位线连接的多个读出放大器单元。分别与字线延伸的第一方向（字线方向）相邻的L个存储单元的位线分别连接的L个读出放大器单元（L是大于1的整数）沿着位线延伸的第二个方向（位线方向）。

33. 发明授权

US07613066B2 Integrated circuit device and electronic instrument 有权
标题翻译：集成电路器件和电子仪器
公开(公告)号：US07613066B2
公开(公告)日：2009-11-03
申请号：US11477719
申请日：2006-06-30
申请人： Satoru Kodaira , Noboru Itomi , Shuji Kawaguchi , Takashi Kumagai , Junichi Karasawa , Satoru Ito , Masahiko Moriguchi , Kazuhiro Maekawa
发明人： Satoru Kodaira , Noboru Itomi , Shuji Kawaguchi , Takashi Kumagai , Junichi Karasawa , Satoru Ito , Masahiko Moriguchi , Kazuhiro Maekawa
IPC分类号： G11C8/00
CPC分类号： G09G3/3685 , G09G2300/0426 , G09G2310/0218 , G09G2310/027 , G09G2360/12
摘要： In an integrated circuit device, a data line driver block which drives data lines of a display panel based on data supplied from a RAM block from which data is read N times (N is an integer larger than one) in one horizontal scan period 1H of the display panel includes first to N-th divided data line driver blocks disposed along a first direction in which bitlines extend. When data supplied from the RAM block is M bits (M is an integer larger than 1) and grayscale of a pixel corresponding to the data line is G bits, each of the first to N-th divided data line driver blocks includes (M/G) (multiple of three) data line driver cells which drive (M/G) data lines. (M/3G) R data line driver cells are provided in a first subdivided driver, (M/3G) G data line driver cells are provided in a second subdivided driver, and (M/3G) B data line driver cells are provided in a third subdivided driver.
摘要翻译：在集成电路装置中，数据线驱动器模块，其基于从RAM数据块提供的数据驱动显示面板的数据线，数据被读取N次（N为大于1的整数）N 显示面板包括沿位线延伸的第一方向设置的第一至第N分割数据线驱动器块。当从RAM块提供的数据是M位（M是大于1的整数）并且与数据线相对应的像素的灰度级是G位时，第一至第N划分数据线驱动器块中的每一个包括（M / G）（三个的三个）数据线驱动器单元驱动（M / G）数据线。（M / 3G）R数据线驱动器单元设置在第一细分驱动器中，（M / 3G）G数据线驱动器单元设置在第二细分驱动器中，并且（M / 3G）B数据线驱动器单元设置在第三个细分驱动程序。

34. 发明申请

US20070013707A1 Integrated circuit device and electronic instrument 有权
标题翻译：集成电路器件和电子仪器
公开(公告)号：US20070013707A1
公开(公告)日：2007-01-18
申请号：US11477719
申请日：2006-06-30
申请人： Satoru Kodaira , Noboru Itomi , Shuji Kawaguchi , Takashi Kumagai , Junichi Karasawa , Satoru Ito , Masahiko Moriguchi , Kazuhiro Maekawa
发明人： Satoru Kodaira , Noboru Itomi , Shuji Kawaguchi , Takashi Kumagai , Junichi Karasawa , Satoru Ito , Masahiko Moriguchi , Kazuhiro Maekawa
IPC分类号： G09G5/36
CPC分类号： G09G3/3685 , G09G2300/0426 , G09G2310/0218 , G09G2310/027 , G09G2360/12
摘要： In an integrated circuit device, a data line driver block which drives data lines of a display panel based on data supplied from a RAM block from which data is read N times (N is an integer larger than one) in one horizontal scan period 1H of the display panel includes first to N-th divided data line driver blocks disposed along a first direction in which bitlines extend. When data supplied from the RAM block is M bits (M is an integer larger than 1) and grayscale of a pixel corresponding to the data line is G bits, each of the first to N-th divided data line driver blocks includes (M/G) (multiple of three) data line driver cells which drive (M/G) data lines. (M/3G) R data line driver cells are provided in a first subdivided driver, (M/3G) G data line driver cells are provided in a second subdivided driver, and (M/3G) B data line driver cells are provided in a third subdivided driver.
摘要翻译：在集成电路装置中，数据线驱动器模块，其基于从RAM数据块提供的数据驱动显示面板的数据线，数据被读取N次（N为大于1的整数）N 显示面板包括沿位线延伸的第一方向设置的第一至第N分割数据线驱动器块。当从RAM块提供的数据是M位（M是大于1的整数）并且与数据线相对应的像素的灰度级是G位时，第一至第N划分数据线驱动器块中的每一个包括（M / G）（三个的三个）数据线驱动器单元驱动（M / G）数据线。（M / 3G）R数据线驱动器单元设置在第一细分驱动器中，（M / 3G）G数据线驱动器单元设置在第二细分驱动器中，并且（M / 3G）B数据线驱动单元第三个细分驱动程序。

35. 发明申请

US20070013706A1 Integrated circuit device and electronic instrument 审中-公开
标题翻译：集成电路器件和电子仪器
公开(公告)号：US20070013706A1
公开(公告)日：2007-01-18
申请号：US11477647
申请日：2006-06-30
申请人： Satoru Kodaira , Noboru Itomi , Shuji Kawaguchi , Takashi Kumagai , Junichi Karasawa , Satoru Ito , Masahiko Moriguchi , Kazuhiro Maekawa
发明人： Satoru Kodaira , Noboru Itomi , Shuji Kawaguchi , Takashi Kumagai , Junichi Karasawa , Satoru Ito , Masahiko Moriguchi , Kazuhiro Maekawa
IPC分类号： G09G5/36 , G06F12/02
CPC分类号： G09G3/3685 , G09G2300/0426 , G09G2310/0218 , G09G2310/027 , G09G2310/0275 , G09G2360/12
摘要： Each of RAM blocks provided in a display memory and disposed along a first direction in which bitlines extend includes a sense amplifier circuit which outputs M-bit data upon one wordline selection (M is an integer larger than 1). At least M memory cells are arranged in each of the RAM blocks along a second direction in which wordlines extend. M sense amplifier cells to which M-bit data read from the M memory cells is input are provided in the sense amplifier circuit. L sense amplifier cells of the M sense amplifier cells are disposed at a position corresponding to L memory cells adjacent in the second direction (L is an integer which satisfies 2≦L
摘要翻译：提供在显示存储器中并沿着位线延伸的第一方向布置的每个RAM块包括读取放大器电路，其在一个字线选择（M是大于1的整数）上输出M位数据。至少M个存储单元沿着字线延伸的第二方向布置在每个RAM块中。在读出放大器电路中设置有从M个存储单元读取M位数据的M个读出放大器单元。 M个读出放大器单元的L个读出放大器单元配置在与第二方向相邻的L个存储单元对应的位置（L为满足2 <= L

36. 发明申请

US20070013687A1 Integrated circuit device and electronic instrument 有权
标题翻译：集成电路器件和电子仪器
公开(公告)号：US20070013687A1
公开(公告)日：2007-01-18
申请号：US11477716
申请日：2006-06-30
申请人： Satoru Kodaira , Noboru Itomi , Shuji Kawaguchi , Takashi Kumagai , Junichi Karasawa , Satoru Ito , Masahiko Moriguchi , Kazuhiro Maekawa
发明人： Satoru Kodaira , Noboru Itomi , Shuji Kawaguchi , Takashi Kumagai , Junichi Karasawa , Satoru Ito , Masahiko Moriguchi , Kazuhiro Maekawa
IPC分类号： G09G5/00
CPC分类号： G09G3/20 , G09G2310/027 , G09G2360/18
摘要： An integrated circuit device includes a display memory and a data read control circuit. The data read control circuit controls data reading so that data of pixels corresponding to a plurality of signal lines is read out by N-time reading in one horizontal scan period of a display panel (N is an integer larger than 1). The display memory includes a plurality of sense amplifier cells respectively connected with a plurality of bitlines. L sense amplifier cells (L is an integer larger than 1) respectively connected with the bitlines of L memory cells adjacent in a first direction (wordline direction) in which wordlines extend are disposed along a second direction (bitline direction) in which the bitlines extend.
摘要翻译：集成电路装置包括显示存储器和数据读取控制电路。数据读取控制电路控制数据读取，使得通过在显示面板的一个水平扫描周期（N是大于1的整数）中的N次读取来读出与多条信号线相对应的像素的数据。显示存储器包括分别与多个位线连接的多个读出放大器单元。分别与字线延伸的第一方向（字线方向）相邻的L个存储单元的位线分别连接的L个读出放大器单元（L是大于1的整数）沿着位线延伸的第二个方向（位线方向）。

37. 发明申请

US20070013685A1 Integrated circuit device and electronic instrument 有权
标题翻译：集成电路器件和电子仪器
公开(公告)号：US20070013685A1
公开(公告)日：2007-01-18
申请号：US11270694
申请日：2005-11-10
申请人： Satoru Kodaira , Noboru Itomi , Shuji Kawaguchi , Takashi Kumagai , Hisanobu Ishiyama , Kazuhiro Maekawa
发明人： Satoru Kodaira , Noboru Itomi , Shuji Kawaguchi , Takashi Kumagai , Hisanobu Ishiyama , Kazuhiro Maekawa
IPC分类号： G09G5/00
CPC分类号： G09G3/2007 , G09G2310/027 , G09G2360/18
摘要： An integrated circuit device having a display memory, wherein a plurality of first power supply interconnects VSSL for supplying a first power supply voltage VSS to memory cells MC are formed in a metal interconnect layer in which a plurality of wordlines WL are formed; and wherein a plurality of second power supply interconnects VDDL for supplying a second power supply voltage VDD to the memory cells are formed in another metal interconnect layer in which a plurality of bitlines BL are formed, the second power supply voltage VDD being higher than the first power supply voltage VSS. A plurality of bitline protection interconnects SHD are formed in a layer above the bitlines BL, and each of the bitline protection interconnects SHD at least partially covers one of the bitlines BL in a plan view. A third power supply interconnect GL for supplying a third power supply voltage to circuits other than the display memory are formed in a layer above the bitline protection interconnects SHD, the third power supply voltage being higher than the second power supply voltage VDD.
摘要翻译：一种具有显示存储器的集成电路器件，其中在形成有多个字线WL的金属互连层中形成有用于向存储单元MC提供第一电源电压VSS的多个第一电源互连VSSL; 并且其中，在形成有多个位线BL的另一个金属互连层中形成有用于将第二电源电压VDD提供给存储单元的多个第二电源互连VDDL，第二电源电压VDD高于第一电源电压VDD 电源电压VSS。多个位线保护互连SHD形成在位线BL上方的层中，并且每个位线保护互连SHD在平面图中至少部分地覆盖位线BL之一。用于将第三电源电压提供给除了显示存储器之外的电路的第三电源互连GL形成在位线保护互连SHD上方的层中，第三电源电压高于第二电源电压VDD。

38. 发明申请

US20070013074A1 Integrated circuit device and electronic instrument 有权
标题翻译：集成电路器件和电子仪器
公开(公告)号：US20070013074A1
公开(公告)日：2007-01-18
申请号：US11270586
申请日：2005-11-10
申请人： Satoru Kodaira , Noboru Itomi , Shuji Kawaguchi , Takashi Kumagai , Hisanobu Ishiyama , Kazuhiro Maekawa
发明人： Satoru Kodaira , Noboru Itomi , Shuji Kawaguchi , Takashi Kumagai , Hisanobu Ishiyama , Kazuhiro Maekawa
IPC分类号： H01L23/52
CPC分类号： H01L23/552 , G11C5/063 , H01L24/49 , H01L2224/49175 , H01L2924/00014 , H01L2924/01019 , H01L2924/01037 , H01L2924/01066 , H01L2924/14 , H01L2924/19041 , H01L2924/3025 , H01L2224/45099
摘要： An integrated circuit device having a display memory, wherein a plurality of first power supply interconnects for supplying a first power supply voltage to a plurality of memory cells are provided in a metal interconnect layer in which a plurality of bitlines are formed; wherein a second power supply interconnect for supplying a second power supply voltage to the memory cells is provided in a metal interconnect layer in which a plurality of wordlines are formed, the second power supply voltage being higher than the first power supply voltage; wherein a plurality of bitline protection interconnects are formed in a layer above the bitlines, each of the bitline protection interconnects at least partially covering one of the bitlines in a plan view; and wherein a third power supply interconnect for supplying a third power supply voltage to circuits of the integrated circuit device other than the display memory is provided in a layer above the bitline protection interconnects, the third power supply voltage being higher than the second power supply voltage.
摘要翻译：一种具有显示存储器的集成电路器件，其中在形成多个位线的金属互连层中提供用于向多个存储单元提供第一电源电压的多个第一电源互连件; 其中在形成有多个字线的金属互连层中提供用于向所述存储单元提供第二电源电压的第二电源互连，所述第二电源电压高于所述第一电源电压; 其中多个位线保护互连形成在所述位线上方的层中，所述位线保护互连中的每一个在平面图中至少部分地覆盖所述位线之一; 并且其中，用于将第三电源电压提供给除了所述显示存储器之外的所述集成电路装置的电路的第三电源互连设置在所述位线保护互连线上方的层中，所述第三电源电压高于所述第二电源电压。

39. 发明授权

US07492659B2 Integrated circuit device and electronic instrument 有权
标题翻译：集成电路器件和电子仪器
公开(公告)号：US07492659B2
公开(公告)日：2009-02-17
申请号：US11270586
申请日：2005-11-10
申请人： Satoru Kodaira , Noboru Itomi , Shuji Kawaguchi , Takashi Kumagai , Hisanobu Ishiyama , Kazuhiro Maekawa
发明人： Satoru Kodaira , Noboru Itomi , Shuji Kawaguchi , Takashi Kumagai , Hisanobu Ishiyama , Kazuhiro Maekawa
IPC分类号： G11C5/14
CPC分类号： H01L23/552 , G11C5/063 , H01L24/49 , H01L2224/49175 , H01L2924/00014 , H01L2924/01019 , H01L2924/01037 , H01L2924/01066 , H01L2924/14 , H01L2924/19041 , H01L2924/3025 , H01L2224/45099
摘要： An integrated circuit device having a display memory, wherein a plurality of first power supply interconnects for supplying a first power supply voltage to a plurality of memory cells are provided in a metal interconnect layer in which a plurality of bitlines are formed; wherein a second power supply interconnect for supplying a second power supply voltage to the memory cells is provided in a metal interconnect layer in which a plurality of wordlines are formed, the second power supply voltage being higher than the first power supply voltage; wherein a plurality of bitline protection interconnects are formed in a layer above the bitlines, each of the bitline protection interconnects at least partially covering one of the bitlines in a plan view; and wherein a third power supply interconnect for supplying a third power supply voltage to circuits of the integrated circuit device other than the display memory is provided in a layer above the bitline protection interconnects, the third power supply voltage being higher than the second power supply voltage.
摘要翻译：一种具有显示存储器的集成电路器件，其中在形成多个位线的金属互连层中提供用于向多个存储单元提供第一电源电压的多个第一电源互连件; 其中在形成有多个字线的金属互连层中提供用于向所述存储单元提供第二电源电压的第二电源互连，所述第二电源电压高于所述第一电源电压; 其中多个位线保护互连形成在所述位线上方的层中，所述位线保护互连中的每一个在平面图中至少部分地覆盖所述位线之一; 并且其中，用于将第三电源电压提供给除了所述显示存储器之外的所述集成电路装置的电路的第三电源互连设置在所述位线保护互连线上方的层中，所述第三电源电压高于所述第二电源电压。

40. 发明授权

US07495988B2 Integrated circuit device and electronic instrument 有权
标题翻译：集成电路器件和电子仪器
公开(公告)号：US07495988B2
公开(公告)日：2009-02-24
申请号：US11270694
申请日：2005-11-10
申请人： Satoru Kodaira , Noboru Itomi , Shuji Kawaguchi , Takashi Kumagai , Hisanobu Ishiyama , Kazuhiro Maekawa
发明人： Satoru Kodaira , Noboru Itomi , Shuji Kawaguchi , Takashi Kumagai , Hisanobu Ishiyama , Kazuhiro Maekawa
IPC分类号： G11C5/14
CPC分类号： G09G3/2007 , G09G2310/027 , G09G2360/18
摘要： An integrated circuit device having a display memory, wherein a plurality of first power supply interconnects VSSL for supplying a first power supply voltage VSS to memory cells MC are formed in a metal interconnect layer in which a plurality of wordlines WL are formed; and wherein a plurality of second power supply interconnects VDDL for supplying a second power supply voltage VDD to the memory cells are formed in another metal interconnect layer in which a plurality of bitlines BL are formed, the second power supply voltage VDD being higher than the first power supply voltage VSS. A plurality of bitline protection interconnects SHD are formed in a layer above the bitlines BL, and each of the bitline protection interconnects SHD at least partially covers one of the bitlines BL in a plan view. A third power supply interconnect GL for supplying a third power supply voltage to circuits other than the display memory are formed in a layer above the bitline protection interconnects SHD, the third power supply voltage being higher than the second power supply voltage VDD.
摘要翻译：一种具有显示存储器的集成电路器件，其中在形成有多个字线WL的金属互连层中形成有用于向存储单元MC提供第一电源电压VSS的多个第一电源互连VSSL; 并且其中，在形成有多个位线BL的另一个金属互连层中形成有用于将第二电源电压VDD提供给存储单元的多个第二电源互连VDDL，第二电源电压VDD高于第一电源电压VDD 电源电压VSS。多个位线保护互连SHD形成在位线BL上方的层中，并且每个位线保护互连SHD在平面图中至少部分地覆盖位线BL之一。用于将第三电源电压提供给除了显示存储器之外的电路的第三电源互连GL形成在位线保护互连SHD上方的层中，第三电源电压高于第二电源电压VDD。

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