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    • 37. 发明授权
    • Power supply circuit for generating an internal power supply potential
based on an external potential
    • 用于基于外部电位产生内部电源电位的电源电路
    • US5587648A
    • 1996-12-24
    • US378217
    • 1995-01-25
    • Shinichi JinboShigeru Mori
    • Shinichi JinboShigeru Mori
    • G11C11/407G11C5/14G11C11/409G05F1/613
    • G11C5/147G11C5/14
    • An internal power supply circuit of the present invention includes a primary internal power supply potential supplying circuit, two auxiliary internal power supply potential supplying circuits, and a P channel MOS transistor. The internal power supply potential supplying circuit always supplies an internal power supply potential to a first output node based on an external power supply potential. One auxiliary internal power supply potential supplying circuit is activated in response to a control signal, and, when activated, supplies the internal power supply potential to the first output node. The other auxiliary internal power supply potential supplying circuit is activated in response to another control signal, and, when activated, supplies the internal power supply potential to a second output node. The P channel MOS transistor is connected between the first output node and the second output node. The P channel MOS transistor has a gate electrode receiving the control signal.
    • 本发明的内部电源电路包括主内部电源电位供给电路,两个辅助内部电源电位供给电路和P沟道MOS晶体管。 内部电源电位供应电路总是基于外部电源电位向第一输出节点提供内部电源电位。 响应于控制信号激活一个辅助内部电源电位供应电路,并且当被激活时,将内部电源电位提供给第一输出节点。 另一个辅助内部电源电位供应电路响应于另一个控制信号被激活,并且当被激活时,将内部电源电位提供给第二输出节点。 P沟道MOS晶体管连接在第一输出节点和第二输出节点之间。 P沟道MOS晶体管具有接收控制信号的栅电极。
    • 40. 发明授权
    • Semiconductor device having an improved immunity to a short-circuit at a
power supply line
    • 具有对电源线短路的抗干扰性的半导体装置
    • US5519650A
    • 1996-05-21
    • US301752
    • 1994-09-07
    • Tooru IchimuraKazuhiro SakemiShigeru MoriMikio Sakurai
    • Tooru IchimuraKazuhiro SakemiShigeru MoriMikio Sakurai
    • G11C11/41G11C29/50H01L21/3205H01L21/82H01L23/52H01L23/525G11C5/06
    • G11C29/50H01L23/5258H01L2924/0002
    • A semiconductor memory device includes a memory cell array (1) having a plurality of memory cells arranged in rows and columns, a plurality of column select lines (3) extending over the memory cell array and coupled to received column select signals generated by a column decoder (100), a plurality of power supply lines (4) provided in parallel with the column select lines to transfer a power supply voltage from a main power supply line (130), and a plurality of ground lines (5) provided in parallel with the column select lines to transfer a ground voltage from a main ground line. A plurality of fuse elements (6) are provided for each of the column select lines. When a short-circuit is found between a column select line and power supply line or a ground line, a fuse element corresponding to the short-circuited column select line is blown off and the short-circuited column select line is isolated from the column decoder. By repairing the short-circuited column select line with a redundant column select line (60), the memory device operates correctly without an adverse effect of the short-circuit.
    • 半导体存储器件包括具有以行和列排列的多个存储器单元的存储单元阵列(1),在存储单元阵列上延伸的多个列选择线(3),并与由列产生的接收列选择信号耦合 解码器(100),与列选择线并联设置的多个电源线(4),用于传送来自主电源线(130)的电源电压和并联设置的多个接地线(5) 列选择线从主地线传输接地电压。 为每个列选择线提供多个熔丝元件(6)。 当在列选择线和电源线或接地线之间发现短路时,与短路列选择线相对应的熔丝元件被断开,并且短路列选择线与列解码器隔离 。 通过修复具有冗余列选择线(60)的短路列选择线,存储器件正常工作而没有短路的不利影响。