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    • 31. 发明授权
    • Power supply supervisor having a line voltage detector
    • 电源监控器具有线路电压检测器
    • US06418002B1
    • 2002-07-09
    • US09607029
    • 2000-06-29
    • Ta-yung YangJenn-yu G. LinRui-hong Lu
    • Ta-yung YangJenn-yu G. LinRui-hong Lu
    • H02H300
    • G06F1/28G06F1/30H02H3/20H02H3/207H02H3/247H02H7/1227
    • A power supply supervisor having a line voltage detector is used to monitor a power supply. A peak detector detects the line voltage by measuring the PWM switching signal in the secondary of the transformer. A logic circuit couples to the peak detector and the under-voltage detector, etc. to generate a power good (PG) signal when the power supply outputs meet the specifications. The logic circuit outputs a FAIL signal to turn off the power supply when an abnormal situation, such as over-voltage, occurs. Furthermore, when AC power is lost or turned off, the logic circuit detects a low line voltage and generates a power-down-warning PG signal before the output voltages are disabled. When an abnormal situation occurs before the low line voltage is detected, the logic circuit latches the power supply in a power off state. If the abnormal situation occurs after the low line voltage is detected, the logic circuit turns off the power outputs, but disables the latch function. In the meantime, a time delay circuit is applied to postpone the power off status, in which the time delay limits the duty cycle of power outputs and protects the power supply from over-stress damage.
    • 具有线路电压检测器的电源管理器用于监视电源。 峰值检测器通过测量变压器次级中的PWM开关信号来检测线路电压。 当电源输出满足规格时,逻辑电路耦合到峰值检测器和欠压检测器等,以产生电源良好(PG)信号。 当发生异常情况(如过电压)时,逻辑电路输出FAIL信号以关闭电源。 此外,当交流电源丢失或关闭时,逻辑电路检测到低电压电压,并且在禁用输出电压之前产生掉电警告PG信号。 当在检测到低线电压之前发生异常情况时,逻辑电路将电源锁定在断电状态。 如果在检测到低电压电压后发生异常情况,则逻辑电路关闭电源输出,但禁用锁存功能。 同时延时电路用于推迟断电状态,延时限制电源输出的占空比,保护电源免受过度应力损坏。
    • 32. 发明授权
    • Low distortion video analog-to-digital converter
    • 低失真视频模数转换器
    • US06353405B1
    • 2002-03-05
    • US09607095
    • 2000-06-29
    • Ta-yung YangJenn-yu G. Lin
    • Ta-yung YangJenn-yu G. Lin
    • H03M112
    • H03M1/1028H03M1/12
    • An analog to digital video converter is made of a differential correlated double sampling (DCDS) module, a DC bias circuit, an adjustment module and an analog-to-digital converter. The DCDS module samples a red, a green, and a blue analog signal respectively with a delay time, and then selects one of the sampled signals for outputting. The DC bias circuit is connected to the DCDS module for performing an analog addition to the output signal of the DCDS module. The adjustment module converts the digital adjustment data to an analog adjustable reference voltage. The analog-to-digital converter is connected to the output of the DC bias circuit and the adjustment module. By referring the adjustable reference voltage, the analog-to-digital converter converts the analog input signal to a digital output signal. Therefore, the analog input signal is equivalently adjusted by scaling the adjustable reference voltage.
    • 模数转换器由差分相关双采样(DCDS)模块,直流偏置电路,调节模块和模数转换器组成。 DCDS模块以延迟时间分别采样一个红色,绿色和蓝色模拟信号,然后选择一个采样信号进行输出。 DC偏置电路连接到DCDS模块,用于对DCDS模块的输出信号进行模拟加法。 调整模块将数字调节数据转换为模拟可调参考电压。 模数转换器连接到直流偏置电路和调节模块的输出端。 通过参考可调参考电压,模数转换器将模拟输入信号转换为数字输出信号。 因此,通过缩放可调参考电压来等效地调整模拟输入信号。
    • 34. 发明授权
    • Electrostatic discharge protection semiconductor structure
    • 静电放电保护半导体结构
    • US07615826B2
    • 2009-11-10
    • US11427773
    • 2006-06-29
    • Chih-Feng HuangTuo-Hsin ChienJenn-Yu G. LinTa-yung Yang
    • Chih-Feng HuangTuo-Hsin ChienJenn-Yu G. LinTa-yung Yang
    • H01L23/62
    • H01L27/0259
    • An electrostatic discharge (ESD) protection device with adjustable single-trigger or multi-trigger voltage is provided. The semiconductor structure has multi-stage protection semiconductor circuit function and adjustable discharge capacity. The single-trigger or multi-trigger semiconductor structure may be fabricated by using the conventional semiconductor process, and can be applied to IC semiconductor design and to effectively protect the important semiconductor devices and to prevent the semiconductor devices from ESD damage. In particular, the present invention can meet the requirements of high power semiconductor device and has better protection function compared to conventional ESD protection circuit. In the present invention, a plurality of N-wells or P-wells connected in parallel are used to adjust the discharge capacity of various wells in the P-substrate so as to improve the ESD protection capability and meet different power standards.
    • 提供具有可调单触发或多触发电压的静电放电(ESD)保护装置。 半导体结构具有多级保护半导体电路功能和可调放电容量。 单触发或多触发半导体结构可以通过使用传统的半导体工艺制造,并且可以应用于IC半导体设计并且有效地保护重要的半导体器件并且防止半导体器件受到ESD损坏。 特别地,本发明可以满足大功率半导体器件的要求,与传统的ESD保护电路相比具有更好的保护功能。 在本发明中,使用并联连接的多个N阱或P阱来调整P基板中的各个阱的放电容量,以提高ESD保护能力并满足不同的功率标准。
    • 35. 发明授权
    • CMOS compatible process with different-voltage devices
    • CMOS兼容过程与不同电压器件
    • US07205201B2
    • 2007-04-17
    • US10914943
    • 2004-08-09
    • Chih-Feng HuangTa-yung YangJenn-yu G. LinTuo-Hsin Chien
    • Chih-Feng HuangTa-yung YangJenn-yu G. LinTuo-Hsin Chien
    • H01L21/8234
    • H01L21/823814H01L21/823857H01L21/823892
    • A method of manufacturing different-voltage devices mainly comprises forming at least one high-voltage well in high-voltage device regions, at least one N-well in low-voltage device regions, at least one P-well in low-voltage device regions, source/drain wells in high-voltage device regions, and isolation wells in isolation regions in a p-type substrate. The breakdown voltage is adjusted by modulating the ion doping profile. Furthermore, parameters of implanting conductive ions are adjusted for implanting conductive ions into both high-voltage device regions and low-voltage device regions. The isolation wells formed in isolation regions between devices are for separating device formed over high-voltage device regions and device formed over low-voltage device regions. The thickness of a HV gate oxide layer is thicker than the thickness of an LV gate oxide layer for modulating threshold voltages of high-voltage devices and low-voltage devices.
    • 一种制造不同电压装置的方法主要包括在高电压装置区域中形成至少一个高电压阱,在低电压装置区域中形成至少一个N阱,在低电压装置区域中形成至少一个P阱 ,高压器件区域中的源/漏极阱以及p型衬底中的隔离区中的隔离阱。 通过调制离子掺杂分布来调整击穿电压。 此外,调整注入导电离子的参数,以将导电离子注入到高电压器件区域和低电压器件区域中。 在器件之间的隔离区域中形成的隔离阱用于在高电压器件区域上形成的分离器件和在低电压器件区域上形成的器件。 HV栅极氧化物层的厚度比用于调制高电压器件和低电压器件的阈值电压的LV栅极氧化物层的厚度厚。
    • 36. 发明授权
    • Low dropout voltage regulator providing adaptive compensation
    • 低压差稳压器提供自适应补偿
    • US07091710B2
    • 2006-08-15
    • US10838925
    • 2004-05-03
    • Ta-yung YangJenn-yu G. LinChien-Liang Chen
    • Ta-yung YangJenn-yu G. LinChien-Liang Chen
    • G05F1/40
    • G05F1/575
    • A method and apparatus to dynamically modify internal compensation of a low dropout (LDO) voltage regulator is provided. The LDO voltage regulator includes an output pass transistor, an error amplifier, a bias transistor and a compensation network. The compensation network is connected between a gate and a drain of the output pass transistor to compensate for the feedback loop. The compensation network and the bias transistor generate pole-zero pairs to perform a maximum 45 degrees phase shift before reaching the crossover frequency in the LDO voltage regulator. Therefore a minimum 45 degrees phase margin is provided for the feedback loop in various load conditions. Furthermore, the pole-zero pairs produced in the LDO voltage regulator are adaptively adjusted according to load conditions, so that the bandwidth is optimized and faster transient response is achieved.
    • 提供了一种用于动态修改低压差(LDO)电压调节器的内部补偿的方法和装置。 LDO稳压器包括输出传输晶体管,误差放大器,偏置晶体管和补偿网络。 补偿网络连接在输出传输晶体管的栅极和漏极之间,以补偿反馈环路。 补偿网络和偏置晶体管产生极点对,以在LDO稳压器达到交越频率之前执行最大45度相移。 因此,在各种负载条件下,为反馈回路提供最小45度的相位裕度。 此外,LDO稳压器中产生的极点对根据负载条件进行自适应调整,从而优化带宽,实现更快的瞬态响应。
    • 39. 发明授权
    • Over-voltage crowbar for lightning surge and ESD protection
    • 用于雷电浪涌和ESD保护的过电压撬棒
    • US06744611B2
    • 2004-06-01
    • US10065533
    • 2002-10-28
    • Ta-yung YangJenn-yu G. Lin
    • Ta-yung YangJenn-yu G. Lin
    • H02H900
    • H02H9/041
    • FI over-voltage crowbar provides lightning surge and ESD protection. The crowbar has a clamping transistor, which is driven by a mirror-amplifier. When an input surge voltage is higher than the voltage of a Zener diode, the mirror-amplifier will be switched on and generate an amplified voltage. The amplified voltage works together with a speed-up capacitor easily to switch on the clamping transistor. The mirror-amplifier has an n-transistor and two p-transistors, which provide sufficient headroom for the turn-on of a clamping transistor. The over-voltage crowbar of this invention rapidly drives the clamping transistor to low impedance, thereby achieving a higher sustenance rating for lightning surge and ESD in the integrated circuit.
    • FI过压撬棒提供雷电浪涌和ESD保护。 撬棒具有由镜像放大器驱动的钳位晶体管。 当输入浪涌电压高于齐纳二极管的电压时,镜像放大器将被接通并产生放大的电压。 放大的电压与加速电容一起工作,容易打开钳位晶体管。 镜面放大器具有n型晶体管和两个p型晶体管,为钳位晶体管的导通提供足够的余量。 本发明的过电压撬棒将钳位晶体管快速驱动到低阻抗,从而为集成电路中的雷电浪涌和ESD提供更高的维持等级。
    • 40. 发明授权
    • Fan speed pulse filter for a PWM fan
    • 用于PWM风扇的风扇速度脉冲滤波器
    • US06262549B1
    • 2001-07-17
    • US09607024
    • 2000-06-29
    • Ta-yung YangJenn-yu G. LinCheng-chi Hsueh
    • Ta-yung YangJenn-yu G. LinCheng-chi Hsueh
    • G01P3489
    • G01P3/489G01P3/481Y10S388/912
    • A fan speed pulse filter is used for a PWM fan. The filter comprises a comparator, a latch circuit and a synchronizer. The fan unit, including a tachometer pulse output, is controlled by a PWM signal for determining the fan speed. By comparing the PWM signal with a reference voltage, the comparator generates a reset signal. The latch circuit, coupled to the comparator and the fan unit, receives the reset signal and the tachometer pulse and outputs a filtered tachometer pulse containing no phantom pulses. Furthermore, a synchronizer generates an output signal without interruption when the PWM signal is switched off.
    • 风扇转速脉冲滤波器用于PWM风扇。 滤波器包括比较器,锁存电路和同步器。 包括转速计脉冲输出的风扇单元由用于确定风扇速度的PWM信号控制。 通过将PWM信号与参考电压进行比较,比较器产生复位信号。 耦合到比较器和风扇单元的锁存电路接收复位信号和转速计脉冲,并输出不含幻影脉冲的滤波转速计脉冲。 此外,当PWM信号关闭时,同步器产生输出信号而不中断。