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1. 发明授权

US07858466B2 Different-voltage device manufactured by a CMOS compatible process and high-voltage device used in the different-voltage device 有权
标题翻译：由CMOS兼容工艺制造的不同电压器件和用于不同电压器件的高压器件
公开(公告)号：US07858466B2
公开(公告)日：2010-12-28
申请号：US11682621
申请日：2007-03-06
申请人： Chih-Feng Huang , Ta-yung Yang , Jenn-yu G. Lin , Tuo-Hsin Chien
发明人： Chih-Feng Huang , Ta-yung Yang , Jenn-yu G. Lin , Tuo-Hsin Chien
IPC分类号： H01L21/8238
CPC分类号： H01L21/823814 , H01L21/823857 , H01L21/823892
摘要： A method of manufacturing different-voltage devices mainly comprises forming at least one high-voltage well in high-voltage device regions, at least one N-well in low-voltage device regions, at least one P-well in low-voltage device regions, source/drain wells in high-voltage device regions, and isolation wells in isolation regions in a p-type substrate. The breakdown voltage is adjusted by modulating the ion doping profile. Furthermore, parameters of implanting conductive ions are adjusted for implanting conductive ions into both high-voltage device regions and low-voltage device regions. The isolation wells formed in isolation regions between devices are for separating device formed over high-voltage device regions and device formed over low-voltage device regions. The thickness of a HV gate oxide layer is thicker than the thickness of an LV gate oxide layer for modulating threshold voltages of high-voltage devices and low-voltage devices.
摘要翻译：一种制造不同电压装置的方法主要包括在高电压装置区域中形成至少一个高电压阱，在低电压装置区域中形成至少一个N阱，在低电压装置区域中形成至少一个P阱，高压器件区域中的源/漏极阱以及p型衬底中的隔离区中的隔离阱。通过调制离子掺杂分布来调整击穿电压。此外，调整注入导电离子的参数，以将导电离子注入到高电压器件区域和低电压器件区域中。在器件之间的隔离区域中形成的隔离阱用于在高电压器件区域上形成的分离器件和在低电压器件区域上形成的器件。 HV栅极氧化物层的厚度比用于调制高电压器件和低电压器件的阈值电压的LV栅极氧化物层的厚度厚。

2. 发明授权

US07355250B2 Electrostatic discharge device with controllable holding current 有权
标题翻译：具有可控保持电流的静电放电装置
公开(公告)号：US07355250B2
公开(公告)日：2008-04-08
申请号：US11222707
申请日：2005-09-08
申请人： Chih-Feng Huang , Ta-yung Yang , Jenn-yu G. Lin , Tuo-Hsin Chien
发明人： Chih-Feng Huang , Ta-yung Yang , Jenn-yu G. Lin , Tuo-Hsin Chien
IPC分类号： H01L23/62 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113
CPC分类号： H01L27/0262
摘要： An electrostatic discharge (ESD) device with a parasitic silicon controlled rectifier (SCR) structure and controllable holding current is provided. A first distance is kept between a first N+ doped region and a first P+ doped region, and a second distance is kept between a second P+ doped region and a third N+ doped region. In addition, the holding current of the ESD device can be set to a specific value by modulating the first distance and the second distance. The holding current is in inverse proportion to the first distance and the second distance.
摘要翻译：提供具有寄生可控硅整流器（SCR）结构和可控保持电流的静电放电（ESD）器件。在第一N +掺杂区域和第一P +掺杂区域之间保持第一距离，并且在第二P +掺杂区域和第三N +掺杂区域之间保持第二距离。此外，通过调制第一距离和第二距离，可以将ESD装置的保持电流设定为特定值。保持电流与第一距离和第二距离成反比。

3. 发明授权

US06903421B1 Isolated high-voltage LDMOS transistor having a split well structure 失效
标题翻译：隔离式高压LDMOS晶体管具有分裂阱结构
公开(公告)号：US06903421B1
公开(公告)日：2005-06-07
申请号：US10758919
申请日：2004-01-16
申请人： Chih-Feng Huang , Ta-yung Yang , Jenn-yu G. Lin , Tuo-Hsin Chien
发明人： Chih-Feng Huang , Ta-yung Yang , Jenn-yu G. Lin , Tuo-Hsin Chien
IPC分类号： H01L23/62 , H01L27/088 , H01L29/06 , H01L29/08 , H01L29/76 , H01L29/78 , H01L29/94
CPC分类号： H01L29/0634 , H01L29/0696 , H01L29/0886 , H01L29/42368 , H01L29/7816 , H01L2924/0002 , H01L2924/00
摘要： The isolated high-voltage LDMOS transistor according to the present invention includes a split N-well and P-well in the extended drain region. The P-well is split in the extended drain region of the N-well to form a split junction-field in the N-well. The split N-well and P-well deplete the drift region, which shifts the electric field maximum into the bulk of the N-well. This achieves a higher breakdown voltage and allows the N-well to have a higher doping density. Furthermore, the LDMOS transistor according to the present invention includes a N-well embedded beneath the source diffusion region. This creates a low-impedance path for the source region, which restricts the transistor current flow between the drain region and the source region.
摘要翻译：根据本发明的隔离的高电压LDMOS晶体管在扩展漏极区域中包括分裂的N阱和P阱。 P阱在N阱的扩展漏极区域中分裂，以在N阱中形成分离的连接场。分裂的N阱和P阱消耗了漂移区域，其将电场最大值移动到N阱的大部分中。这实现了更高的击穿电压并且允许N阱具有更高的掺杂密度。此外，根据本发明的LDMOS晶体管包括嵌入在源极扩散区之下的N阱。这为源极区域产生低阻抗路径，这限制了漏极区域和源极区域之间的晶体管电流。

4. 发明授权

US07615826B2 Electrostatic discharge protection semiconductor structure 有权
标题翻译：静电放电保护半导体结构
公开(公告)号：US07615826B2
公开(公告)日：2009-11-10
申请号：US11427773
申请日：2006-06-29
申请人： Chih-Feng Huang , Tuo-Hsin Chien , Jenn-Yu G. Lin , Ta-yung Yang
发明人： Chih-Feng Huang , Tuo-Hsin Chien , Jenn-Yu G. Lin , Ta-yung Yang
IPC分类号： H01L23/62
CPC分类号： H01L27/0259
摘要： An electrostatic discharge (ESD) protection device with adjustable single-trigger or multi-trigger voltage is provided. The semiconductor structure has multi-stage protection semiconductor circuit function and adjustable discharge capacity. The single-trigger or multi-trigger semiconductor structure may be fabricated by using the conventional semiconductor process, and can be applied to IC semiconductor design and to effectively protect the important semiconductor devices and to prevent the semiconductor devices from ESD damage. In particular, the present invention can meet the requirements of high power semiconductor device and has better protection function compared to conventional ESD protection circuit. In the present invention, a plurality of N-wells or P-wells connected in parallel are used to adjust the discharge capacity of various wells in the P-substrate so as to improve the ESD protection capability and meet different power standards.
摘要翻译：提供具有可调单触发或多触发电压的静电放电（ESD）保护装置。半导体结构具有多级保护半导体电路功能和可调放电容量。单触发或多触发半导体结构可以通过使用传统的半导体工艺制造，并且可以应用于IC半导体设计并且有效地保护重要的半导体器件并且防止半导体器件受到ESD损坏。特别地，本发明可以满足大功率半导体器件的要求，与传统的ESD保护电路相比具有更好的保护功能。在本发明中，使用并联连接的多个N阱或P阱来调整P基板中的各个阱的放电容量，以提高ESD保护能力并满足不同的功率标准。

5. 发明授权

US07205201B2 CMOS compatible process with different-voltage devices 有权
标题翻译： CMOS兼容过程与不同电压器件
公开(公告)号：US07205201B2
公开(公告)日：2007-04-17
申请号：US10914943
申请日：2004-08-09
申请人： Chih-Feng Huang , Ta-yung Yang , Jenn-yu G. Lin , Tuo-Hsin Chien
发明人： Chih-Feng Huang , Ta-yung Yang , Jenn-yu G. Lin , Tuo-Hsin Chien
IPC分类号： H01L21/8234
CPC分类号： H01L21/823814 , H01L21/823857 , H01L21/823892
摘要： A method of manufacturing different-voltage devices mainly comprises forming at least one high-voltage well in high-voltage device regions, at least one N-well in low-voltage device regions, at least one P-well in low-voltage device regions, source/drain wells in high-voltage device regions, and isolation wells in isolation regions in a p-type substrate. The breakdown voltage is adjusted by modulating the ion doping profile. Furthermore, parameters of implanting conductive ions are adjusted for implanting conductive ions into both high-voltage device regions and low-voltage device regions. The isolation wells formed in isolation regions between devices are for separating device formed over high-voltage device regions and device formed over low-voltage device regions. The thickness of a HV gate oxide layer is thicker than the thickness of an LV gate oxide layer for modulating threshold voltages of high-voltage devices and low-voltage devices.
摘要翻译：一种制造不同电压装置的方法主要包括在高电压装置区域中形成至少一个高电压阱，在低电压装置区域中形成至少一个N阱，在低电压装置区域中形成至少一个P阱，高压器件区域中的源/漏极阱以及p型衬底中的隔离区中的隔离阱。通过调制离子掺杂分布来调整击穿电压。此外，调整注入导电离子的参数，以将导电离子注入到高电压器件区域和低电压器件区域中。在器件之间的隔离区域中形成的隔离阱用于在高电压器件区域上形成的分离器件和在低电压器件区域上形成的器件。 HV栅极氧化物层的厚度比用于调制高电压器件和低电压器件的阈值电压的LV栅极氧化物层的厚度厚。

6. 发明授权

US06995428B2 High voltage LDMOS transistor having an isolated structure 有权
标题翻译：具有隔离结构的高压LDMOS晶体管
公开(公告)号：US06995428B2
公开(公告)日：2006-02-07
申请号：US10786703
申请日：2004-02-24
申请人： Chih-Feng Huang , Ta-yung Yang , Jenn-yu G. Lin , Tuo-Hsin Chien
发明人： Chih-Feng Huang , Ta-yung Yang , Jenn-yu G. Lin , Tuo-Hsin Chien
IPC分类号： H01L29/76
CPC分类号： H01L29/0634 , H01L29/0878 , H01L29/0886 , H01L29/42368 , H01L29/7816
摘要： A high voltage LDMOS transistor according to the present invention includes a P-field and divided P-fields in an extended drain region of a N-well. The P-field and divided P-fields form junction-fields in the N-well, in which a drift region is fully depleted before breakdown occurs. Therefore, a higher breakdown voltage is achieved and a higher doping density of the N-well is allowed. Higher doping density can effectively reduce the on-resistance of the LDMOS transistor. Furthermore, the N-well generated beneath a source diffusion region provides a low-impedance path for a source region, which restrict the transistor current flow in between a drain region and a source region.
摘要翻译：根据本发明的高电压LDMOS晶体管包括在N阱的扩展漏极区域中的P场和分割的P场。 P场和分割的P场在N阱中形成结场，其中漂移区在击穿之前被完全耗尽。因此，实现更高的击穿电压，并且允许N阱的较高的掺杂密度。较高的掺杂密度可以有效降低LDMOS晶体管的导通电阻。此外，在源极扩散区域之下产生的N阱为源极区域提供了低阻抗路径，其限制了漏极区域和源极区域之间的晶体管电流。

7. 发明授权

US06873011B1 High voltage and low on-resistance LDMOS transistor having equalized capacitance 失效
标题翻译：具有均衡电容的高电压和低导通电阻LDMOS晶体管
公开(公告)号：US06873011B1
公开(公告)日：2005-03-29
申请号：US10786701
申请日：2004-02-24
申请人： Chih-Feng Huang , Ta-yung Yang , Jenn-yu G. Lin , Tuo-Hsin Chien
发明人： Chih-Feng Huang , Ta-yung Yang , Jenn-yu G. Lin , Tuo-Hsin Chien
IPC分类号： H01L29/06 , H01L29/78 , H01L29/94
CPC分类号： H01L29/7816 , H01L29/0623 , H01L29/0634 , H01L29/0696
摘要： A high voltage LDMOS transistor according to the present invention includes P-field blocks in the extended drain region of a N-well. The P-field blocks form the junction-fields in the N-well for equalizing the capacitance of parasitic capacitors between the drain region and the source region and fully deplete the drift region before breakdown occurs. A higher breakdown voltage is therefore achieved and the N-well having a higher doping density is thus allowed. The higher doping density reduces the on-resistance of the transistor. Furthermore, the portion of the N-well generated beneath the source diffusion region produces a low-impedance path for the source region, which restricts the transistor current flow in between the drain region and the source region.
摘要翻译：根据本发明的高电压LDMOS晶体管包括N阱扩展漏极区中的P场区块。 P-场块形成N阱中的结场，用于均衡漏极区域和源极区域之间的寄生电容器的电容，并且在击穿之前完全耗尽漂移区域。因此实现更高的击穿电压，因此允许具有较高掺杂密度的N阱。较高的掺杂密度降低了晶体管的导通电阻。此外，在源极扩散区域之下产生的N阱的部分产生用于源极区域的低阻抗路径，其限制了漏极区域和源极区域之间的晶体管电流。

8. 发明授权

US07285837B2 Electrostatic discharge device integrated with pad 有权
标题翻译：静电放电装置与垫片集成
公开(公告)号：US07285837B2
公开(公告)日：2007-10-23
申请号：US10905677
申请日：2005-01-17
申请人： Chih-Feng Huang , Tuo-Hsin Chien , Jenn-yu G. Lin , Ta-yung Yang
发明人： Chih-Feng Huang , Tuo-Hsin Chien , Jenn-yu G. Lin , Ta-yung Yang
IPC分类号： H01L23/58
CPC分类号： H01L27/0255
摘要： A structure of an electrostatic discharge (ESD) device integrated with a pad is provided. The ESD device is integrated with the pad and formed under the pad. By using the area under the pad, the ESD device does not occupy additional space of an integrated circuit. Furthermore, since the pad is a large, plate, and ideal conductor, the connected pad and the ESD device are capable of distributing current in the ESD device averagely.
摘要翻译：提供了与焊盘集成的静电放电（ESD）器件的结构。 ESD器件与焊盘集成并形成在焊盘下方。通过使用垫下的区域，ESD器件不占用集成电路的额外空间。此外，由于焊盘是大的，板状的和理想的导体，所以连接的焊盘和ESD器件能够平均地在ESD器件中分配电流。

9. 发明授权

US07102194B2 High voltage and low on-resistance LDMOS transistor having radiation structure and isolation effect 有权
标题翻译：具有辐射结构和隔离效果的高电压和低导通电阻LDMOS晶体管
公开(公告)号：US07102194B2
公开(公告)日：2006-09-05
申请号：US10919916
申请日：2004-08-16
申请人： Chih-Feng Huang , Ta-yung Yang , Jenn-yu G. Lin , Tuo-Hsin Chien
发明人： Chih-Feng Huang , Ta-yung Yang , Jenn-yu G. Lin , Tuo-Hsin Chien
IPC分类号： H01L29/94
CPC分类号： H01L29/7816 , H01L29/0634 , H01L29/0692 , H01L29/0696 , H01L29/0886 , H01L29/42368
摘要： A high voltage LDMOS transistor according to the present invention includes at least one P-field block in the extended drain region of the N-well. The P-field blocks form junction-fields in the N-well for equalizing the capacitance of parasitic capacitors between the drain region and the source region and fully deplete the drift region before breakdown occurs. A higher breakdown voltage is therefore achieved and the N-well having a higher doping density is thus allowed. The source region and P-field blocks enclose the drain region, which makes the LDMOS transistor self-isolated.
摘要翻译：根据本发明的高电压LDMOS晶体管包括N阱扩展漏极区中的至少一个P场模块。 P场块在N阱中形成结场，用于均衡漏极区和源极区之间的寄生电容的电容，并在击穿之前完全耗尽漂移区。因此实现更高的击穿电压，因此允许具有较高掺杂密度的N阱。源极区域和P场区域封装漏极区域，这使得LDMOS晶体管自隔离。

10. 发明申请

US20060157790A1 ELECTROSTATIC DISCHARGE DEVICE INTEGRATED WITH PAD 有权
标题翻译：静电放电装置与PAD集成
公开(公告)号：US20060157790A1
公开(公告)日：2006-07-20
申请号：US10905677
申请日：2005-01-17
申请人： Chih-Feng Huang , Tuo-Hsin Chien , Jenn-yu G. Lin , Ta-yung Yang
发明人： Chih-Feng Huang , Tuo-Hsin Chien , Jenn-yu G. Lin , Ta-yung Yang
IPC分类号： H01L23/62
CPC分类号： H01L27/0255
摘要： A structure of an electrostatic discharge (ESD) device integrated with a pad is provided. The ESD device is integrated with the pad and formed under the pad. By using the area under the pad, the ESD device does not occupy additional space of an integrated circuit. Furthermore, since the pad is a large, plate, and ideal conductor, the connected pad and the ESD device are capable of distributing current in the ESD device averagely.
摘要翻译：提供了与焊盘集成的静电放电（ESD）器件的结构。 ESD器件与焊盘集成并形成在焊盘下方。通过使用垫下的区域，ESD器件不占用集成电路的额外空间。此外，由于焊盘是大的，板状的和理想的导体，所以连接的焊盘和ESD器件能够平均地在ESD器件中分配电流。

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