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31. 发明授权

US08164004B2 Embedded circuit structure and fabricating process of the same 有权
标题翻译：嵌入式电路结构及其制作工艺相同
公开(公告)号：US08164004B2
公开(公告)日：2012-04-24
申请号：US11958920
申请日：2007-12-18
申请人： Tsung-Yuan Chen , Shu-Sheng Chiang
发明人： Tsung-Yuan Chen , Shu-Sheng Chiang
IPC分类号： H05K1/11
CPC分类号： H05K3/107 , H05K3/045 , H05K3/423 , H05K3/426 , H05K2201/0376 , H05K2201/09036 , H05K2201/09563 , Y10T29/49155 , Y10T29/49165
摘要： A fabricating process for an embedded circuit structure is provided. A through hole is formed in a core panel and penetrates the core panel. Two indent patterns are respectively formed on two opposite surfaces of the core panel. A conductive material is electroplated into the through hole and the indent patterns, so as to form a conductive channel in the through hole and two circuit patterns in the indent patterns respectively. Portions of the circuit patterns, which exceed the indent patterns respectively, are removed for planarizing the circuit patterns to be level with the two surfaces of the core panel respectively.
摘要翻译：提供了一种用于嵌入式电路结构的制造工艺。在芯板中形成贯通孔，贯通芯板。在芯板的两个相对的表面上分别形成两个压痕图案。将导电材料电镀到通孔和凹陷图案中，以在通孔中分别形成导电通道和凹陷图案中的两个电路图案。电路图案的分别超过凹口图案的部分被去除，用于将电路图案平坦化以与芯板的两个表面分级。

32. 发明授权

US08132321B2 Method for making embedded circuit structure 有权
标题翻译：制作嵌入式电路结构的方法
公开(公告)号：US08132321B2
公开(公告)日：2012-03-13
申请号：US12190602
申请日：2008-08-13
申请人： Yi-Chun Liu , Wei-Ming Cheng , Tsung-Yuan Chen , Shu-Sheng Chiang
发明人： Yi-Chun Liu , Wei-Ming Cheng , Tsung-Yuan Chen , Shu-Sheng Chiang
IPC分类号： H01K3/10
CPC分类号： H05K3/465 , H05K3/0032 , H05K3/0035 , H05K3/0055 , H05K3/383 , H05K3/421 , H05K3/4661 , H05K2203/0796 , H05K2203/1383
摘要： An embedded structure of circuit board is provided. The embedded structure includes a substrate, a first patterned conductive layer disposed on the substrate and selectively exposing the substrate, a first dielectric layer covering the first patterned conductive layer and the substrate, a pad opening disposed in the first dielectric layer, and a via disposed in the pad opening and exposing the first patterned conductive layer, wherein the outer surface of the first dielectric layer has a substantially even surface.
摘要翻译：提供电路板的嵌入式结构。所述嵌入式结构包括基板，设置在所述基板上并选择性地暴露所述基板的第一图案化导电层，覆盖所述第一图案化导电层和所述基板的第一介电层，设置在所述第一介电层中的焊盘开口，在所述焊盘开口中并暴露所述第一图案化导电层，其中所述第一介电层的外表面具有基本上均匀的表面。

33. 发明申请

US20110147339A1 METHOD FOR MANUFACTURING WIRING STRUCTURE OF WIRING BOARD 有权
标题翻译：制造接线板接线结构的方法
公开(公告)号：US20110147339A1
公开(公告)日：2011-06-23
申请号：US12793560
申请日：2010-06-03
申请人： Shu-Sheng Chiang , Tsung-Yuan Chen , Wei-Ming Cheng
发明人： Shu-Sheng Chiang , Tsung-Yuan Chen , Wei-Ming Cheng
IPC分类号： B05D5/12 , C23C16/00 , B32B37/00 , B29C35/08 , C25D5/02
CPC分类号： B32B38/04 , B32B2311/00 , B32B2457/08 , C23C18/1608 , C23C18/1653 , C23C18/1831 , C23C18/31 , H05K3/107
摘要： A method for manufacturing a wiring structure of a wiring board is provided. In the method, a substrate including an insulation layer and a film disposed on the insulation layer is provided. Next, a barrier layer completely covering the film is formed. Next, an intaglio pattern partially exposing the insulation layer is formed on an outer surface of the barrier layer. Next, an activated layer is formed on the outer surface and in the intaglio pattern. Then, the activated layer on the outer surface is removed, and the activated layer in the intaglio pattern is remained. After the activated layer on the outer surface is removed, a conductive material is formed in the intaglio pattern by using a chemical deposition method. After forming the conductive material, the barrier layer and the film are removed.
摘要翻译：提供一种用于制造布线板的布线结构的方法。在该方法中，提供了包括绝缘层和设置在绝缘层上的膜的衬底。接下来，形成完全覆盖该膜的阻挡层。接下来，在阻挡层的外表面上形成部分地露出绝缘层的凹版图案。接下来，在外表面和凹版图案中形成活化层。然后，去除外表面上的活化层，并保留凹版图案中的活化层。在去除外表面上的活化层之后，通过使用化学沉积方法在凹版图案中形成导电材料。在形成导电材料之后，去除阻挡层和膜。

34. 发明授权

US07926172B2 Embedded circuit board and process thereof 有权
标题翻译：嵌入式电路板及其工艺
公开(公告)号：US07926172B2
公开(公告)日：2011-04-19
申请号：US11774728
申请日：2007-07-09
申请人： Tsung-Yuan Chen , Shu-Sheng Chiang
发明人： Tsung-Yuan Chen , Shu-Sheng Chiang
IPC分类号： H05K3/36 , H05K3/02
CPC分类号： H05K1/0366 , H05K3/205 , H05K3/426 , H05K2201/0959 , Y10T29/49126 , Y10T29/49128 , Y10T29/49155 , Y10T29/49165
摘要： An embedded circuit board including a glass fiber layer, two dielectric layers, and two circuit layers is provided. The glass fiber layer has a first surface and a second surface corresponding to the first surface. The dielectric layers are disposed on the first surface and the second surface, respectively. The circuit layers are embedded in the dielectric layers above the first surface and the second surface, respectively. The outer surface of each circuit layer is coplanar with the outer surface of each dielectric layer, and a distance between the circuit layer and the glass fiber layer is greater than or equal to 3 μm. In addition, a process of the embedded circuit board is provided.
摘要翻译：提供了包括玻璃纤维层，两个电介质层和两个电路层的嵌入式电路板。玻璃纤维层具有对应于第一表面的第一表面和第二表面。电介质层分别设置在第一表面和第二表面上。电路层分别嵌入在第一表面和第二表面上方的电介质层中。每个电路层的外表面与每个电介质层的外表面共面，并且电路层和玻璃纤维层之间的距离大于或等于3μm。此外，提供了嵌入式电路板的处理。

35. 发明申请

US20100038124A1 EMBEDDED STRUCTURE AND METHOD FOR MAKING THE SAME 有权
标题翻译：嵌入式结构及其制作方法
公开(公告)号：US20100038124A1
公开(公告)日：2010-02-18
申请号：US12190602
申请日：2008-08-13
申请人： Yi-Chun Liu , Wei-Ming Cheng , Tsung-Yuan Chen , Shu-Sheng Chiang
发明人： Yi-Chun Liu , Wei-Ming Cheng , Tsung-Yuan Chen , Shu-Sheng Chiang
IPC分类号： H05K3/10 , H05K1/11
CPC分类号： H05K3/465 , H05K3/0032 , H05K3/0035 , H05K3/0055 , H05K3/383 , H05K3/421 , H05K3/4661 , H05K2203/0796 , H05K2203/1383
摘要： An embedded structure of circuit board is provided. The embedded structure includes a substrate, a first patterned conductive layer disposed on the substrate and selectively exposing the substrate, a first dielectric layer covering the first patterned conductive layer and the substrate, a pad opening disposed in the first dielectric layer, and a via disposed in the pad opening and exposing the first patterned conductive layer, wherein the outer surface of the first dielectric layer has a substantially even surface.
摘要翻译：提供电路板的嵌入式结构。所述嵌入式结构包括基板，设置在所述基板上并选择性地暴露所述基板的第一图案化导电层，覆盖所述第一图案化导电层和所述基板的第一介电层，设置在所述第一介电层中的焊盘开口，在所述焊盘开口中并暴露所述第一图案化导电层，其中所述第一介电层的外表面具有基本上均匀的表面。

36. 发明申请

US20090282674A1 ELECTRICAL INTERCONNECT STRUCTURE AND PROCESS THEREOF AND CIRCUIT BOARD STRUCTURE 有权
标题翻译：电气互连结构及其工艺及电路板结构
公开(公告)号：US20090282674A1
公开(公告)日：2009-11-19
申请号：US12345364
申请日：2008-12-29
申请人： Tsung-Yuan Chen , Shu-Sheng Chiang , David C. H. Cheng
发明人： Tsung-Yuan Chen , Shu-Sheng Chiang , David C. H. Cheng
IPC分类号： H01R9/00 , H05K1/14 , H05K1/11
CPC分类号： H05K3/465 , H05K1/0265 , H05K3/0032 , H05K3/0038 , H05K3/107 , H05K3/426 , H05K3/428 , H05K3/4602 , H05K3/4652 , H05K2201/09536 , H05K2201/09736 , Y10T29/49147
摘要： An electrical interconnecting structure suitable for a circuit board is provided. The electrical interconnecting structure includes a core, an ultra fine pattern, and a patterned conductive layer. The core has a surface, and the ultra fine pattern is inlaid in the surface of the core. The patterned conductive layer is disposed on the surface of the core and is partially connected to the ultra fine pattern. Since the ultra fine pattern of the electrical interconnecting structure is inlaid in the surface of the core and is partially connected to the patterned conductive layer located on the surface of the core.
摘要翻译：提供了适用于电路板的电互连结构。电互连结构包括芯，超细图案和图案化导电层。芯具有表面，并且超细图案镶嵌在芯的表面中。图案化导电层设置在芯的表面上并且部分地连接到超细图案。由于电互连结构的超细图案镶嵌在芯的表面中，并且部分地连接到位于芯的表面上的图案化导电层。

37. 发明授权

US09116191B2 Voltage-drop testing system, voltage-drop control apparatus, and method thereof 有权
标题翻译：降压测试系统，压降控制装置及其方法
公开(公告)号：US09116191B2
公开(公告)日：2015-08-25
申请号：US13421858
申请日：2012-03-15
申请人： Tsung-Yuan Chen , Kuei-Chih Hou , Wen-Kai Chiang
发明人： Tsung-Yuan Chen , Kuei-Chih Hou , Wen-Kai Chiang
IPC分类号： G01R31/02 , G01R31/00
CPC分类号： G01R31/001 , G01R31/002
摘要： A voltage-drop testing system, including a voltage-drop control apparatus, and a voltage-drop testing method adapted for the voltage-drop testing system based on LABVIEW department platform. When the LABVIEW department platform 12 is running, different groups of test data may be transferred to the PLD tester 20, when the PLD tester 20 finishes the testing based on all groups of test data, the PLD tester 20 feeds back the test results to the LABVIEW department platform 12, and the LABVIEW department platform 12 creates the voltage-drop testing graphic frame displaying the test results for the electronic device under test 2 for the convenience of a user.
摘要翻译：一种降压测试系统，包括压降控制装置和适用于基于LABVIEW部门平台的降压测试系统的降压测试方法。当LABVIEW部门平台12运行时，当PLD测试器20基于所有测试数据组完成测试时，不同组的测试数据可以被传送到PLD测试器20，PLD测试器20将测试结果反馈给 LABVIEW部门平台12和LABVIEW部门平台12为了方便用户创建了显示被测电子设备2的测试结果的电压降测试图形框架。

38. 发明申请

US20120313240A1 SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF 审中-公开
标题翻译：半导体封装及其制造方法
公开(公告)号：US20120313240A1
公开(公告)日：2012-12-13
申请号：US13241285
申请日：2011-09-23
申请人： Shih-Lian Cheng , Tsung-Yuan Chen
发明人： Shih-Lian Cheng , Tsung-Yuan Chen
IPC分类号： H01L23/498 , H01L21/60
CPC分类号： H01L23/49822 , H01L24/13 , H01L24/16 , H01L24/81 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/16225 , H01L2224/16227 , H01L2224/16237 , H01L2224/32225 , H01L2224/73204 , H01L2224/81191 , H01L2224/81411 , H01L2924/12042 , H01L2924/15311 , H01L2924/00 , H01L2924/00014
摘要： A semiconductor package includes a substrate having a flip chip bonding area. A plurality of recessed bump pads are disposed in the flip chip bonding area. The substrate further includes a solder mask that covers a circuit area. A chip having a plurality of metal bumps is mounted in the flip chip bonding area. The metal bumps are respectively connected to the recessed bump pads. An underfill is filled into the gap between the substrate and the chip.
摘要翻译：半导体封装包括具有倒装芯片接合区域的衬底。多个凹陷凸块焊盘设置在倒装芯片接合区域中。基板还包括覆盖电路区域的焊接掩模。具有多个金属凸块的芯片安装在倒装芯片接合区域中。金属凸块分别连接到凹凸焊盘。将底部填充物填充到基板和芯片之间的间隙中。

39. 发明授权

US08322679B2 Container data center 失效
标题翻译：集装箱数据中心
公开(公告)号：US08322679B2
公开(公告)日：2012-12-04
申请号：US13193592
申请日：2011-07-28
申请人： Tsung-Yuan Chen
发明人： Tsung-Yuan Chen
IPC分类号： F16M13/00
CPC分类号： H05K7/1497
摘要： A container data center includes a container, a number of shock absorbers installed in the container, and a support plate installed on the shock absorbers. Each shock absorber includes a support bracket and two damping elements positioned at opposite ends of the support bracket. Each damping element includes a first connecting end fixed to a corresponding end of the support bracket, and a second connecting end fixed to the container. The first connecting ends of the damping elements are movable relative to the corresponding second ends of the damping elements through overcoming resistance. The support plate is installed on the support bracket and can support a number of servers.
摘要翻译：容器数据中心包括容器，安装在容器中的多个减震器和安装在减震器上的支撑板。每个减震器包括支撑支架和位于支撑支架的相对端的两个阻尼元件。每个阻尼元件包括固定到支撑托架的对应端的第一连接端和固定到容器的第二连接端。阻尼元件的第一连接端可通过克服阻力相对于阻尼元件的对应的第二端移动。支撑板安装在支架上，可支撑多台服务器。

40. 发明申请

US20120174391A1 PROCESS FOR FABRICATING WIRING BOARD 审中-公开
标题翻译：制造布线板的工艺
公开(公告)号：US20120174391A1
公开(公告)日：2012-07-12
申请号：US13423578
申请日：2012-03-19
申请人： Tsung-Yuan Chen , Chun-Chien Chen , Cheng-Po Yu
发明人： Tsung-Yuan Chen , Chun-Chien Chen , Cheng-Po Yu
IPC分类号： H05K3/00
CPC分类号： H05K3/428 , H05K3/0032 , H05K3/0035 , H05K3/0038 , H05K3/20 , H05K3/205 , H05K2201/09509 , H05K2201/09563 , H05K2201/0969 , H05K2203/0369 , H05K2203/0376 , H05K2203/0384 , H05K2203/0554 , H05K2203/108 , H05K2203/1476 , Y10T29/49124 , Y10T29/49126
摘要： A process for fabricating a wiring board is provided. In the process, a wiring carrying substrate including a carry substrate and a wiring layer is formed. Next, at least one blind via is formed in the wiring carrying substrate. Next, the wiring carrying substrate is laminated to another wiring carrying substrate via an insulation layer. The insulation layer is disposed between the wiring layers of the wiring carrying substrates and full fills the blind via. Next, parts of the carry substrates are removed to expose the insulation layer in the blind via. Next, a conductive pillar connected between the wiring layers is formed. Next, the rest carry substrates are removed.
摘要翻译：提供一种制造布线板的工艺。在该过程中，形成包括携带衬底和布线层的布线承载衬底。接下来，在布线承载基板中形成至少一个盲孔。接下来，通过绝缘层将布线承载基板层叠到另一布线承载基板。绝缘层设置在布线基板的布线层之间，并且完全填充盲孔。接下来，去除部分搬运基板以露出盲孔中的绝缘层。接下来，形成连接在布线层之间的导电柱。接下来，其余的携带衬底被去除。

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