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31. 发明授权

US08847306B2 Direct contact in trench with three-mask shield gate process 有权
标题翻译：直接接触沟槽与三屏蔽屏蔽门工艺
公开(公告)号：US08847306B2
公开(公告)日：2014-09-30
申请号：US13343666
申请日：2012-01-04
申请人： Sung-Shan Tai , Hamza Yilmaz , Anup Bhalla , Hong Chang , John Chen
发明人： Sung-Shan Tai , Hamza Yilmaz , Anup Bhalla , Hong Chang , John Chen
IPC分类号： H01L29/66 , H01L21/336 , H01L29/423 , H01L29/78 , H01L29/40 , H01L29/45 , H01L29/49 , H01L29/08 , H01L21/265
CPC分类号： H01L29/7813 , H01L21/26586 , H01L29/0869 , H01L29/407 , H01L29/4236 , H01L29/4238 , H01L29/456 , H01L29/4933 , H01L29/66727 , H01L29/66734 , H01L29/7811
摘要： A semiconductor substrate may be etched to form trenches with three different widths. A first conductive material is formed at the bottom of the trenches. A second conductive material separated by an insulator is formed over the first conductive material. A first insulator layer is formed on the trenches. A body layer is formed in the substrate. A source is formed in the body layer. A second insulator layer is formed on the trenches and source. Source and gate contacts are formed through the second insulator layer. Source and gate metal are formed on the second insulator layer. This abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
摘要翻译：可以蚀刻半导体衬底以形成具有三个不同宽度的沟槽。第一导电材料形成在沟槽的底部。在第一导电材料上方形成由绝缘体隔开的第二导电材料。在沟槽上形成第一绝缘体层。在衬底中形成体层。源体形成在体层中。在沟槽和源极上形成第二绝缘体层。源极和栅极触点通过第二绝缘体层形成。源极和栅极金属形成在第二绝缘体层上。提供该摘要以符合要求抽象的规则，允许搜索者或其他读者快速确定技术公开内容的主题。提交它的理解是，它不会用于解释或限制权利要求的范围或含义。

32. 发明申请

US20140225187A1 DEVICE STRUCTURE AND MANUFACTURING METHOD USING HDP DEPOSITED SOURCE-BODY IMPLANT BLOCK 审中-公开
标题翻译：使用HDP沉积源体植入块的装置结构和制造方法
公开(公告)号：US20140225187A1
公开(公告)日：2014-08-14
申请号：US13763644
申请日：2013-02-09
申请人： Anup Bhalla , François Hébert , Sung-Shan Tai , Sik K. Lui
发明人： Anup Bhalla , François Hébert , Sung-Shan Tai , Sik K. Lui
IPC分类号： H01L29/78 , H01L29/66 , H01L21/265
CPC分类号： H01L29/7827 , H01L21/265 , H01L21/2652 , H01L21/26586 , H01L21/266 , H01L29/0619 , H01L29/1095 , H01L29/407 , H01L29/4236 , H01L29/42368 , H01L29/66666 , H01L29/66734 , H01L29/7806 , H01L29/7811 , H01L29/7813
摘要： This invention discloses a semiconductor power device. The trenched semiconductor power device includes a trenched gate, opened from a top surface of a semiconductor substrate, surrounded by a source region encompassed in a body region near the top surface above a drain region disposed on a bottom surface of a substrate. The semiconductor power device further includes an implanting-ion block disposed above the top surface on a mesa area next to the body region having a thickness substantially larger than 0.3 micron for blocking body implanting ions and source ions from entering into the substrate under the mesa area whereby masks for manufacturing the semiconductor power device can be reduced.
摘要翻译：本发明公开了一种半导体功率器件。沟槽半导体功率器件包括从半导体衬底的顶表面开口的沟槽栅极，被包围在设置在衬底底表面上的漏区以上的顶表面附近的体区中的源极区围绕。所述半导体功率器件还包括植入离子块，所述植入离子块设置在所述身体区域旁边的台面区域的上表面上，所述植入离子块具有基本上大于0.3微米的厚度，用于阻挡体注入离子和源离子进入台面区域从而可以减少用于制造半导体功率器件的掩模。

33. 发明申请

US20130175612A1 DUAL GATE OXIDE TRENCH MOSFET WITH CHANNEL STOP TRENCH 有权
标题翻译：具有通道停止电位器的双栅氧化物晶体管MOSFET
公开(公告)号：US20130175612A1
公开(公告)日：2013-07-11
申请号：US13780579
申请日：2013-02-28
申请人： Sung-Shan Tai , Sik Lui , Xiaobin Wang
发明人： Sung-Shan Tai , Sik Lui , Xiaobin Wang
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L29/0638 , H01L29/0653 , H01L29/0878 , H01L29/407 , H01L29/41766 , H01L29/4236 , H01L29/456 , H01L29/66727 , H01L29/66734 , H01L29/7811
摘要： A semiconductor device and fabrication methods are disclosed. The device includes a plurality of gate electrodes formed in trenches located in an active region of a semiconductor substrate. A first gate runner is formed in the substrate and electrically connected to the gate electrodes, wherein the first gate runner surrounds the active region. A second gate runner is connected to the first gate runner and located between the active region and a termination region. A termination structure surrounds the first and second gate runners and the active region. The termination structure includes a conductive material in an insulator-lined trench in the substrate, wherein the termination structure is electrically shorted to a source or body layer of the substrate thereby forming a channel stop for the device.
摘要翻译：公开了半导体器件和制造方法。该器件包括形成在位于半导体衬底的有源区中的沟槽中的多个栅电极。第一栅极流道形成在基板中并电连接到栅电极，其中第一栅极流道围绕有源区。第二浇口浇道连接到第一浇口浇道并且位于活性区域和终止区域之间。终端结构围绕第一和第二栅极流道和有源区域。端接结构包括在衬底中的绝缘体衬里的沟槽中的导电材料，其中端接结构电气短路到衬底的源极或体层，从而形成用于器件的通道停止。

34. 发明授权

US08236653B2 Configuration and method to form MOSFET devices with low resistance silicide gate and mesa contact regions 有权
标题翻译：用于形成具有低电阻硅化物栅极和台面接触区域的MOSFET器件的配置和方法
公开(公告)号：US08236653B2
公开(公告)日：2012-08-07
申请号：US13361950
申请日：2012-01-31
申请人： Yongzhong Hu , Sung-Shan Tai
发明人： Yongzhong Hu , Sung-Shan Tai
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L29/456 , H01L29/4933 , H01L29/66719 , H01L29/66734
摘要： A novel integration scheme for forming power MOSFET, particularly forming salicided layers for both gate contact regions and mesa contact regions, as well as using multiple energy contact implants through the salicided layer to form conductive body contacts which short to the source region by the salicided layers.
摘要翻译：一种用于形成功率MOSFET的新颖的集成方案，特别是形成用于两个栅极接触区域和台面接触区域的浸渍层，以及使用多个能量接触植入物通过该水浸层形成导电体接触物，该接触体通过浸渍层。

35. 发明申请

US20120129306A1 CONFIGURATION AND METHOD TO FORM MOSFET DEVICES WITH LOW RESISTANCE SILICIDE GATE AND MESA CONTACT REGIONS 有权
标题翻译：形成具有低电阻硅胶门和MESA接触区域的MOSFET器件的配置和方法
公开(公告)号：US20120129306A1
公开(公告)日：2012-05-24
申请号：US13361950
申请日：2012-01-31
申请人： Yongzhong Hu , Sung-Shan Tai
发明人： Yongzhong Hu , Sung-Shan Tai
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L29/456 , H01L29/4933 , H01L29/66719 , H01L29/66734
摘要： A novel integration scheme for forming power MOSFET, particularly forming salicided layers for both gate contact regions and mesa contact regions, as well as using multiple energy contact implants through the salicided layer to form conductive body contacts which short to the source region by the salicided layers.
摘要翻译：一种用于形成功率MOSFET的新颖的集成方案，特别是形成用于两个栅极接触区域和台面接触区域的浸渍层，以及使用多个能量接触植入物通过该水浸层形成导电体接触物，该接触体通过浸渍层。

36. 发明申请

US20120112268A1 TERMINATION STRUCTURE OF POWER SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：功率半导体器件的终止结构及其制造方法
公开(公告)号：US20120112268A1
公开(公告)日：2012-05-10
申请号：US13038346
申请日：2011-03-01
申请人： Sung-Shan Tai , Hung-Sheng Tsai
发明人： Sung-Shan Tai , Hung-Sheng Tsai
IPC分类号： H01L29/78 , H01L29/06 , H01L21/336
CPC分类号： H01L29/7813 , H01L29/0638 , H01L29/0653 , H01L29/0661 , H01L29/0696 , H01L29/41766 , H01L29/4238 , H01L29/66727 , H01L29/66734 , H01L29/7811 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a termination structure of a power semiconductor device and a manufacturing method thereof. The power semiconductor device has an active region and a termination region. The termination region surrounds the active region, and the termination structure is disposed in the termination region. The termination structure includes a semiconductor substrate, an insulating layer and a metal layer. The semiconductor substrate has a trench disposed in the termination region. The insulating layer is partially filled into the trench and covers the semiconductor substrate, and a top surface of the insulating layer has a hole. The metal layer is disposed on the insulating layer, and is filled into the hole.
摘要翻译：本发明提供一种功率半导体器件的端接结构及其制造方法。功率半导体器件具有有源区和端接区。终端区域围绕有源区域，终端结构设置在终端区域中。端接结构包括半导体衬底，绝缘层和金属层。半导体衬底具有设置在终端区域中的沟槽。绝缘层部分地填充到沟槽中并且覆盖半导体衬底，并且绝缘层的顶表面具有孔。金属层设置在绝缘层上，并被填充到孔中。

37. 发明授权

US08035159B2 Device structure and manufacturing method using HDP deposited source-body implant block 有权
标题翻译：使用HDP沉积源体植入块的装置结构和制造方法
公开(公告)号：US08035159B2
公开(公告)日：2011-10-11
申请号：US11796985
申请日：2007-04-30
申请人： Anup Bhalla , François Hébert , Sung-Shan Tai , Sik K Lui
发明人： Anup Bhalla , François Hébert , Sung-Shan Tai , Sik K Lui
IPC分类号： H01L29/66 , H01L21/336
CPC分类号： H01L29/7813 , H01L29/1095 , H01L29/407 , H01L29/42368 , H01L29/66734 , H01L29/7806 , H01L29/7811
摘要： This invention discloses a semiconductor power device. The trenched semiconductor power device includes a trenched gate, opened from a top surface of a semiconductor substrate, surrounded by a source region encompassed in a body region near the top surface above a drain region disposed on a bottom surface of a substrate. The semiconductor power device further includes an implanting-ion block disposed above the top surface on a mesa area next to the body region having a thickness substantially larger than 0.3 micron for blocking body implanting ions and source ions from entering into the substrate under the mesa area whereby masks for manufacturing the semiconductor power device can be reduced.
摘要翻译：本发明公开了一种半导体功率器件。沟槽半导体功率器件包括从半导体衬底的顶表面开口的沟槽栅极，被包围在设置在衬底底表面上的漏区以上的顶表面附近的体区中的源极区围绕。所述半导体功率器件还包括植入离子块，所述植入离子块设置在所述身体区域旁边的台面区域的上表面上，所述植入离子块具有基本上大于0.3微米的厚度，用于阻挡体注入离子和源离子进入台面区域从而可以减少用于制造半导体功率器件的掩模。

38. 发明授权

US07932148B2 Processes for manufacturing MOSFET devices with excessive round-hole shielded gate trench (SGT) 有权
标题翻译：用于制造具有过多圆形屏蔽栅极沟槽（SGT）的MOSFET器件的工艺
公开(公告)号：US07932148B2
公开(公告)日：2011-04-26
申请号：US12378040
申请日：2009-02-09
申请人： Hong Chang , Sung-Shan Tai , Tiesheng Li , Yu Wang
发明人： Hong Chang , Sung-Shan Tai , Tiesheng Li , Yu Wang
IPC分类号： H01L21/336
CPC分类号： H01L21/76232 , H01L29/4236 , H01L29/42376 , H01L29/66621 , H01L29/7834
摘要： This invention discloses an improved trenched metal oxide semiconductor field effect transistor (MOSFET) device that includes a trenched gate surrounded by a source region encompassed in a body region above a drain region disposed on a bottom surface of a substrate. The MOSFET cell further includes a shielded gate trench (SGT) structure below and insulated from the trenched gate. The SGT structure is formed substantially as a round hole having a lateral expansion extended beyond the trench gate and covered by a dielectric liner layer filled with a trenched gate material. The round hole is formed by an isotropic etch at the bottom of the trenched gate and is insulated from the trenched gate by an oxide insulation layer. The round hole has a lateral expansion beyond the trench walls and the lateral expansion serves as a vertical alignment landmark for controlling the depth of the trenched gate. The MOSFET device has a reduced gate to drain capacitance Cgd depending on the controllable depth of the trenched gate disposed above the SGT structure formed as a round hole below the trenched gate.
摘要翻译：本发明公开了一种改进的沟槽金属氧化物半导体场效应晶体管（MOSFET）器件，其包括被包围在设置在衬底的底表面上的漏区以上的体区中的源极区包围的沟槽栅。 MOSFET单元进一步包括屏蔽栅极沟槽（SGT）结构，并且与沟槽栅极绝缘。 SGT结构基本上形成为具有延伸超过沟槽栅极并且被填充有沟槽栅极材料的介电衬垫层覆盖的横向膨胀的圆孔。圆形孔通过在沟槽底部的各向同性蚀刻形成，并且通过氧化物绝缘层与沟槽栅极绝缘。圆孔具有超出沟槽壁的横向膨胀，并且横向膨胀用作用于控制沟槽浇口的深度的垂直对准界标。 MOSFET器件具有减小的栅极到漏极电容Cgd，这取决于设置在形成为沟槽栅极下方的圆孔的SGT结构之上的沟槽栅极的可控深度。

39. 发明授权

US07824977B2 Completely decoupled high voltage and low voltage transistor manufacturing processes 有权
标题翻译：完全去耦的高压和低压晶体管制造工艺
公开(公告)号：US07824977B2
公开(公告)日：2010-11-02
申请号：US11729408
申请日：2007-03-27
申请人： YongZhong Hu , Sung-Shan Tai
发明人： YongZhong Hu , Sung-Shan Tai
IPC分类号： H01L29/00
CPC分类号： H01L29/7322 , H01L21/823418 , H01L21/823462 , H01L21/823493 , H01L21/823814 , H01L21/823857 , H01L21/823892 , H01L27/088 , H01L27/0922 , H01L29/0878 , H01L29/42368 , H01L29/66689 , H01L29/7816
摘要： A semiconductor wafer includes at least a partially manufactured high voltage transistor covered by a high-voltage low voltage decoupling layer and at least a partially manufactured low voltage transistor with the high-voltage low-voltage decoupling layer etched off for further performance of a low-voltage manufacturing process thereon. The high-voltage low-voltage decoupling layer comprising a high temperature oxide (HTO) oxide layer of about 30-150 Angstroms and a low-pressure chemical vapor deposition (LPCVD) nitride layer.
摘要翻译：半导体晶片包括至少部分制造的由高压低电压去耦层覆盖的高压晶体管和至少部分制造的低压晶体管，其中蚀刻掉高压低压去耦层，电压制造工艺。包括约30-150埃的高温氧化物（HTO）氧化物层和低压化学气相沉积（LPCVD）氮化物层的高压低电压去耦层。

40. 发明授权

US07805687B2 One-time programmable (OTP) memory cell 有权
标题翻译：一次性可编程（OTP）存储单元
公开(公告)号：US07805687B2
公开(公告)日：2010-09-28
申请号：US11541369
申请日：2006-09-30
申请人： YongZhong Hu , Yu Cheng Chang , Sung-Shan Tai
发明人： YongZhong Hu , Yu Cheng Chang , Sung-Shan Tai
IPC分类号： G06F17/50
CPC分类号： G11C17/16 , G11C17/18 , H01L27/112 , H01L27/11206
摘要： A method of performing a programming, testing and trimming operation is disclosed in this invention. The method includes a step of applying a programming circuit for programming an OTP memory for probing and sensing one of three different states of the OTP memory for carrying out a trimming operation using one of the three states of the OTP memory whereby a higher utilization of OTP memory cells is achieved. Selecting and programming two conductive circuits of the OTP into two different operational characteristics thus enables the storing and sensing one of the three different states of the OTP memory. These two conductive circuits may include two different transistors for programming into a linear resistor and a nonlinear resistor with different current conducting characteristics. The programming processes include application of a high voltage and different programming currents thus generating different operational characteristics of these two transistors.
摘要翻译：在本发明中公开了执行编程，测试和修整操作的方法。该方法包括应用用于对OTP存储器进行编程的编程电路的步骤，用于探测和感测OTP存储器的三种不同状态之一，以使用OTP存储器的三种状态之一进行修整操作，由此OTP的较高利用率实现了存储单元。将OTP的两个导电电路选择和编程成两个不同的操作特性，因此能够存储和感测OTP存储器的三种不同状态之一。这两个导电电路可以包括用于编程成线性电阻器的两个不同晶体管和具有不同电流传导特性的非线性电阻器。编程过程包括应用高电压和不同的编程电流，从而产生这两个晶体管的不同操作特性。

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