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1. 发明授权

US08022482B2 Device configuration of asymmetrical DMOSFET with schottky barrier source 有权
标题翻译：具有肖特基势垒源的非对称DMOSFET的器件配置
公开(公告)号：US08022482B2
公开(公告)日：2011-09-20
申请号：US11355128
申请日：2006-02-14
申请人： Yongzhong Hu , Sung-Shan Tai
发明人： Yongzhong Hu , Sung-Shan Tai
IPC分类号： H01L27/108 , H01L29/94 , H01L21/08 , H01L27/088 , H01L29/40 , H01L23/12 , H01L23/48 , H01L23/52 , H01L29/417 , H01L29/45 , H01L29/78 , H01L29/812
CPC分类号： H01L29/7813 , H01L21/28518 , H01L21/823418 , H01L29/41766 , H01L29/456 , H01L29/665 , H01L29/66507 , H01L29/66727 , H01L29/66734 , H01L29/7806 , H01L29/7839 , H01L29/7845 , H01L2924/0002 , H01L2924/00 , H01L2924/1082
摘要： A trenched semiconductor power device includes a trenched gate insulated by a gate insulation layer and surrounded by a source region encompassed in a body region above a drain region disposed on a bottom surface of a semiconductor substrate. The source region surrounding the trenched gate includes a metal of low barrier height to function as a Schottky source. The metal of low barrier height further may include a PtSi or ErSi layer. In a preferred embodiment, the metal of low barrier height further includes an ErSi layer. The metal of low barrier height further may be a metal silicide layer having the low barrier height. A top oxide layer is disposed under a silicon nitride spacer on top of the trenched gate for insulating the trenched gate from the source region. A source contact disposed in a trench opened into the body region for contacting a body-contact dopant region and covering with a conductive metal layer such as a Ti/TiN layer. In a preferred embodiment, the semiconductor power device constitutes an asymmetrical double diffusion metal oxide semiconductor field effect transistor (DMOSFET) device.
摘要翻译：沟槽半导体功率器件包括由栅极绝缘层绝缘并被包围在设置在半导体衬底的底表面上的漏极区域上方的体区中的源极区包围的沟槽栅极。围绕沟槽栅极的源极区域包括具有低势垒高度的金属，用作肖特基源。低阻挡高度的金属还可以包括PtSi或ErSi层。在优选实施例中，低势垒高度的金属还包括ErSi层。低势垒高度的金属还可以是具有低势垒高度的金属硅化物层。顶部氧化物层设置在沟槽栅极顶部的氮化硅间隔物下方，用于使沟槽栅极与源极区域绝缘。源极接触件，设置在沟槽内，开口到体区，用于接触体接触掺杂区域并用诸如Ti / TiN层的导电金属层覆盖。在优选实施例中，半导体功率器件构成非对称双扩散金属氧化物半导体场效应晶体管（DMOSFET）器件。

2. 发明申请

US20120083084A1 Method of fabrication and device configuration of asymmetrical DMOSFET with schottky barrier source 审中-公开
标题翻译：具有肖特基势垒源的非对称DMOSFET的制造方法和器件配置
公开(公告)号：US20120083084A1
公开(公告)日：2012-04-05
申请号：US13199795
申请日：2011-09-08
申请人： Yongzhong Hu , Sung-Shan Tai
发明人： Yongzhong Hu , Sung-Shan Tai
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L21/28518 , H01L21/823418 , H01L29/41766 , H01L29/456 , H01L29/665 , H01L29/66507 , H01L29/66727 , H01L29/66734 , H01L29/7806 , H01L29/7839 , H01L29/7845 , H01L2924/0002 , H01L2924/00 , H01L2924/1082
摘要： A trenched semiconductor power device includes a trenched gate insulated by a gate insulation layer and surrounded by a source region encompassed in a body region above a drain region disposed on a bottom surface of a semiconductor substrate. The source region surrounding the trenched gate includes a metal of low barrier height to function as a Schottky source and that may include a PtSi, ErSi layer and may be a metal silicide layer having the low barrier height. A top oxide layer is disposed under a silicon nitride spacer on top of the trenched gate for insulating the trenched gate from the source region. A source contact disposed in a trench opened into the body region for contacting a body-contact dopant region and covering with a conductive metal layer such as a Ti/TiN layer.
摘要翻译：沟槽半导体功率器件包括由栅极绝缘层绝缘并被包围在设置在半导体衬底的底表面上的漏极区域上方的体区中的源极区包围的沟槽栅极。围绕沟槽栅极的源极区域包括低势垒高度的金属，用作肖特基源，并且可以包括PtSi，ErSi层，并且可以是具有低势垒高度的金属硅化物层。顶部氧化物层设置在沟槽栅极顶部的氮化硅间隔物下方，用于使沟槽栅极与源极区域绝缘。源极接触件，设置在沟槽内，开口到体区，用于接触体接触掺杂区域并用诸如Ti / TiN层的导电金属层覆盖。

3. 发明授权

US08105905B2 Configuration and method to form MOSFET devices with low resistance silicide gate and mesa contact regions 有权
标题翻译：用于形成具有低电阻硅化物栅极和台面接触区域的MOSFET器件的配置和方法
公开(公告)号：US08105905B2
公开(公告)日：2012-01-31
申请号：US12927177
申请日：2010-11-08
申请人： Yongzhong Hu , Sung-Shan Tai
发明人： Yongzhong Hu , Sung-Shan Tai
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L29/456 , H01L29/4933 , H01L29/66719 , H01L29/66734
摘要： A novel integration scheme for forming power MOSFET, particularly forming salicides for both gate and mesa contact regions, as well as using multiple energy contact implants through the salicided layer to form conductive body contacts which short to the source region by the salicides.
摘要翻译：一种用于形成功率MOSFET的新型集成方案，特别是形成栅极和台面接触区域的杀螨剂，以及通过浸渍层使用多个能量接触植入物，以形成导电体接触物，其通过杀螨剂与源区域短接。

4. 发明申请

US20110124167A1 Configuration and method to form MOSFET devices with low resistance silicide gate and mesa contact regions 有权
标题翻译：用于形成具有低电阻硅化物栅极和台面接触区域的MOSFET器件的配置和方法
公开(公告)号：US20110124167A1
公开(公告)日：2011-05-26
申请号：US12927177
申请日：2010-11-08
申请人： Yongzhong Hu , Sung-Shan Tai
发明人： Yongzhong Hu , Sung-Shan Tai
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L29/456 , H01L29/4933 , H01L29/66719 , H01L29/66734
摘要： A novel integration scheme for forming power MOSFET, particularly forming salicides for both gate and mesa contact regions, as well as using multiple energy contact implants through the salicided layer to form conductive body contacts which short to the source region by the salicides.
摘要翻译：一种用于形成功率MOSFET的新型集成方案，特别是形成栅极和台面接触区域的杀螨剂，以及通过浸渍层使用多个能量接触植入物，以形成导电体接触物，其通过杀螨剂与源极区域短接触。

5. 发明授权

US07256446B2 One time programmable memory cell 有权
标题翻译：一次可编程存储单元
公开(公告)号：US07256446B2
公开(公告)日：2007-08-14
申请号：US11122848
申请日：2005-05-05
申请人： Yongzhong Hu , Sung-Shan Tai
发明人： Yongzhong Hu , Sung-Shan Tai
IPC分类号： H01L29/788
CPC分类号： G11C17/16 , G11C17/18 , H01L27/112 , H01L27/11206
摘要： This invention discloses a one-time programmable (OTP) memory cell. The OTP memory cell includes a dielectric layer disposed between two conductive polysilicon segments wherein the dielectric layer is ready to change from a non-conductive state to a conductive state through an induced voltage breakdown. In a preferred embodiment, one of the conductive polysilicon segments further includes an etch undercut configuration for conveniently inducing the voltage breakdown in the dielectric layer. In a preferred embodiment, the dielectric layer is further formed as sidewalls covering the edges and corners of a first polysilicon segments to conveniently induce a voltage breakdown in the dielectric layer by the edge and corner electrical field effects.
摘要翻译：本发明公开了一种可编程（OTP）存储单元。 OTP存储单元包括设置在两个导电多晶硅段之间的电介质层，其中介电层准备好通过感应电压击穿从非导电状态改变到导通状态。在优选实施例中，导电多晶硅段中的一个还包括蚀刻底切配置，用于方便地引起电介质层中的电压击穿。在优选实施例中，电介质层还被形成为覆盖第一多晶硅段的边缘和角部的侧壁，以便通过边缘和拐角电场效应方便地引起电介质层中的电压击穿。

6. 发明申请

US20070170498A1 Configuration and method to form mosfet devices with low resistance silicide gate and mesa contact regions 有权
标题翻译：用于形成具有低电阻硅化物栅极和台面接触区域的mosfet器件的配置和方法
公开(公告)号：US20070170498A1
公开(公告)日：2007-07-26
申请号：US11338019
申请日：2006-01-24
申请人： Yongzhong Hu , Sung-Shan Tai
发明人： Yongzhong Hu , Sung-Shan Tai
IPC分类号： H01L29/94
CPC分类号： H01L29/7813 , H01L29/456 , H01L29/4933 , H01L29/66719 , H01L29/66734
摘要： A novel integration scheme for forming power MOSFET, particularly forming salicides for both gate and mesa contact regions, as well as using multiple energy contact implants through the salicided layer to form conductive body contacts which short to the source region by the salicides.
摘要翻译：一种用于形成功率MOSFET的新型集成方案，特别是形成栅极和台面接触区域的杀螨剂，以及通过浸渍层使用多个能量接触植入物，以形成导电体接触物，其通过杀螨剂与源区域短接。

7. 发明授权

US09337329B2 Method of fabrication and device configuration of asymmetrical DMOSFET with schottky barrier source 有权
标题翻译：具有肖特基势垒源的非对称DMOSFET的制造方法和器件配置
公开(公告)号：US09337329B2
公开(公告)日：2016-05-10
申请号：US13199795
申请日：2011-09-08
申请人： Yongzhong Hu , Sung-Shan Tai
发明人： Yongzhong Hu , Sung-Shan Tai
IPC分类号： H01L21/8234 , H01L29/78 , H01L29/66 , H01L21/285 , H01L29/417 , H01L29/45
CPC分类号： H01L29/7813 , H01L21/28518 , H01L21/823418 , H01L29/41766 , H01L29/456 , H01L29/665 , H01L29/66507 , H01L29/66727 , H01L29/66734 , H01L29/7806 , H01L29/7839 , H01L29/7845 , H01L2924/0002 , H01L2924/00 , H01L2924/1082
摘要： A trenched semiconductor power device includes a trenched gate insulated by a gate insulation layer and surrounded by a source region encompassed in a body region above a drain region disposed on a bottom surface of a semiconductor substrate. The source region surrounding the trenched gate includes a metal of low barrier height to function as a Schottky source and that may include a PtSi, ErSi layer and may further be a metal silicide layer having the low barrier height. A top oxide layer is disposed under a silicon nitride spacer on top of the trenched gate for insulating the trenched gate from the source region. A source contact disposed in a trench opened into the body region for contacting a body-contact dopant region and covering with a conductive metal layer such as a Ti/TiN layer.
摘要翻译：沟槽半导体功率器件包括由栅极绝缘层绝缘并被包围在设置在半导体衬底的底表面上的漏极区域上方的体区中的源极区包围的沟槽栅极。围绕沟槽栅极的源极区域包括低势垒高度的金属，用作肖特基源并且可以包括PtSi，ErSi层，并且还可以是具有低势垒高度的金属硅化物层。顶部氧化物层设置在沟槽栅极顶部的氮化硅间隔物下方，用于使沟槽栅极与源极区域绝缘。源极接触件，设置在沟槽内，开口到体区，用于接触体接触掺杂区域并用诸如Ti / TiN层的导电金属层覆盖。

8. 发明授权

US07829941B2 Configuration and method to form MOSFET devices with low resistance silicide gate and mesa contact regions 有权
标题翻译：用于形成具有低电阻硅化物栅极和台面接触区域的MOSFET器件的配置和方法
公开(公告)号：US07829941B2
公开(公告)日：2010-11-09
申请号：US11338019
申请日：2006-01-24
申请人： Yongzhong Hu , Sung-Shan Tai
发明人： Yongzhong Hu , Sung-Shan Tai
IPC分类号： H01L29/66
CPC分类号： H01L29/7813 , H01L29/456 , H01L29/4933 , H01L29/66719 , H01L29/66734
摘要： A novel integration scheme for forming power MOSFET, particularly forming salicides for both gate and mesa contact regions, as well as using multiple energy contact implants through the salicided layer to form conductive body contacts which short to the source region by the salicides.
摘要翻译：一种用于形成功率MOSFET的新型集成方案，特别是形成栅极和台面接触区域的杀螨剂，以及通过浸渍层使用多个能量接触植入物，以形成导电体接触物，其通过杀螨剂与源区域短接。

9. 发明申请

US20100015770A1 Double gate manufactured with locos techniques 审中-公开
标题翻译：双门使用locos技术制造
公开(公告)号：US20100015770A1
公开(公告)日：2010-01-21
申请号：US12586257
申请日：2009-09-18
申请人： Sung-Shan Tai , Yongzhong Hu
发明人： Sung-Shan Tai , Yongzhong Hu
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L29/407 , H01L29/42368 , H01L29/66734
摘要： This invention discloses a method for manufacturing a trenched semiconductor power device that includes step of opening a trench in a semiconductor substrate. The method further includes a step of opening a top portion of the trench first then depositing a SiN on sidewalls of the top portion followed by etching a bottom surface of the top portion of the trench then silicon etching to open a bottom portion of the trench with a slightly smaller width than the top portion of the trench. The method further includes a step of growing a thick oxide layer along sidewalls of the bottom portion of the trench thus forming a bird-beak shaped layer at an interface point between the top portion and bottom portion of the trench.
摘要翻译：本发明公开了一种制造沟槽半导体功率器件的方法，包括在半导体衬底中打开沟槽的步骤。该方法还包括首先打开沟槽顶部的步骤，然后在顶部的侧壁上沉积SiN，随后蚀刻沟槽顶部的底部表面，然后进行硅蚀刻以打开沟槽的底部部分，比沟槽的顶部稍小的宽度。该方法还包括沿着沟槽底部的侧壁生长厚氧化物层的步骤，从而在沟槽的顶部和底部之间的界面处形成鸟嘴形层。

10. 发明申请

US20060249791A1 One time programmable memory cell 有权
标题翻译：一次可编程存储单元
公开(公告)号：US20060249791A1
公开(公告)日：2006-11-09
申请号：US11122848
申请日：2005-05-05
申请人： Yongzhong Hu , Sung-Shan Tai
发明人： Yongzhong Hu , Sung-Shan Tai
IPC分类号： H01L23/62
CPC分类号： G11C17/16 , G11C17/18 , H01L27/112 , H01L27/11206
摘要： This invention discloses a one-time programmable (OTP) memory cell. The OTP memory cell includes a dielectric layer disposed between two conductive polysilicon segments wherein the dielectric layer is ready to change from a non-conductive state to a conductive state through an induced voltage breakdown. In a preferred embodiment, one of the conductive polysilicon segments further includes an etch undercut configuration for conveniently inducing the voltage breakdown in the dielectric layer. In a preferred embodiment, the dielectric layer is further formed as sidewalls covering the edges and corners of a first polysilicon segments to conveniently induce a voltage breakdown in the dielectric layer by the edge and corner electrical field effects.
摘要翻译：本发明公开了一种可编程（OTP）存储单元。 OTP存储单元包括设置在两个导电多晶硅段之间的电介质层，其中介电层准备好通过感应电压击穿从非导电状态改变到导通状态。在优选实施例中，导电多晶硅段中的一个还包括蚀刻底切配置，用于方便地引起电介质层中的电压击穿。在优选实施例中，电介质层还被形成为覆盖第一多晶硅段的边缘和角部的侧壁，以便通过边缘和拐角电场效应方便地引起电介质层中的电压击穿。

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