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31. 发明申请

US20130027051A1 NONCONTACT ELECTRICAL TESTING WITH OPTICAL TECHNIQUES 失效
标题翻译：非接触式电气测试与光学技术
公开(公告)号：US20130027051A1
公开(公告)日：2013-01-31
申请号：US13191555
申请日：2011-07-27
申请人： Xu Ouyang , Tso-Hui Ting , Ping-Chuan Wang , Yongchun Xin
发明人： Xu Ouyang , Tso-Hui Ting , Ping-Chuan Wang , Yongchun Xin
IPC分类号： G01R31/3187
CPC分类号： G01R31/31728
摘要： An on-chip technique for noncontact electrical testing of a test structure on a chip is provided. On-chip photodiodes receives pump light from a pump light source, where the on-chip photodiodes are electrically connected to the test structure and are configured to generate power for the test structure. An on-chip coupling unit receives probe light from a probe light source, where the on-chip coupling unit is optically connected to on-chip waveguides through which the probe light is transferred. On-chip switches open in response to receiving voltage output from the test structure, and the on-chip switches remain closed when the voltage output is not received from the test structure. The on-chip switches pass the probe light when opened by the voltage output from the test structure. The on-chip switches block the probe light by remaining closed, when the voltage output is not received from the test structure.
摘要翻译：提供了芯片上测试结构的非接触电测试的片上技术。片上光电二极管从泵浦光源接收泵浦光，其中片上光电二极管电连接到测试结构，并且被配置为产生用于测试结构的电力。片上耦合单元接收来自探针光源的探测光，其中片上耦合单元光学连接到传输探针光的片上波导。响应于测试结构的接收电压输出，片内开关打开，并且当没有从测试结构接收到电压输出时，片上开关保持闭合。当由测试结构输出的电压打开时，片上开关通过探测灯。当没有从测试结构接收到电压输出时，片内开关通过保持关闭来阻止探测光。

32. 发明授权

US08294485B2 Detecting asymmetrical transistor leakage defects 有权
标题翻译：检测不对称晶体管漏电缺陷
公开(公告)号：US08294485B2
公开(公告)日：2012-10-23
申请号：US12699211
申请日：2010-02-03
申请人： Xu Ouyang , Yun-Yu Wang , Yunsheng Song
发明人： Xu Ouyang , Yun-Yu Wang , Yunsheng Song
IPC分类号： G01R31/02 , G01R31/08
CPC分类号： H01L27/1104 , G11C11/41 , G11C29/50 , G11C2029/5006 , H01L22/34 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A method of detecting low-probability defects in large transistor arrays (such as large arrays of SRAM cells), where the defects manifest themselves as asymmetrical leakage in a transistor (such as a pulldown nFET in an SRAM cell). These defects are detected by creating one or more test arrays, identical in all regards to the large transistor arrays up until the contact and metallization layers. Leakage is measured by applying an appropriate off-state voltage (e.g., 0V) by a common connection to all of the gates of the transistors in the test array, then measuring the aggregate drain/source leakage current, both forward and reverse (e.g., first grounded source and positively biased drain, then grounded drain and positively biased source) comparing the difference between the two leakage current measurements.
摘要翻译：检测大晶体管阵列（例如大量SRAM单元阵列）中的低概率缺陷的方法，其中缺陷在晶体管（例如，SRAM单元中的下拉nFET）中表现为非对称泄漏。通过创建一个或多个测试阵列来检测这些缺陷，所有这些测试阵列在大量晶体管阵列上相同，直到接触和金属化层。通过与测试阵列中的晶体管的所有栅极的公共连接施加适当的截止状态电压（例如，0V）来测量泄漏，然后测量正向和反向的汇总漏极/漏极电流（例如，第一接地源和正偏置漏极，然后接地漏极和正偏置源）比较两个漏电流测量值之间的差异。

33. 发明申请

US20120232686A1 WAFER ALIGNMENT SYSTEM WITH OPTICAL COHERENCE TOMOGRAPHY 失效
标题翻译：具有光学相干坐标的波形对准系统
公开(公告)号：US20120232686A1
公开(公告)日：2012-09-13
申请号：US13042494
申请日：2011-03-08
申请人： Yongchun Xin , Xu Ouyang , Yunsheng Song , Tso-Hui Ting
发明人： Yongchun Xin , Xu Ouyang , Yunsheng Song , Tso-Hui Ting
IPC分类号： G05D3/00 , G06F15/00 , G01B9/02
CPC分类号： H01L21/681 , G01B9/02091 , H01L23/544 , H01L24/75 , H01L24/81 , H01L24/94 , H01L2223/5442 , H01L2223/54426 , H01L2223/54453 , H01L2224/75753 , H01L2224/8113 , H01L2224/81132 , H01L2224/81191 , H01L2224/94 , H01L2224/81
摘要： A system for performing alignment of two wafers is disclosed. The system comprises an optical coherence tomography system and a wafer alignment system. The wafer alignment system is configured and disposed to control the relative position of a first wafer and a second wafer. The optical coherence tomography system is configured and disposed to compute coordinate data for a plurality of alignment marks on the first wafer and second wafer, and send that coordinate data to the wafer alignment system
摘要翻译：公开了一种用于执行两个晶片对准的系统。该系统包括光学相干断层摄影系统和晶片对准系统。晶片对准系统被配置和设置以控制第一晶片和第二晶片的相对位置。光学相干断层摄影系统被配置和设置为计算第一晶片和第二晶片上的多个对准标记的坐标数据，并将该坐标数据发送到晶片对准系统

34. 发明申请

US20120192137A1 PLACEMENT AND OPTIMIZATION OF PROCESS DUMMY CELLS 有权
标题翻译：放置和优化过程细胞
公开(公告)号：US20120192137A1
公开(公告)日：2012-07-26
申请号：US13435795
申请日：2012-03-30
申请人： Xu Ouyang , Geng Han , Lars W. Liebmann
发明人： Xu Ouyang , Geng Han , Lars W. Liebmann
IPC分类号： G06F17/50
CPC分类号： G11C29/24 , G06F2217/12 , G11C5/02 , H01L27/0203 , H01L27/105 , Y02P90/265
摘要： A method for laying out process dummy cells in relationship to inside memory cells of a memory array includes (a) calculating an initial process performance parameter for the memory array; (b) changing dummy cell layout configuration for a layer electrically connected to inside cells; (c) applying lithographic simulation and yield model for both the inside memory cells and the changed layout configuration process dummy cells; and (d) repeating steps (b) and (c) until yield is maximized. Checks may be performed to ensure that there is enough room to make the change and that there is no significant adverse effect to neighboring circuits. The process performance parameter may be yield or a process window for the inside memory cells.
摘要翻译：与存储器阵列的内部存储单元相关地布置处理虚设单元的方法包括：（a）计算存储器阵列的初始处理性能参数; （b）改变电连接到内部单元的层的虚拟单元布局配置; （c）为内部存储单元和改变的布局配置处理虚拟单元应用光刻模拟和屈服模型; 和（d）重复步骤（b）和（c），直到产率最大化。可以进行检查，以确保有足够的空间进行更改，并且对相邻电路没有明显的不利影响。过程性能参数可以是产量或内部存储器单元的处理窗口。

35. 发明授权

US07676775B2 Method to determine the root causes of failure patterns by using spatial correlation of tester data 失效
标题翻译：通过使用测试仪数据的空间相关性确定故障模式的根本原因的方法
公开(公告)号：US07676775B2
公开(公告)日：2010-03-09
申请号：US11754947
申请日：2007-05-29
申请人： Howard Chen , Katherine V. Hawkins , Fook-Luen Heng , Louis Hsu , Xu Ouyang
发明人： Howard Chen , Katherine V. Hawkins , Fook-Luen Heng , Louis Hsu , Xu Ouyang
IPC分类号： G06F17/50
CPC分类号： G01R31/2894 , G01R31/31718 , G01R31/318314 , G11C29/10 , G11C29/56 , G11C29/56008
摘要： A method for determining the root causes of fail patterns in integrated circuit chips is provide wherein a known integrated circuit chip layout is used to identify a plurality of potential defects and a plurality of potential fail patterns in the integrated circuit chip. Correlations between the potential defects and the potential fail patterns that result from those defects are identified. Based on this identification, the potential fail patterns are grouped by common potential defect. An actual integrated circuit chip that is manufactured in accordance with the test layout is tested for failure patterns. These failure patterns are then compared to the groupings of potential fail patterns. When a match is found, that is when a given group of fail patterns is found in the actual integrated circuit chip, then the potential defect associated with the potential fail patterns to which the actual fail patterns are matched is identified. This defect is the root cause of the failure pattern in the actual chip.
摘要翻译：提供了一种用于确定集成电路芯片中的故障模式的根本原因的方法，其中使用已知的集成电路芯片布局来识别集成电路芯片中的多个潜在缺陷和多个潜在故障模式。鉴定出潜在缺陷与由这些缺陷产生的潜在失效模式之间的相关性。基于此识别，潜在的故障模式由共同的潜在缺陷分组。测试根据测试布局制造的实际集成电路芯片的故障模式。然后将这些故障模式与潜在故障模式的分组进行比较。当发现匹配时，即在实际的集成电路芯片中发现给定的一组故障模式时，识别与实际故障模式匹配的潜在故障模式相关联的潜在缺陷。这个缺陷是实际芯片中故障模式的根本原因。

36. 发明申请

US20090319074A1 METHOD FOR COMPENSATING FOR TOOL PROCESSING VARIATION IN THE ROUTING OF WAFERS/LOTS 失效
标题翻译：用于补偿在WAFERS / LOTS路由中工具处理变化的方法
公开(公告)号：US20090319074A1
公开(公告)日：2009-12-24
申请号：US12144093
申请日：2008-06-23
申请人： Keith Kwong Hon Wong , Xu Ouyang , Yunsheng Song
发明人： Keith Kwong Hon Wong , Xu Ouyang , Yunsheng Song
IPC分类号： G06F19/00
CPC分类号： H01L22/20 , H01L22/12
摘要： A method for increasing overall yield in semiconductor manufacturing including routing wafers or wafer lots from tool to tool in a manner which at least partially neutralizes or compensates for processing variations. A system for increasing overall yield in semiconductor manufacturing includes a module for recording processing data from plural first and second types of tools and a module for routing wafers or wafer lots from tools of the first type of tools to tools of the second type of tools so as to at least partially neutralizes or compensate for processing variation.
摘要翻译：一种用于提高半导体制造中的总产量的方法，包括以至少部分中和或补偿处理变化的方式从工具到工具路由晶圆或晶片批次。用于提高半导体制造中的整体产量的系统包括用于记录来自多个第一和第二类型工具的处理数据的模块和用于将晶片或晶片批次从第一类型工具的工具转移到第二类型工具的工具的模块，至少部分地中和或补偿处理变化。

37. 发明申请

US20090306807A1 MULTIDIMENSIONAL PROCESS WINDOW OPTIMIZATION IN SEMICONDUCTOR MANUFACTURING 有权
标题翻译：半导体制造中的多维处理窗优化
公开(公告)号：US20090306807A1
公开(公告)日：2009-12-10
申请号：US12135522
申请日：2008-06-09
申请人： Yunsheng Song , Xu Ouyang , James P. Rice
发明人： Yunsheng Song , Xu Ouyang , James P. Rice
IPC分类号： G06F19/00
CPC分类号： H01L22/20 , H01L22/12
摘要： A method for optimizing multiple process windows in a semiconductor manufacturing process is disclosed. The message comprises performing dependent variable composition on a plurality of dependent variables. Metrology data is joined with the dependent variables, and then a partial least squares regression is performed on the joined data set to obtain a prediction equation, and a variable importance prediction for each process window in a process window set. A set of product limited yield are derived, and the process window set is adjusted, and the yields recalculated, until an optimal process window set is derived.
摘要翻译：公开了一种在半导体制造工艺中优化多个工艺窗口的方法。该消息包括在多个因变量上执行从属变量组合。计量学数据与因变量相连，然后对连接的数据集执行偏最小二乘回归，以获得预测方程，并对过程窗口集中的每个过程窗口进行可变重要度预测。导出一组产品有限收益，并调整过程窗口集合，并重新计算收益，直到导出最优过程窗口集合。

38. 发明授权

US07515502B1 Memory array peripheral structures and use 失效
标题翻译：内存阵列外设结构和使用
公开(公告)号：US07515502B1
公开(公告)日：2009-04-07
申请号：US11856964
申请日：2007-09-18
申请人： Ishtiaq Ahsan , Louis Lu-Chen Hsu , Xu Ouyang
发明人： Ishtiaq Ahsan , Louis Lu-Chen Hsu , Xu Ouyang
IPC分类号： G11C8/00
CPC分类号： G11C8/08 , G11C5/02 , G11C5/06 , G11C29/006 , G11C29/24 , G11C29/48 , G11C29/808 , G11C29/816 , G11C29/838
摘要： A method for using photolithographic dummy memory cells arranged in rings around a set of primary memory cells as test structures and as redundant memory cells. Also circuits and structures of memory arrays having multiple-use dummy memory cells.
摘要翻译：一种使用设置在作为测试结构的一组主存储器单元周围的环的光刻虚拟存储单元的方法和作为冗余存储单元的方法。还有具有多次使用的虚拟存储器单元的存储器阵列的电路和结构。

39. 发明申请

US20080286888A1 TEST STRUCTURES AND METHODOLOGY FOR DETECTING HOT DEFECTS 审中-公开
标题翻译：用于检测热缺陷的测试结构和方法
公开(公告)号：US20080286888A1
公开(公告)日：2008-11-20
申请号：US11750364
申请日：2007-05-18
申请人： Louis Lu-Chen Hsu , Byeong Yeol Kim , Xu Ouyang
发明人： Louis Lu-Chen Hsu , Byeong Yeol Kim , Xu Ouyang
IPC分类号： H01L21/66 , H01L23/58
CPC分类号： H01L22/12 , H01L2924/0002 , H01L2924/00
摘要： Test structures for detecting defects arising from hybrid orientation technology (HOT) through detection of device leakage (gate leakage, junction leakage, and sub-threshold leakage), having at least one active region disposed in a re-grown region of a substrate: a layer of oxide; a layer of poly. Some test structures are dog-bone shaped test structure, tower shaped test structure, and inside-hole shaped. A method for detecting HOT defects involves measuring defect size and location in terms of device leakage, such as gate leakage, junction leakage, and sub-threshold leakage. HOT edge defect density and edge defect size distribution may be calculated, and the resulting defect information may be used to calibrate a defect yield model.
摘要翻译：用于通过检测器件泄漏（栅极泄漏，结漏电和次阈值泄漏）检测由混合取向技术（HOT）产生的缺陷的测试结构，其具有设置在衬底的再生长区域中的至少一个有源区：氧化层; 一层聚一些测试结构是狗骨形测试结构，塔形测试结构和内孔形状。用于检测HOT缺陷的方法包括根据器件泄漏测量缺陷尺寸和位置，例如栅极泄漏，结漏电和次阈值泄漏。可以计算HOT边缘缺陷密度和边缘缺陷尺寸分布，并且所得到的缺陷信息可以用于校准缺陷产量模型。

40. 发明授权

US07405880B2 Multilayer optical filter 有权
标题翻译：多层光学滤波器
公开(公告)号：US07405880B2
公开(公告)日：2008-07-29
申请号：US10842869
申请日：2004-05-10
申请人： Anguel N. Nikolov , Jian Jim Wang , Xu Ouyang , Feng Liu , Jiangdong Deng , Xuegong Deng , Greg E. Blonder , Ronnie Paul Varghese
发明人： Anguel N. Nikolov , Jian Jim Wang , Xu Ouyang , Feng Liu , Jiangdong Deng , Xuegong Deng , Greg E. Blonder , Ronnie Paul Varghese
IPC分类号： F21V9/04 , G02B5/28
CPC分类号： G02B5/285
摘要： In one aspect, the invention features articles that include a substrate having a first surface and a second surface contiguous with the first surface. The first and second surfaces are non-coplanar. A first multilayer film is disposed on the first surface. A second multilayer film is disposed on the second surface. The second multilayer film is contiguous with the first multilayer film.
摘要翻译：在一个方面，本发明的特征在于包括具有第一表面和与第一表面邻接的第二表面的基底的制品。第一和第二表面是非共面的。第一多层膜设置在第一表面上。第二多层膜设置在第二表面上。第二多层膜与第一多层膜邻接。

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