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31. 发明授权

US06949404B1 Flip chip package with warpage control 有权
标题翻译：倒装芯片封装具有翘曲控制
公开(公告)号：US06949404B1
公开(公告)日：2005-09-27
申请号：US10305671
申请日：2002-11-25
申请人： Don Fritz , Wen-chou Vincent Wang , Yuan Li
发明人： Don Fritz , Wen-chou Vincent Wang , Yuan Li
IPC分类号： H01L21/44 , H01L21/48 , H01L21/50 , H01L23/367
CPC分类号： H01L23/3675 , H01L21/50 , H01L2224/16 , H01L2224/73253 , H01L2924/01012 , H01L2924/01019 , H01L2924/0102 , H01L2924/01322 , H01L2924/10253 , H01L2924/15311 , H01L2924/16152 , H01L2924/16195 , H01L2924/351 , H01L2924/3511 , H01L2924/00
摘要： Provided are a semiconductor flip chip package with warpage control and fabrication methods for such packages. The packages of the present invention include heat spreader lids that are rigidly attached to the die or packaging substrate with a bond that can withstand the considerable bowing pressures caused by the CTE mismatch between the die and substrate. The result is a package with less bowing and so improved co-planarity (in compliance with industry specifications) with the PCB board to which it is ultimately bound. Package reliability is thereby also enhanced, particularly for large die sizes.
摘要翻译：提供了一种用于这种封装的翘曲控制和制造方法的半导体倒装芯片封装。本发明的包装包括散热器盖子，该散热器盖子具有可以承受由模具和基板之间的CTE不匹配引起的相当大的弯曲压力的粘合件刚性地附接到模具或包装基板。结果是与其最终绑定的PCB板相比，具有较少弯曲度和改善的共平面性（符合行业规范）的封装。因此，包装可靠性也得到提高，特别是对于大型模具尺寸。

32. 发明授权

US5656414A Methods of forming tall, high-aspect ratio vias and trenches in photo-imageable materials, photoresist materials, and the like 失效
标题翻译：在光可成像材料，光致抗蚀剂材料等中形成高，高纵横比通孔和沟槽的方法
公开(公告)号：US5656414A
公开(公告)日：1997-08-12
申请号：US52639
申请日：1993-04-23
申请人： William Tai-Hua Chou , Wen-chou Vincent Wang
发明人： William Tai-Hua Chou , Wen-chou Vincent Wang
IPC分类号： G03F7/038 , G03F7/039 , G03F7/095 , G03F7/20 , G03F7/26 , H01L21/027 , H01L23/29 , H01L23/31 , G03C5/00
CPC分类号： G03F7/095 , G03F7/2022
摘要： Simple and cost-effective methods for forming tall, high-aspect ratio structures in a material layer comprising a first layer of a image-reversal-type photo-sensitive material and a second layer of a positive-type photo-sensitive material is disclosed. The layers are formed, exposed to actinic radiation, and developed such that the formation, exposure, and development of the second layer does not substantially modify or destroy the patterns formed in the first layer. In one embodiment, the first layer is exposed to actinic radiation through a first mask comprising the complimentary image, or negative, of a desired high-aspect ratio structure. The image in the first layer is then reversed by heating to an elevated temperature and subsequently blank flood exposure of actinic radiation. A second layer of a positive type photo-sensitive material chemically compatible with the IRP layer is then formed over the first layer. The second layer is exposed to actinic radiation through a second mask comprising the positive image of the desired structure. Both layers are exposed to a developer solution to remove material from the layers, thereby completing the formation of the desired structure.
摘要翻译：公开了一种用于在包括图像反转型光敏材料的第一层和正型感光材料的第二层的材料层中形成高的高纵横比结构的简单和成本有效的方法。形成这些层，暴露于光化辐射，并显影，使得第二层的形成，曝光和显影基本上不改变或破坏在第一层中形成的图案。在一个实施方案中，第一层通过包含所需高纵横比结构的互补图像或负片的第一掩模暴露于光化辐射。然后将第一层中的图像加热到升高的温度并随后空白的光化辐射暴露。然后在第一层上形成与IRP层化学相容的正型感光材料的第二层。第二层通过包含所需结构的正像的第二掩模曝光于光化辐射。将这两层暴露于显影剂溶液以从层中去除材料，从而完成所需结构的形成。

33. 发明授权

US06669801B2 Device transfer method 有权
公开(公告)号：US06669801B2
公开(公告)日：2003-12-30
申请号：US09853353
申请日：2001-05-09
申请人： Tetsuzo Yoshimura , James Roman , Wen-chou Vincent Wang , Masaaki Inao , Mark Thomas McCormack
发明人： Tetsuzo Yoshimura , James Roman , Wen-chou Vincent Wang , Masaaki Inao , Mark Thomas McCormack
IPC分类号： B32B3100
CPC分类号： H01L24/73 , H01L21/568 , H01L21/6835 , H01L24/24 , H01L24/82 , H01L2221/68359 , H01L2221/68368 , H01L2224/04105 , H01L2224/05568 , H01L2224/05573 , H01L2224/16225 , H01L2224/18 , H01L2224/24137 , H01L2224/82005 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01023 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01039 , H01L2924/01046 , H01L2924/01051 , H01L2924/01066 , H01L2924/01072 , H01L2924/01074 , H01L2924/01075 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01105 , H01L2924/014 , H01L2924/09701 , H01L2924/10329 , H01L2924/12042 , H01L2924/12043 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , Y10T156/1089 , H01L2924/00 , H01L2224/05611 , H01L2924/00014 , H01L2224/05644 , H01L2224/05647
摘要： A method for transferring devices to a device substrate is disclosed. In one embodiment, the method includes providing an array of devices on a carrier substrate having a generally horizontal surface, where the array comprises multiple device pluralities. The method includes tilting the device pluralities with respect to the generally horizontal surface of the carrier substrate. Each tilted device plurality is preferably in substantially the same pattern, and each tilted device plurality is placed on device regions on respective device substrates.

34. 发明授权

US06428942B1 Multilayer circuit structure build up method 失效
标题翻译：多层电路结构建立方法
公开(公告)号：US06428942B1
公开(公告)日：2002-08-06
申请号：US09429854
申请日：1999-10-28
申请人： Hunt Hang Jiang , Yasuhito Takahashi , Michael Guang-Tzong Lee , Wen-chou Vincent Wang , Mark McCormack
发明人： Hunt Hang Jiang , Yasuhito Takahashi , Michael Guang-Tzong Lee , Wen-chou Vincent Wang , Mark McCormack
IPC分类号： G03F700
CPC分类号： H01L24/96 , H01L21/486 , H01L2221/68359 , H01L2224/16237 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01023 , H01L2924/01027 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01051 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/01327 , H01L2924/12042 , H01L2924/3011 , H05K3/0035 , H05K3/108 , H05K3/243 , H05K3/4602 , H05K3/4647 , H05K2203/066 , H05K2203/0733 , H05K2203/1383 , H01L2924/00
摘要： Methods for forming multilayer circuit structures are disclosed. In some embodiments, conductive layers, dielectric layers and conductive posts can be formed on both sides of a circuitized core structure. The conductive posts are disposed in the dielectric layers and can be stacked to form a generally vertical conduction pathway which passes at least partially through a multilayer circuit structure. The formed multilayer circuit structures can occupy less space than corresponding multilayer circuit structures with stacked via structures.
摘要翻译：公开了形成多层电路结构的方法。在一些实施例中，可以在电路化芯结构的两侧上形成导电层，电介质层和导电柱。导电柱设置在电介质层中并且可以被堆叠以形成通常至少部分穿过多层电路结构的大致垂直的传导路径。形成的多层电路结构可以占据比具有堆叠通孔结构的相应多层电路结构更小的空间。

35. 发明授权

US07741160B1 Structure and assembly procedure for low stress thin die flip chip packages designed for low-K Si and thin core substrate 有权
标题翻译：针对低K Si和薄芯基板设计的低应力薄晶片倒装芯片封装的结构和组装程序
公开(公告)号：US07741160B1
公开(公告)日：2010-06-22
申请号：US12535624
申请日：2009-08-04
申请人： Wen-chou Vincent Wang , Yuan Li , Bruce Euzent , Vadali Mahadev
发明人： Wen-chou Vincent Wang , Yuan Li , Bruce Euzent , Vadali Mahadev
IPC分类号： H01L21/44
CPC分类号： H01L23/3128 , H01L21/50 , H01L21/563 , H01L23/16 , H01L24/31 , H01L24/81 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2224/73253 , H01L2224/81801 , H01L2924/01019 , H01L2924/0102 , H01L2924/01322 , H01L2924/10253 , H01L2924/14 , H01L2924/15311 , H01L2924/16195 , H01L2924/00 , H01L2924/3512
摘要： Provided are semiconductor die flip chip packages and semiconductor die flip chip package components where certain properties of the packages/components are controlled to facilitate management of the package stresses. Also provided are fabrication methods for such packages and package components. For instance, the thickness of a die can be controlled such that the stress generated/experienced by the die is minimized. As such, the package stress is managed to suitable levels for incorporation of a low-K Si die and/or a thin package substrate. Further, a thin die can be attached to a heat spreader to increase the rigidity for easier handling during fabrication of the semiconductor die flip chip package.
摘要翻译：提供了半导体管芯倒装芯片封装和半导体管芯倒装芯片封装元件，其中封装/部件的某些特性被控制以便于封装应力的管理。还提供了用于这种包装和包装部件的制造方法。例如，可以控制模具的厚度，使得由模具产生/经历的应力最小化。因此，封装应力被控制到适合于并入低K Si管芯和/或薄封装衬底的水平。此外，在半导体管芯倒装芯片封装的制造期间，可以将薄模具附接到散热器以增加刚性以便于更容易的处理。

36. 发明授权

US07427813B1 Structure, material, and design for assembling a low-K Si die to achieve an industrial grade reliability wire bonding package 有权
标题翻译：用于组装低K Si模具的结构，材料和设计，以实现工业级可靠性引线接合封装
公开(公告)号：US07427813B1
公开(公告)日：2008-09-23
申请号：US10719218
申请日：2003-11-20
申请人： Wen-chou Vincent Wang , Yuan Li
发明人： Wen-chou Vincent Wang , Yuan Li
IPC分类号： H01L29/40 , H01L23/28 , H01L23/29
CPC分类号： H01L23/3185 , H01L23/3107 , H01L23/3128 , H01L23/3142 , H01L23/3171 , H01L24/48 , H01L24/73 , H01L2224/32225 , H01L2224/32245 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/48465 , H01L2224/73265 , H01L2224/92247 , H01L2924/00014 , H01L2924/01019 , H01L2924/01079 , H01L2924/10253 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/45015 , H01L2924/207
摘要： Provided are semiconductor low-K Si die wire bonding packages with package stress control and fabrication methods for such packages. The packages include molding interface material applied onto the low-K Si die. In general, the molding interface material is selectively applied onto the low-K Si die surface in order to minimize to safe levels the package stress experienced by the low-K Si die. Selective application includes defining various combinatorial patterns of coated and non-coated regions. In addition, selective application may also include a general application of molding interface material to create a stress buffer zone. The results are packages with less stress experienced by the low-K Si die and so improved reliability (in compliance with industry specifications).
摘要翻译：提供具有封装应力控制的半导体低K Si芯线焊接封装和用于这种封装的制造方法。包装包括施加到低K Si模具上的成型界面材料。通常，将成型界面材料选择性地施加到低K Si晶粒表面上，以便最小化由低K Si晶粒经受的封装应力的安全水平。选择性应用包括定义涂层和非涂层区域的各种组合图案。此外，选择性应用还可以包括模制界面材料的一般应用以产生应力缓冲区。结果是低K Si模具经受较少应力的封装，从而提高了可靠性（符合行业规范）。

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