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31. 发明授权

US07265030B2 Method of fabricating silicon on glass via layer transfer 有权
标题翻译：通过层转移在玻璃上制造硅的方法
公开(公告)号：US07265030B2
公开(公告)日：2007-09-04
申请号：US10894685
申请日：2004-07-20
申请人： Jer-Shen Maa , Jong-Jan Lee , Douglas J. Tweet , Sheng Teng Hsu
发明人： Jer-Shen Maa , Jong-Jan Lee , Douglas J. Tweet , Sheng Teng Hsu
IPC分类号： H01L21/46
CPC分类号： H01L21/76254 , Y10S438/977
摘要： A method of fabricating a silicon-on-glass layer via layer transfer includes depositing a layer of SiGe on a silicon substrate; relaxing the SiGe layer; depositing a layer of silicon on the relaxed SiGe layer; implanting hydrogen ions in a second hydrogen implantation step to facilitate splitting of the wafer; bonding a glass substrate to the strained silicon layer to form a composite wafer; splitting the composite wafer to provide a split wafer; and processing the split wafer to prepare it for subsequent device fabrication.
摘要翻译：通过层转移制造硅 - 玻璃层的方法包括在硅衬底上沉积SiGe层; 放松SiGe层; 在松弛的SiGe层上沉积一层硅; 在第二氢注入步骤中注入氢离子以促进晶片的分裂; 将玻璃基板粘合到应变硅层以形成复合晶片; 分离复合晶片以提供分离晶片; 并处理分离晶片以准备其用于随后的器件制造。

32. 发明授权

US07186611B2 High-density germanium-on-insulator photodiode array 有权
标题翻译：高密度锗绝缘体上的光电二极管阵列
公开(公告)号：US07186611B2
公开(公告)日：2007-03-06
申请号：US11240969
申请日：2005-09-30
申请人： Sheng Teng Hsu , Jong-Jan Lee , Jer-Shen Maa , Douglas J. Tweet
发明人： Sheng Teng Hsu , Jong-Jan Lee , Jer-Shen Maa , Douglas J. Tweet
IPC分类号： H01L21/329
CPC分类号： H01L31/1126 , C30B19/00 , C30B29/08 , H01L21/02381 , H01L21/02488 , H01L21/02532 , H01L21/02623 , H01L21/02639 , H01L21/30625 , H01L21/7624 , H01L27/14683 , H01L27/14689 , H01L29/16 , H01L29/78 , H01L31/105 , H01L31/1804 , H01L31/1808 , Y02E10/547
摘要： A high-density Germanium (Ge)-on-Insulator (GOI) photodiode array and corresponding fabrication method are provided. The method includes: forming an array of pixel driver nMOST devices, each device having a gate connected to a row line in a first orientation, a first source/drain (S/D) region, and a second S/D region connected to Vdd; forming a P-I-N Ge diode for each pixel as follows: forming a n+ region; forming an intrinsic Ge region overlying the n+ region; forming a p+ junction in the intrinsic Ge; and, isolating the P-I-N Ge diodes; and, forming an Indium Tin oxide (ITO) column in a second orientation, about orthogonal to the first orientation, overlying the P-I-N Ge diodes.
摘要翻译：提供了高密度锗（Ge）绝缘体（GOI）光电二极管阵列和相应的制造方法。该方法包括：形成像素驱动器nMOST器件的阵列，每个器件具有以第一取向连接到行线的栅极，第一源极/漏极（S / D）区域和连接到Vdd的第二S / D区域 ; 如下形成每个像素的P-I-N Ge二极管：形成n +区; 形成覆盖n +区域的本征Ge区域; 在本征Ge中形成p +结; 并隔离P-I-N Ge二极管; 并且以与第一取向正交的第二取向形成铟锡氧化物（ITO）柱，覆盖P-I-N Ge二极管。

33. 发明授权

US07008813B1 Epitaxial growth of germanium photodetector for CMOS imagers 有权
标题翻译：用于CMOS成像器的锗光电探测器的外延生长
公开(公告)号：US07008813B1
公开(公告)日：2006-03-07
申请号：US11069424
申请日：2005-02-28
申请人： Jong-Jan Lee , Jer-Shen Maa , Douglas J. Tweet , Sheng Teng Hsu
发明人： Jong-Jan Lee , Jer-Shen Maa , Douglas J. Tweet , Sheng Teng Hsu
IPC分类号： H01L21/00
CPC分类号： H01L27/14689 , H01L31/105 , H01L31/1804 , Y02E10/547 , Y02P70/521 , Y10S148/101
摘要： A method of fabricating a germanium photodetector includes preparing a silicon wafer as a silicon substrate; depositing a layer of silicon nitride on the silicon substrate; patterning and etching the silicon nitride layer; depositing a first germanium layer on the silicon nitride layer; patterning and etching the germanium layer wherein a portion of the germanium layer is in direct physical contact with the silicon substrate; depositing a layer of silicon oxide on the germanium layer wherein the germanium layer is encapsulated by the silicon oxide layer; annealing the structure at a temperature wherein the germanium melts and the other layers remain solid; growing a second, single-crystal layer of germanium on the structure by liquid phase epitaxy; selectively removing the silicon oxide layer; and completing the germanium photodetector.
摘要翻译：制造锗光电检测器的方法包括制备硅晶片作为硅衬底; 在硅衬底上沉积氮化硅层; 图案化和蚀刻氮化硅层; 在所述氮化硅层上沉积第一锗层; 图案化和蚀刻锗层，其中锗层的一部分与硅衬底直接物理接触; 在锗层上沉积氧化硅层，其中锗层被氧化硅层包封; 在锗熔融并且其它层保持固体的温度下退火该结构; 通过液相外延在结构上生长第二个锗单晶层; 选择性地除去氧化硅层; 并完成锗光电探测器。

34. 发明授权

US06967112B2 Three-dimensional quantum dot structure for infrared photodetection 有权
标题翻译：用于红外光电检测的三维量子点结构
公开(公告)号：US06967112B2
公开(公告)日：2005-11-22
申请号：US10794158
申请日：2004-03-03
申请人： Jer-Shen Maa , Jong-Jan Lee , Douglas J. Tweet , Sheng Teng Hsu
发明人： Jer-Shen Maa , Jong-Jan Lee , Douglas J. Tweet , Sheng Teng Hsu
IPC分类号： H01L21/00 , H01L21/66 , H01L31/0352 , H01L31/26
CPC分类号： H01L31/035236 , B82Y10/00 , B82Y20/00
摘要： A 3D quantum dot optical path structure is provided, along with a method for selectively forming a 3D quantum dot optical path. The method comprises: forming a single crystal Si substrate with a surface; forming a Si feature in the substrate, such as a via, trench, or pillar; forming dots from a Ge or SiGe material overlying the Si feature; and, forming an optical path that includes the dots. In some aspects of the method, the Si feature has defect sites. For example, the Si feature may be formed with a miscut angle. As a result of the miscut angle, steps are formed in the Si feature plane. Then, the dots are formed in the Si feature steps. The miscut angle is in the range between 0.1 and 5 degrees, and the spacing between steps is in the range between 1 and 250 nanometers (nm).
摘要翻译：提供了3D量子点光路结构以及用于选择性地形成3D量子点光路的方法。该方法包括：用表面形成单晶Si衬底; 在衬底中形成Si特征，例如通孔，沟槽或柱; 从覆盖Si特征的Ge或SiGe材料形成点; 并且形成包括点的光路。在该方法的某些方面，Si特征具有缺陷位点。例如，Si特征可以形成为错误角度。作为误差角的结果，在Si特征平面中形成台阶。然后，在Si特征步骤中形成点。误差角在0.1和5度之间的范围内，并且步骤之间的间隔在1和250纳米（nm）之间的范围内。

35. 发明授权

US06903384B2 System and method for isolating silicon germanium dislocation regions in strained-silicon CMOS applications 失效
标题翻译：在应变硅CMOS应用中分离硅锗位错区的系统和方法
公开(公告)号：US06903384B2
公开(公告)日：2005-06-07
申请号：US10345551
申请日：2003-01-15
申请人： Sheng Teng Hsu , Jong-Jan Lee , Douglas J. Tweet , Jer-shen Maa
发明人： Sheng Teng Hsu , Jong-Jan Lee , Douglas J. Tweet , Jer-shen Maa
IPC分类号： H01L21/322 , H01L21/762 , H01L21/8238 , H01L27/092 , H01L27/12 , H01L29/10 , H01L29/78 , H01L29/786 , H01L31/0312
CPC分类号： H01L29/1054 , H01L21/76224 , H01L21/823807 , H01L21/823842 , H01L21/823878 , H01L27/1203 , H01L29/78645
摘要： A dual gate strained-Si MOSFET with thin SiGe dislocation regions and a method for fabricating the same are provided. The method comprises: forming a first layer of relaxed SiGe overlying a substrate, having a thickness of less than 5000 Å; forming a second layer of relaxed SiGe overlying the substrate and adjacent to the first layer of SiGe, having a thickness of less than 5000 Å; forming a layer of strained-Si overlying the first and second SiGe layers; forming a shallow trench isolation region interposed between the first SiGe layer and the second SiGe layer; forming an n-well in the substrate and the overlying first layer of SiGe; forming a p-well in the substrate and the overlying second layer of SiGe; forming channel regions, in the strained-Si, and forming PMOS and NMOS transistor source and drain regions.
摘要翻译：提供具有薄SiGe位错区域的双栅应变Si MOSFET及其制造方法。该方法包括：形成覆盖衬底的第一层松弛SiGe，厚度小于5000; 形成第二层弛豫的SiGe，覆盖衬底并与第一层SiGe相邻，厚度小于5000; 形成层叠在第一和第二SiGe层上的应变层; 形成介于所述第一SiGe层和所述第二SiGe层之间的浅沟槽隔离区域; 在衬底和上覆的第一层SiGe中形成n阱; 在衬底和SiGe的上覆第二层中形成p阱; 在应变Si中形成沟道区，并形成PMOS和NMOS晶体管的源极和漏极区。

36. 发明授权

US06767802B1 Methods of making relaxed silicon-germanium on insulator via layer transfer 失效
标题翻译：通过层转移在绝缘体上制造松散的硅 - 锗的方法
公开(公告)号：US06767802B1
公开(公告)日：2004-07-27
申请号：US10665944
申请日：2003-09-19
申请人： Jer-Shen Maa , Jong-Jan Lee , Douglas J. Tweet , Sheng Teng Hsu
发明人： Jer-Shen Maa , Jong-Jan Lee , Douglas J. Tweet , Sheng Teng Hsu
IPC分类号： H01L2176
CPC分类号： H01L21/76254
摘要： Methods of forming a SiGe layer overlying an insulator are provided. A layer of SiGe is deposited on a substrate and implanted with ion to form a defect region within the SiGe material below its surface. The SiGe layer is then patterned and transferred by contact bonding to an insulator on a second substrate. After contact bonding the structure is annealed to split the SiGe layer along the defect region. The splitting anneal will relax the SiGe layer. Additional annealing at higher temperatures may be used to further relax the SiGe layer. A layer of strained silicon may then be epitaxial deposited on the resulting structure of relaxed SiGe on insulator. Another method provides for epitaxially depositing a layer of silicon over the SiGe layer prior to patterning. The silicon layer would then be bonded to the insulator on the second substrate. The splitting anneal and additional anneals, if any, should then induce strain into the silicon layer. The silicon layer would then remain over the insulator after the SiGe layer is removed.
摘要翻译：提供了形成覆盖在绝缘体上的SiGe层的方法。将一层SiGe沉积在衬底上并注入离子以在其表面下方的SiGe材料内形成缺陷区。然后，通过接触粘合将SiGe层图案化并转移到第二基板上的绝缘体。在接合之后，将结构退火以沿着缺陷区域分离SiGe层。分裂退火将使SiGe层松弛。可以在较高温度下进行额外退火以进一步松弛SiGe层。然后可以将绝缘体上的松散SiGe结构外延沉积一层应变硅。另一种方法提供在图案化之前在SiGe层上外延沉积硅层。然后将硅层与第二基板上的绝缘体接合。分裂退火和额外的退火（如果有的话）应该在硅层中诱导应变。在除去SiGe层之后，硅层将保留在绝缘体上。

37. 发明授权

US07906825B2 Ge imager for short wavelength infrared 有权
标题翻译： Ge成像仪用于短波长红外
公开(公告)号：US07906825B2
公开(公告)日：2011-03-15
申请号：US12630893
申请日：2009-12-04
申请人： Douglas J. Tweet , Jer-Shen Maa , Jong-Jan Lee , Sheng Teng Hsu
发明人： Douglas J. Tweet , Jer-Shen Maa , Jong-Jan Lee , Sheng Teng Hsu
IPC分类号： H01L27/14
CPC分类号： H01L31/1055 , H01L27/14643 , H01L27/14689
摘要： A germanium (Ge) short wavelength infrared (SWIR) imager and associated fabrication process are provided. The imager comprises a silicon (Si) substrate with doped wells. An array of pin diodes is formed in a relaxed Ge-containing film overlying the Si substrate, each pin diode having a flip-chip interface. There is a Ge/Si interface, and a doped Ge-containing buffer interposed between the Ge-containing film and the Ge/Si interface. An array of Si CMOS readout circuits is bonded to the flip-chip interfaces. Each readout circuit has a zero volt diode bias interface.
摘要翻译：提供锗（Ge）短波长红外（SWIR）成像器和相关制造工艺。该成像器包括具有掺杂阱的硅（Si）衬底。在位于Si衬底上的松弛的含Ge膜中形成一个pin二极管阵列，每个pin二极管具有倒装芯片接口。存在Ge / Si界面和插入含Ge膜和Ge / Si界面之间的含掺杂Ge的缓冲层。 Si CMOS读出电路阵列结合到倒装芯片接口。每个读出电路都具有零伏二极管偏置接口。

38. 发明授权

US07786469B2 Thermal sensor with a silicon/germanium superlattice structure 有权
标题翻译：具有硅/锗超晶格结构的热传感器
公开(公告)号：US07786469B2
公开(公告)日：2010-08-31
申请号：US12236480
申请日：2008-09-23
申请人： Jer-Shen Maa , Jinke Tang , Jong-Jan Lee , Douglas J. Tweet , Sheng Teng Hsu
发明人： Jer-Shen Maa , Jinke Tang , Jong-Jan Lee , Douglas J. Tweet , Sheng Teng Hsu
IPC分类号： H01L31/00
CPC分类号： H01L31/035254 , B82Y20/00 , H01L27/14649 , H01L31/028 , H01L31/101 , H01L31/1804 , Y02P70/521
摘要： A silicon/germanium (SiGe) superlattice thermal sensor is provided with a corresponding fabrication method. The method forms an active CMOS device in a first Si substrate, and a SiGe superlattice structure on a second Si-on-insulator (SOI) substrate. The first substrate is bonded to the second substrate, forming a bonded substrate. An electrical connection is formed between the SiGe superlattice structure and the CMOS device, and a cavity is formed between the SiGe superlattice structure and the bonded substrate.
摘要翻译：硅/锗（SiGe）超晶格热传感器具有相应的制造方法。该方法在第一Si衬底中形成有源CMOS器件，并在第二绝缘体上（SOI）衬底上形成SiGe超晶格结构。第一基板与第二基板接合，形成接合基板。在SiGe超晶格结构和CMOS器件之间形成电连接，并且在SiGe超晶格结构和键合衬底之间形成空穴。

39. 发明授权

US07390725B2 Strained silicon on insulator from film transfer and relaxation by hydrogen implantation 有权
标题翻译：绝缘体上的应变硅通过氢注入从膜转移和弛豫
公开(公告)号：US07390725B2
公开(公告)日：2008-06-24
申请号：US11284326
申请日：2005-11-21
申请人： Jer-shen Maa , Jong-Jan Lee , Douglas J. Tweet , David R. Evans , Allen W. Burmaster , Sheng Teng Hsu
发明人： Jer-shen Maa , Jong-Jan Lee , Douglas J. Tweet , David R. Evans , Allen W. Burmaster , Sheng Teng Hsu
IPC分类号： H01L21/46 , H01L21/30
CPC分类号： H01L21/76254
摘要： Transistors fabricated on SSOI (Strained Silicon On Insulator) substrate, which comprises a strained silicon layer disposed directly on an insulator layer, have enhanced device performance due to the strain-induced band modification of the strained silicon device channel and the limited silicon volume because of the insulator layer. The present invention discloses SSOI substrate fabrication processes comprising various novel approaches. One is the use of a thin relaxed SiGe layer as the strain-induced seed layer to facilitate integration and reduce processing cost. Another is the formation of split implant microcracks deep in the silicon substrate to reduce the number of threading dislocations reaching the strained silicon layer. And lastly is a two step annealing/thinning process for the strained silicon/SiGe multilayer film transfer without blister or flaking formation.
摘要翻译：包含直接设置在绝缘体层上的应变硅层的SSOI（应变绝缘体硅）基板上制造的晶体管由于应变诱导的应变硅器件通道的带隙修改而增加了器件性能，并且由于绝缘体层。本发明公开了包含各种新颖方法的SSOI衬底制造工艺。一个是使用薄的松弛SiGe层作为应变诱导的种子层，以促进整合并降低加工成本。另一个是在硅衬底深部形成分裂的植入物微裂纹，以减少到达应变硅层的穿透位错的数量。最后是对应变硅/ SiGe多层膜转移进行两步退火/变薄处理，无需起泡或剥落形成。

40. 发明授权

US07323349B2 Self-aligned cross point resistor memory array 有权
标题翻译：自对准交叉点电阻存储器阵列
公开(公告)号：US07323349B2
公开(公告)日：2008-01-29
申请号：US11120385
申请日：2005-05-02
申请人： Sheng Teng Hsu , Jong-Jan Lee , Jer-Shen Maa , Douglas J. Tweet , Wei-Wei Zhuang
发明人： Sheng Teng Hsu , Jong-Jan Lee , Jer-Shen Maa , Douglas J. Tweet , Wei-Wei Zhuang
IPC分类号： H01L21/00 , H01L21/8242
CPC分类号： H01L27/101 , H01L27/2409 , H01L27/2481 , H01L45/04 , H01L45/1233 , H01L45/147 , H01L45/1683
摘要： A method of fabricating resistor memory array includes preparing a silicon substrate; depositing a bottom electrode, a sacrificial layer, and a hard mask layer on a substrate P+ layer; masking, patterning and etching to remove, in a first direction, a portion of the hard mask, the sacrificial material, the bottom electrode; depositing a layer of silicon oxide; masking, patterning and etching to remove, in a second direction perpendicular to the first direction, a portion of the hard mask, the sacrificial material, the bottom electrode;, and over etching to an N+ layer and at least 100 nm of the silicon substrate; depositing of a layer of silicon oxide; etching to remove any remaining hard mask and any remaining sacrificial material; depositing a layer of CMR material; depositing a top electrode; applying photoresist, patterning the photoresist and etching the top electrode; and incorporating the memory array into an integrated circuit.
摘要翻译：制造电阻器存储器阵列的方法包括制备硅衬底; 在衬底P +层上沉积底部电极，牺牲层和硬掩模层; 掩模，图案化和蚀刻以在第一方向上去除硬掩模，牺牲材料，底部电极的一部分; 沉积一层氧化硅; 掩模，图案化和蚀刻以在垂直于第一方向的第二方向上去除硬掩模，牺牲材料，底部电极的一部分，并且对N +层和至少100nm的硅衬底进行过蚀刻 ; 沉积一层氧化硅; 蚀刻以除去任何剩余的硬掩模和任何剩余的牺牲材料; 沉积一层CMR材料; 沉积顶部电极; 施加光致抗蚀剂，图案化光致抗蚀剂并蚀刻顶部电极; 并将存储器阵列并入集成电路中。

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