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    • 31. 发明授权
    • After potential removal in cardiac rhythm management device
    • 心脏节律管理装置中潜在去除后
    • US5690683A
    • 1997-11-25
    • US492199
    • 1995-06-19
    • Paul A. HaefnerMark A. StockburgerWilliam J. Linder
    • Paul A. HaefnerMark A. StockburgerWilliam J. Linder
    • A61N1/37A61N1/39
    • A61N1/3704Y10S128/901
    • An apparatus effectively removes after potential occurring after a electrical pulse is delivered in a cardiac rhythm management system such as a pacemaker system or cardioverter/defibrillator system having an electrode used for both sensing electrical activity of the heart and carrying the electrical pulse to the heart and a sense amplifier for detecting the electrical activity from the electrode. The apparatus includes a lowpass filter coupled to the electrode to filter the sensed electrical activity. A highpass filter is coupled between the lowpass filter and the sense amplifier to further filter the electrical activity passed from the lowpass filter. Equilibrium circuitry is included to allow passive filter components of the lowpass filter and the highpass filter to return to an equilibrium state following delivery of the electrical pulse.
    • 一种装置在电脉冲在诸如起搏器系统或心脏转复器/除颤器系统的心律管理系统中传递之后有效地消除,所述心脏起搏器系统或心脏转复器/除颤器系统具有用于感测心脏的电活动并将心电的脉搏传送到心脏的电极, 用于检测来自电极的电活动的读出放大器。 该装置包括耦合到电极的低通滤波器以滤波感测的电活动。 低通滤波器耦合在低通滤波器和读出放大器之间,以进一步滤除从低通滤波器传递的电活动。 包括平衡电路,以允许低通滤波器的无源滤波器组件和高通滤波器在电脉冲传递后恢复平衡状态。
    • 32. 发明授权
    • Charge redistribution capacitance detection apparatus
    • 电荷再分配电容检测装置
    • US4728931A
    • 1988-03-01
    • US890215
    • 1986-07-25
    • William J. LinderJames D. Reinke
    • William J. LinderJames D. Reinke
    • G01R27/26H03K5/24H03K17/96G06F3/02
    • H03K17/9622G01R27/2605H03K5/249H03K2017/9613Y10T307/766
    • A charge redistribution capacitance detector is disclosed for detecting whether the capacitance of a variable capacitor is smaller or larger than that of a reference capacitor. First plates of the variable and reference capacitors are connected to a sense node, and a switching device responsive to a clock signal periodically impresses a reference voltage on the sense node during one phase of the clock signal and allows the sense node to electrically float during the alternate phase of the clock signal. Second plates of the sense and reference capacitors are alternately charged and discharged by equal voltage differences in opposite senses during successive clock phases. The voltage on the first plates of the capacitors changes in a sense dependent on the relative capacitance values of the capacitors and is compared with the reference voltage by a comparator which produces a corresponding detector output.
    • 公开了一种用于检测可变电容器的电容是否小于或大于参考电容器的电荷再分配电容检测器。 可变参考电容器的第一板连接到感测节点,并且响应于时钟信号的开关装置在时钟信号的一个相位期间周期性地在感测节点上施加参考电压,并允许感测节点在 时钟信号的交替相位。 感测和参考电容器的第二板在连续的时钟相位期间以相反的感测相等的电压差交替地充电和放电。 电容器的第一板上的电压在某种意义上根据电容器的相对电容值而改变,并且通过产生相应检测器输出的比较器与参考电压进行比较。
    • 33. 发明授权
    • CMOS Window detector with hysteresis
    • 具有滞后的CMOS窗口检测器
    • US4503340A
    • 1985-03-05
    • US418512
    • 1982-09-16
    • William J. Linder
    • William J. Linder
    • H03K3/3565H03K5/153
    • H03K3/3565
    • A CMOS window detector provides an output signal which indicates the relationship of an input signal to a voltage "window" as a function of the previous output signal. The window detector includes first and second current source circuits and first and second inverter circuits. A bias current is established in each current source circuit as a function of a different reference voltage. The first and second inverter circuits each include a current mirror field effect transistor (FET) and a current control FET connected in a series current path. The current mirror FET of each inverter circuit is connected to its respective current source circuit and establishes a current in the inverter current path equal in magnitude to its respective bias current. The input signal is applied to the gates of the current control FETs. Each current control FET changes conductivity state when the input signal reaches the reference voltage level used to establish the respective inverter current flow. Each reference voltage therefore represents a window voltage level. The difference in window voltage levels defines the voltage window. An output circuit formed by a CMOS NAND-latch is connected to the first and second inverter circuits and provides the output signal which exhibits hysteresis with respect to the input signal.
    • CMOS窗口检测器提供输出信号,其指示输入信号与作为先前输出信号的函数的电压“窗口”的关系。 窗口检测器包括第一和第二电流源电路以及第一和第二反相器电路。 在每个电流源电路中建立偏置电流作为不同参考电压的函数。 第一和第二逆变器电路各自包括电流镜效应晶​​体管(FET)和连接在串联电流路径中的电流控制FET。 每个逆变器电路的电流反射镜FET连接到其各自的电流源电路,并且在逆变器电流路径中建立与其相应的偏置电流大小相等的电流。 输入信号被施加到电流控制FET的栅极。 当输入信号达到用于建立相应逆变器电流的基准电压电平时,每个电流控制FET改变导电状态。 因此,每个参考电压表示窗口电压电平。 窗口电压电平的差异定义了电压窗口。 由CMOS NAND锁存器形成的输出电路连接到第一和第二反相器电路,并提供相对于输入信号呈现迟滞的输出信号。