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31. 发明申请

US20090168487A1 CYCLING TO MITIGATE IMPRINT IN FERROELECTRIC MEMORIES 有权
标题翻译：循环缓解电磁记忆中的印记
公开(公告)号：US20090168487A1
公开(公告)日：2009-07-02
申请号：US11964223
申请日：2007-12-26
申请人： John Anthony Rodriguez , Sanjeev Aggarwal
发明人： John Anthony Rodriguez , Sanjeev Aggarwal
IPC分类号： G11C11/22 , G11C11/24 , G11C7/00
CPC分类号： G11C11/22 , G11C29/50
摘要： One embodiment of the present invention relates to a method for reducing the imprint of a ferroelectric memory cell. The method comprises storing a memory data state in the ferroelectric memory cell. An event will trigger the evaluation of signal margin on a memory cell. If the memory cell is identified to have a weak signal, the memory cell is exercised. Exercising comprises either performing one or more data read/re-write events or performing one or more simulated data read and data write events of an alternating high data state and a low data state to the memory cell associated with the weak data bit. Both the lifetime retention testing and the memory data state exercising are performed in the background of normal memory operation. Other methods and circuits are also disclosed.
摘要翻译：本发明的一个实施例涉及一种用于减小铁电存储单元的印记的方法。该方法包括将存储器数据状态存储在铁电存储单元中。事件将触发对存储器单元的信号余量的评估。如果存储器单元被识别为具有弱信号，则执行存储器单元。执行包括执行一个或多个数据读取/重写事件或者执行交替的高数据状态和低数据状态的一个或多个模拟数据读取和数据写入事件到与弱数据位相关联的存储单元。寿命保留测试和存储器数据状态行使都是在正常存储器操作的背景下执行的。还公开了其它方法和电路。

32. 发明授权

US07361949B2 Method of making a haze free, lead rich PZT film 有权
标题翻译：制造无雾，富含铅的PZT膜的方法
公开(公告)号：US07361949B2
公开(公告)日：2008-04-22
申请号：US11046568
申请日：2005-01-28
申请人： Sanjeev Aggarwal , Kelly J. Taylor
发明人： Sanjeev Aggarwal , Kelly J. Taylor
IPC分类号： H01L29/76
CPC分类号： H01L21/31691 , C23C16/409 , H01L28/55
摘要： An embodiment of the invention is a method of fabricating a haze free, phase pure, PZT layer, 3, where a lead rich PZT film, 102, is formed over a phase pure stoichiometric PZT film, 101.
摘要翻译：本发明的一个实施方案是制造无浑浊，纯相的PZT层3的方法，其中在相纯化学计量PZT膜101上形成富铅PZT膜102。

33. 发明授权

US07144808B1 Integration flow to prevent delamination from copper 有权
标题翻译：整合流程以防止铜分层
公开(公告)号：US07144808B1
公开(公告)日：2006-12-05
申请号：US11151154
申请日：2005-06-13
申请人： Sanjeev Aggarwal , Kelly J. Taylor
发明人： Sanjeev Aggarwal , Kelly J. Taylor
IPC分类号： H01L21/44 , H01L21/4763
CPC分类号： H01L21/76843 , H01L21/02063 , H01L21/76814 , H01L21/76826 , H01L21/76828
摘要： The present invention provides, in one embodiment, method of forming a barrier layer 300 over a semiconductor substrate 110. The method comprises forming an opening 120 in an insulating layer 130 located over a substrate thereby uncovering an underlying copper layer 140. The method further comprises exposing the opening and the underlying copper layer to a plasma-free reducing atmosphere 200 in the presence of a thermal anneal. The also comprises depositing a barrier layer in the exposed opening and on the exposed underlying copper layer. Such methods and resulting conductive structures thereof may be advantageously used in methods to manufacture integrated circuits comprising copper interconnects.
摘要翻译：本发明在一个实施例中提供了在半导体衬底110上形成阻挡层300的方法。该方法包括在位于衬底上的绝缘层130中形成开口120，从而露出下面的铜层140.该方法还包括在热退火的存在下将开口和下层铜层暴露于无等离子体还原气氛200。还包括在暴露的开口中和暴露的下面的铜层上沉积阻挡层。这样的方法及其导电结构可有利地用于制造包括铜互连的集成电路的方法中。

34. 发明授权

US06995088B2 Surface treatment of copper to improve interconnect formation 有权
标题翻译：铜的表面处理以改善互连形成
公开(公告)号：US06995088B2
公开(公告)日：2006-02-07
申请号：US10848219
申请日：2004-05-18
申请人： Sanjeev Aggarwal , Lindsey Hall , Trace Q. Hurd
发明人： Sanjeev Aggarwal , Lindsey Hall , Trace Q. Hurd
IPC分类号： H01L21/44
CPC分类号： H01L21/2885 , H01L21/76843 , H01L21/76855 , H01L21/76861 , H01L21/76873
摘要： The present invention provides, in one embodiment, a method of forming a copper layer (100) over a semiconductor substrate (105). The method comprises coating a copper seed layer (110) located over a semiconductor substrate with a protective agent (120) to form a protective layer (125). The method also includes placing the semiconductor substrate in an acid bath (145) to remove the protective layer. The method further includes electrochemically depositing a second copper layer (155) on the copper seed layer. Such methods and resulting conductive structures thereof may be advantageously used in methods to manufacture integrated circuits comprising copper interconnects.
摘要翻译：在一个实施例中，本发明提供了一种在半导体衬底（105）上形成铜层（100）的方法。该方法包括用保护剂（120）涂覆位于半导体衬底上的铜籽晶层（110）以形成保护层（125）。该方法还包括将半导体衬底放置在酸浴（145）中以去除保护层。该方法还包括在铜籽晶层上电化学沉积第二铜层（155）。这样的方法及其导电结构可有利地用于制造包括铜互连的集成电路的方法中。

35. 发明授权

US06730354B2 Forming ferroelectric Pb(Zr,Ti)O3 films 失效
标题翻译：形成铁电Pb（Zr，Ti）O3薄膜
公开(公告)号：US06730354B2
公开(公告)日：2004-05-04
申请号：US09925223
申请日：2001-08-08
申请人： Stephen R. Gilbert , Kaushal Singh , Sanjeev Aggarwal , Stevan Hunter
发明人： Stephen R. Gilbert , Kaushal Singh , Sanjeev Aggarwal , Stevan Hunter
IPC分类号： C23C1640
CPC分类号： C23C16/409 , H01L21/31691 , Y10S427/101
摘要： Improved methods of forming PZT thin films that are compatible with industry-standard chemical vapor deposition production techniques are described. These methods enable PZT thin films having thicknesses of 70 nm or less to be fabricated with high within-wafer uniformity, high throughput and at a relatively low deposition temperature. In one aspect, a source reagent solution comprising a mixture of a lead precursor, a titanium precursor and a zirconium precursor in a solvent medium is provided. The source reagent solution is vaporized to form a precursor vapor. The precursor vapor is introduced into a chemical vapor deposition chamber containing the substrate. In another aspect, before deposition, the substrate is preheated during a preheating period. After the preheating period, the substrate is disposed on a heated susceptor during a heating period, after which a PZT film is formed on the heated substrate.
摘要翻译：描述了与工业标准化学气相沉积生产技术相容的形成PZT薄膜的改进方法。这些方法使得厚度为70nm以下的PZT薄膜能够制造成具有高的晶片内均匀性，高产量和较低的沉积温度。一方面，提供了在溶剂介质中包含铅前体，钛前体和锆前体的混合物的源试剂溶液。源试剂溶液蒸发以形成前体蒸气。将前体蒸气引入含有基材的化学气相沉积室中。另一方面，在沉积之前，在预热期间预热衬底。在预热期间之后，在加热时间内将衬底设置在加热的基座上，之后在被加热的衬底上形成PZT膜。

36. 发明授权

US06576482B1 One step deposition process for the top electrode and hardmask in a ferroelectric memory cell 有权
标题翻译：在铁电存储器单元中的顶部电极和硬掩模的一步沉积工艺
公开(公告)号：US06576482B1
公开(公告)日：2003-06-10
申请号：US10140481
申请日：2002-05-07
申请人： Sanjeev Aggarwal , Scott R. Summerfelt , Stevan G. Hunter
发明人： Sanjeev Aggarwal , Scott R. Summerfelt , Stevan G. Hunter
IPC分类号： H01L2100
CPC分类号： H01L28/75 , H01L21/28568 , H01L21/3143 , H01L28/55
摘要： One aspect of the invention relates to a one-step process for forming a transition metal aluminum oxynitride layer over a transition metal aluminum nitride layer. The transition metal aluminum nitride layer is sputter deposited using a transition metal/aluminum target in an atmosphere containing nitrogen. Subsequently, the oxygen content of the atmosphere is increased, whereby the transition metal aluminum oxynitride layer can be deposited without interrupting the process or otherwise reconditioning the target. Another aspect of the invention relates to depositing a transition metal aluminum nitride layer over a transition metal aluminum oxynitride layer by reducing the oxygen content of the atmosphere. The invention provides a one-step process for depositing a hard mask layer and upper diffusion barrier layer for the capacitor stack of a FeRAM. A top electrode, such as an Ir/IrO electrode, can be deposited as part of the one-step process.
摘要翻译：本发明的一个方面涉及在过渡金属氮化铝层上形成过渡金属铝氧氮化物层的一步法。使用过渡金属/铝靶在含氮的气氛中溅射沉积过渡金属氮化铝层。随后，气氛的氧含量增加，从而可以沉积过渡金属铝氮氧化物层，而不会中断该工艺或以其他方式修复靶。本发明的另一方面涉及通过降低大气中的氧含量在过渡金属铝氮氧化物层上沉积过渡金属氮化铝层。本发明提供了一种用于沉积FeRAM的电容器堆叠的硬掩模层和上扩散阻挡层的一步法。作为一步法的一部分，可以沉积上电极，例如Ir / IrO电极。

37. 发明授权

US06528328B1 Methods of preventing reduction of irox during PZT formation by metalorganic chemical vapor deposition or other processing 有权
标题翻译：通过金属有机化学气相沉积或其他处理防止PZT形成期间irox的还原的方法
公开(公告)号：US06528328B1
公开(公告)日：2003-03-04
申请号：US10036903
申请日：2001-12-21
申请人： Sanjeev Aggarwal , Stephen R. Gilbert , Scott R. Summerfelt
发明人： Sanjeev Aggarwal , Stephen R. Gilbert , Scott R. Summerfelt
IPC分类号： H01L2100
CPC分类号： H01L28/75 , H01L27/115 , H01L27/11507 , H01L28/55 , H01L28/60
摘要： A method of fabricating a ferroelectric capacitor is disclosed. The method comprises the decreases a reduction in a bottom electrode material during formation of the ferroelectric dielectric portion of the capacitor. In the above manner, a fatigue resistance of the ferroelectric capacitor is increased substantially.
摘要翻译：公开了一种制造铁电电容器的方法。该方法包括在形成电容器的铁电介质部分期间降低底部电极材料的减少。以上述方式，铁电电容器的耐疲劳性大幅度提高。

38. 发明授权

US06500678B1 Methods of preventing reduction of IrOx during PZT formation by metalorganic chemical vapor deposition or other processing 有权
标题翻译：通过金属有机化学气相沉积或其他处理防止PZT形成期间IrOx的还原的方法
公开(公告)号：US06500678B1
公开(公告)日：2002-12-31
申请号：US10036771
申请日：2001-12-21
申请人： Sanjeev Aggarwal , Stephen R. Gilbert , Scott R. Summerfelt
发明人： Sanjeev Aggarwal , Stephen R. Gilbert , Scott R. Summerfelt
IPC分类号： H01G706
CPC分类号： H01L28/55 , C23C14/08 , C23C16/0281 , C23C16/409 , H01L27/11502 , H01L27/11507 , H01L28/60
摘要： A method of fabricating a ferroelectric capacitor is disclosed. The method comprises the decreases a reduction in a bottom electrode material during formation of the ferroelectric dielectric portion of the capacitor. In the above manner, a fatigue resistance of the ferroelectric capacitor is increased substantially.
摘要翻译：公开了一种制造铁电电容器的方法。该方法包括在形成电容器的铁电介质部分期间降低底部电极材料的减少。以上述方式，铁电电容器的耐疲劳性大幅度提高。

39. 发明授权

US08518734B2 Process integration of a single chip three axis magnetic field sensor 有权
标题翻译：单芯片三轴磁场传感器的工艺集成
公开(公告)号：US08518734B2
公开(公告)日：2013-08-27
申请号：US12751927
申请日：2010-03-31
申请人： Renu Whig , Phillip Mather , Kenneth Smith , Sanjeev Aggarwal , Jon Slaughter , Nicholas Rizzo
发明人： Renu Whig , Phillip Mather , Kenneth Smith , Sanjeev Aggarwal , Jon Slaughter , Nicholas Rizzo
IPC分类号： H01L27/20 , H01L41/06 , G01R33/02
CPC分类号： H01L43/12 , B82Y25/00 , G01R33/0052 , G01R33/09 , G01R33/093 , G01R33/098 , H01L27/22 , H01L43/02 , H01L43/08
摘要： A semiconductor process integrates three bridge circuits, each include magnetoresistive sensors coupled as a Wheatstone bridge on a single chip to sense a magnetic field in three orthogonal directions. The process includes various deposition and etch steps forming the magnetoresistive sensors and a plurality of flux guides on one of the three bridge circuits for transferring a “Z” axis magnetic field onto sensors orientated in the XY plane.
摘要翻译：半导体工艺集成了三个桥接电路，每个电路包括在单个芯片上作为惠斯登电桥耦合的磁阻传感器，以在三个正交方向上感测磁场。该过程包括形成磁阻传感器的各种沉积和蚀刻步骤以及在三个桥接电路中的一个上的多个通量引导器，用于将“Z”轴磁场传送到在XY平面中定向的传感器上。

40. 发明授权

US07729156B2 Cycling to mitigate imprint in ferroelectric memories 有权
标题翻译：循环以减轻铁电记忆中的印记
公开(公告)号：US07729156B2
公开(公告)日：2010-06-01
申请号：US11964223
申请日：2007-12-26
申请人： John Anthony Rodriguez , Sanjeev Aggarwal
发明人： John Anthony Rodriguez , Sanjeev Aggarwal
IPC分类号： G11C11/22
CPC分类号： G11C11/22 , G11C29/50
摘要： The method includes storing a memory data state in the ferroelectric memory cell. An event will trigger the evaluation of signal margin on a memory cell. If the memory cell is identified to have a weak signal, the memory cell is exercised. Exercising includes either performing one or more data read/re-write events or performing one or more simulated data read and data write events of an alternating high data state and a low data state to the memory cell associated with the weak data bit. Both the lifetime retention testing and the memory data state exercising are performed in the background of normal memory operation.
摘要翻译：该方法包括将存储器数据状态存储在铁电存储单元中。事件将触发对存储器单元的信号余量的评估。如果存储器单元被识别为具有弱信号，则执行存储器单元。执行包括执行一个或多个数据读取/重写事件，或者执行交替的高数据状态和低数据状态的一个或多个模拟数据读取和数据写入事件到与弱数据位相关联的存储器单元。寿命保留测试和存储器数据状态行使都是在正常存储器操作的背景下执行的。

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