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31. 发明授权

US10340375B2 Epitaxial substrate for field effect transistor 有权
公开(公告)号：US10340375B2
公开(公告)日：2019-07-02
申请号：US12527142
申请日：2008-02-12
申请人： Masahiko Hata , Hiroyuki Sazawa , Naohiro Nishikawa
发明人： Masahiko Hata , Hiroyuki Sazawa , Naohiro Nishikawa
IPC分类号： H01L29/06 , H01L31/00 , H01L29/778 , H01L29/207 , H01L29/66 , H01L21/02 , H01L29/20
摘要： The present invention provides an epitaxial substrate for field effect transistor. In the epitaxial substrate for field effect transistor, a nitride-based Group III-V semiconductor epitaxial crystal containing Ga is interposed between the ground layer and the operating layer, and the nitride-based Group III-V semiconductor epitaxial crystal includes the following (i), (ii) and (iii). (i) a first buffer layer containing Ga or Al and containing a high resistivity crystal layer having added thereto compensation impurity element present in the same period as Ga in the periodic table and having small atomic number; (ii) a second buffer layer containing Ga or Al, laminated on the operating layer side of the first buffer layer; and (iii) a high purity epitaxial crystal layer containing acceptor impurities in a slight amount such that non-addition or depletion state can be maintained, provided between the high resistivity layer and the operating layer.

32. 发明申请

US20110180903A1 SEMICONDUCTOR SUBSTRATE, ELECTRONIC DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR SUBSTRATE 审中-公开
标题翻译：半导体衬底，电子器件及制造半导体衬底的方法
公开(公告)号：US20110180903A1
公开(公告)日：2011-07-28
申请号：US13122103
申请日：2009-10-01
申请人： Masahiko Hata
发明人： Masahiko Hata
IPC分类号： H01L29/161 , H01L29/22 , H01L29/20 , H01L21/20
CPC分类号： H01L29/78681 , H01L21/02381 , H01L21/02433 , H01L21/0245 , H01L21/02461 , H01L21/02463 , H01L21/02538 , H01L21/02551 , H01L21/02645 , H01L21/02647 , H01L21/84 , H01L29/66242 , H01L29/66742 , H01L29/7378
摘要： There is provided a semiconductor wafer having a base wafer, an insulating layer, and a SixGe1-x crystal layer (0≦x
摘要翻译：提供了具有基片，绝缘层和SixGe1-x晶层（0＆amp; nlE; x <1）的半导体晶片。在此，至少将SixGe1-x晶体层（0＆nlE; x <1）的部分区域进行退火，半导体晶片包括具有晶格匹配或者与所述至少部分晶格匹配的伪晶格的化合物半导体 6Ge1-x晶体层的区域（0＆nlE; x <1）。此外，提供了一种电子器件，其包括衬底，设置在衬底上的绝缘层，设置在绝缘层上的SixGe1-x晶体层（0＆lt; nlE; x <1），至少部分地形成SixGe1-x晶体已经进行退火的层（0＆amp; nlE; x <1），具有与SixGe1-x晶体层（0＆amp; nlE; x <1）的至少部分区域具有晶格匹配或伪晶格的化合物半导体，以及使用该化合物半导体形成的半导体器件。

33. 发明授权

US07904765B2 Test apparatus and test method 有权
标题翻译：试验装置及试验方法
公开(公告)号：US07904765B2
公开(公告)日：2011-03-08
申请号：US11857449
申请日：2007-09-19
申请人： Masahiko Hata , Shinya Sato
发明人： Masahiko Hata , Shinya Sato
IPC分类号： G11C29/38 , G11C29/50
CPC分类号： G11C29/56 , G11C16/04 , G11C29/006 , G11C2029/0401 , G11C2029/5602
摘要： Provided is a test apparatus including: test signal supply sections supplying a test signal writing test data to the connected memory under test, to a terminal of the memory; terminal correspondence determination sections outputting a terminal unit determination result indicating whether test data from the connected terminal matches an expected value; a determination result selection section selecting, for each memory, terminal unit determination results from the terminal correspondence determination sections; a memory correspondence determination section determining whether writing succeeded to each memory, based on the selection result by the determination result selection section; an identifying section identifying a test signal supply section connected to the memory to which writing succeeded and a test signal supply section connected to the memory to which writing failed; and a mask treatment section instructing each test signal supply section whether to perform re-testing, according to whether writing succeeded.
摘要翻译：提供了一种测试装置，包括：测试信号提供部分，将测试信号提供给连接的被测试的存储器，将测试数据写入存储器的终端; 终端对应确定部分，输出指示来自所连接终端的测试数据是否匹配期望值的终端单元确定结果; 确定结果选择部分，从终端对应确定部分为每个存储器选择终端单元确定结果; 存储器对应决定部，基于所述判定结果选择部的选择结果，确定是否对每个存储器进行写入; 识别部分，识别连接到写入成功的存储器的测试信号提供部分和连接到写入失败的存储器的测试信号提供部分; 以及掩模处理部，根据写入是否成功指示每个测试信号提供部分是否执行重新测试。

34. 发明授权

US07595259B2 Method for manufacturing compound semiconductor substrate with pn junction 有权
标题翻译：具有pn结的化合物半导体衬底的方法
公开(公告)号：US07595259B2
公开(公告)日：2009-09-29
申请号：US11597711
申请日：2005-05-27
申请人： Kenji Kohiro , Kazumasa Ueda , Masahiko Hata
发明人： Kenji Kohiro , Kazumasa Ueda , Masahiko Hata
IPC分类号： H01L21/4763
CPC分类号： H01L29/861 , H01L21/02395 , H01L21/02463 , H01L21/02546 , H01L21/0262 , H01L21/02639 , H01L21/02661 , H01L29/66136
摘要： A compound semiconductor substrate manufacturing method suitable for manufacturing a compound semiconductor element having high electrical characteristics. The compound semiconductor substrate manufacturing method is a method for manufacturing a compound semiconductor substrate having pn junction, including an epitaxial growing process, a selective growing process and other discretionary processes after the epitaxial growing process. The highest temperatures in the selective growing process and other discretionary processes after the epitaxial growing process are lower than that in the epitaxial growing process prior to the selective growing process.
摘要翻译：一种适用于制造具有高电特性的化合物半导体元件的化合物半导体衬底制造方法。化合物半导体衬底制造方法是在外延生长工艺之后制造具有pn结的化合物半导体衬底的方法，包括外延生长工艺，选择性生长工艺和其它任意处理。选择性生长过程中的最高温度和外延生长过程之后的其他任意处理比在选择性生长过程之前的外延生长过程中的温度低。

35. 发明申请

US20070232018A1 Method for Manufacturing Compound Semiconductor Substrated with Pn Junction 有权
标题翻译：用Pn结形成的复合半导体制造方法
公开(公告)号：US20070232018A1
公开(公告)日：2007-10-04
申请号：US11597711
申请日：2005-05-27
申请人： Kenji Kohiro , Kazumasa Ueda , Masahiko Hata
发明人： Kenji Kohiro , Kazumasa Ueda , Masahiko Hata
IPC分类号： H01L21/20
CPC分类号： H01L29/861 , H01L21/02395 , H01L21/02463 , H01L21/02546 , H01L21/0262 , H01L21/02639 , H01L21/02661 , H01L29/66136
摘要： A compound semiconductor substrate manufacturing method suitable for manufacturing a compound semiconductor element having high electrical characteristics. The compound semiconductor substrate manufacturing method is a method for manufacturing a compound semiconductor substrate having pn junction, including an epitaxial growing process, a selective growing process and other discretionary processes after the epitaxial growing process. The highest temperatures in the selective growing process and other discretionary processes after the epitaxial growing process are lower than that in the epitaxial growing process prior to the selective growing process.
摘要翻译：一种适用于制造具有高电特性的化合物半导体元件的化合物半导体衬底制造方法。化合物半导体衬底制造方法是在外延生长工艺之后制造具有pn结的化合物半导体衬底的方法，包括外延生长工艺，选择性生长工艺和其它任意处理。选择性生长过程中的最高温度和外延生长过程之后的其他任意处理比在选择性生长过程之前的外延生长过程中的温度低。

36. 发明申请

US20070158684A1 Compound semiconductor, method of producing the same, and compound semiconductor device 审中-公开
标题翻译：化合物半导体及其制造方法以及化合物半导体装置
公开(公告)号：US20070158684A1
公开(公告)日：2007-07-12
申请号：US10560160
申请日：2004-05-24
申请人： Kenji Kohiro , Kazumasa Ueda , Toshimitsu Abe , Masahiko Hata
发明人： Kenji Kohiro , Kazumasa Ueda , Toshimitsu Abe , Masahiko Hata
IPC分类号： H01L31/00
CPC分类号： H01L29/7783 , H01L21/02395 , H01L21/02461 , H01L21/02463 , H01L21/02505 , H01L21/02546 , H01L21/0262
摘要： An InGaP buffer layer (3) is formed on a semi-insulating GaAs substrate (1) to a thickness of not less than 5 nm and not greater than 500 nm and an InAlAs layer (4) and an InGaAs channel layer (5) are grown thereon to form a heterostructure. An In segregation effect occurs at the time of forming the InGaP buffer layer (3), so that the region of the InGaP buffer layer (3) near the layer above becomes excessive in In. As a result, the composition of the surface of the InGaP buffer layer (3) becomes very close to the composition of InP, thereby suppressing occurrence of misfit dislocations that can result in degradation of the surface condition. Further, the surface condition of the InAlAs layer (4) and InGaAs channel layer (5) formed thereon can be made good.
摘要翻译：在半绝缘GaAs衬底（1）上形成厚度不小于5nm且不大于500nm的InGaP缓冲层（3），并且InAlAs层（4）和InGaAs沟道层（5）为在其上生长以形成异质结构。在形成InGaP缓冲层（3）时发生An偏析效应，使得In附近的InGaP缓冲层（3）的区域变得过大。结果，InGaP缓冲层（3）的表面的组成变得非常接近InP的组成，从而抑制可能导致表面状态劣化的失配位错的发生。此外，可以使形成在其上的InAlAs层（4）和InGaAs沟道层（5）的表面状态良好。

37. 发明申请

US20070082467A1 Method for manufacturing compound semiconductor substrate 审中-公开
标题翻译：化合物半导体基板的制造方法
公开(公告)号：US20070082467A1
公开(公告)日：2007-04-12
申请号：US10577069
申请日：2004-10-25
申请人： Masahiko Hata , Yoshinobu Ono , Kazumasa Ueda
发明人： Masahiko Hata , Yoshinobu Ono , Kazumasa Ueda
IPC分类号： H01L21/20 , H01L21/36 , H01L31/20 , H01L21/30 , H01L21/46
CPC分类号： H01L29/66462 , H01L21/2007 , H01L29/2003
摘要： The present invention provides a method for manufacturing a compound semiconductor substrate. The method for manufacturing a compound semiconductor substrate comprises the steps of: (a) epitaxially growing a compound semiconductor functional layer 2 on a substrate 1, (b) bonding a support substrate 3 to the compound semiconductor functional layer 2, (c) polishing the substrate 1 and a part of the compound semiconductor functional layer 2 on the side which is in contact with the substrate 1, to remove them, (d) bonding a thermally conductive substrate 4 having a thermal conductivity higher than that of the substrate 1 to the exposed surface of the compound semiconductor functional layer 2 which is provided in the step (c) to obtain a multilayer substrate and (d) separating the support substrate 3 from the multilayer substrate.
摘要翻译：本发明提供一种化合物半导体衬底的制造方法。制造化合物半导体衬底的方法包括以下步骤：（a）在衬底1上外延生长化合物半导体功能层2，（b）将支撑衬底3接合到化合物半导体功能层2，（c）基板1和与基板1接触的一侧的化合物半导体功能层2的一部分，以除去它们;（d）将具有比基板1的导热率高的导热性基板4接合到在步骤（c）中提供的化合物半导体功能层2的暴露表面以获得多层基板，以及（d）将支撑基板3与多层基板分离。

38. 发明授权

US5603764A Process for crystal growth of III-V group compound semiconductor 失效
标题翻译： III-V族化合物半导体的晶体生长工艺
公开(公告)号：US5603764A
公开(公告)日：1997-02-18
申请号：US368872
申请日：1995-01-05
申请人： Yoshinobu Matsuda , Masahiko Hata , Noboru Fukuhara , Toshio Ishihara
发明人： Yoshinobu Matsuda , Masahiko Hata , Noboru Fukuhara , Toshio Ishihara
IPC分类号： H01L21/205 , C30B25/02 , C30B29/40
CPC分类号： C30B25/02 , C30B29/40
摘要： A process for crystal growth of III-V group compound semiconductor, which comprises pyrolyzing, in a gas phase, a material consisting of an organometallic compound and/or a hydride in the presence of an organic compound containing an oxygen atom-carbon atom direct bond, used as a dopant to grow a III-V group compound semiconductor crystal layer containing at least aluminum, of high electric resistance. Said process can grow a compound semiconductor layer of high electric resistance by the use of a dopant which enables the independent controls of oxygen concentration and aluminum concentration and which has a small effect of oxygen remaining.
摘要翻译： III-V族化合物半导体的晶体生长方法，其包括在气相中，在含有氧原子 - 碳原子直接键的有机化合物存在下，由有机金属化合物和/或氢化物组成的材料热解用作掺杂剂以生长具有高电阻的至少含有铝的III-V族化合物半导体晶体层。所述方法可以通过使用能够独立控制氧浓度和铝浓度并且具有小的氧剩余效果的掺杂剂来生长高电阻的化合物半导体层。

39. 发明授权

US5064778A Vapor-phase epitaxial growth method 失效
标题翻译：蒸气相外延生长法
公开(公告)号：US5064778A
公开(公告)日：1991-11-12
申请号：US472153
申请日：1990-01-30
申请人： Takayoshi Maeda , Masahiko Hata , Noboru Fukuhara , Tadeshi Watanabe
发明人： Takayoshi Maeda , Masahiko Hata , Noboru Fukuhara , Tadeshi Watanabe
IPC分类号： C30B25/02 , H01L21/205 , H01L21/20
CPC分类号： C30B25/02 , C30B29/40 , H01L21/02395 , H01L21/02463 , H01L21/02546 , H01L21/02576 , H01L21/0262 , Y10S148/065 , Y10S148/11
摘要： A vapor-phase epitaxial growth method for producing a Groups III-V compound semiconductor containing arsenic by vapor-phase epitaxial growth using arsenic trihydride as an arsenic source is disclosed, wherein said arsenic trihydride has a volatile impurity concentration of not more than 1.5 molppb on a germanium tetrahydride conversion. The resulting epitaxial crystal has a low residual carrier concentration and is applicable to a field effect transistor.

40. 发明授权

US09112035B2 Semiconductor substrate, field-effect transistor, integrated circuit, and method for fabricating semiconductor substrate 有权
标题翻译：半导体衬底，场效晶体管，集成电路以及半导体衬底的制造方法
公开(公告)号：US09112035B2
公开(公告)日：2015-08-18
申请号：US13410872
申请日：2012-03-02
申请人： Hisashi Yamada , Masahiko Hata , Masafumi Yokoyama , Mitsuru Takenaka , Shinichi Takagi , Tetsuji Yasuda , Hideki Takagi , Yuji Urabe
发明人： Hisashi Yamada , Masahiko Hata , Masafumi Yokoyama , Mitsuru Takenaka , Shinichi Takagi , Tetsuji Yasuda , Hideki Takagi , Yuji Urabe
IPC分类号： H01L29/02 , H01L29/786 , H01L21/762 , H01L29/49 , H01L29/51 , H01L29/66
CPC分类号： H01L29/78681 , H01L21/76251 , H01L21/76256 , H01L29/4966 , H01L29/517 , H01L29/66742
摘要： A semiconductor substrate includes a substrate, an insulating layer, and a semiconductor layer. The insulating layer is over and in contact with the substrate. The insulating layer includes at least one of an amorphous metal oxide and an amorphous metal nitride. The semiconductor layer is over and in contact with the insulating layer. The semiconductor layer is formed by crystal growth.
摘要翻译：半导体衬底包括衬底，绝缘层和半导体层。绝缘层在衬底上并与衬底接触。绝缘层包括无定形金属氧化物和无定形金属氮化物中的至少一种。半导体层在绝缘层上方并与之接触。半导体层通过晶体生长形成。

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