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31. 发明申请

US20070266228A1 BLOCK-BASED BRANCH TARGET ADDRESS CACHE 审中-公开
标题翻译：基于块的分支目标地址高速缓存
公开(公告)号：US20070266228A1
公开(公告)日：2007-11-15
申请号：US11382527
申请日：2006-05-10
申请人： Rodney Smith , James Dieffenderfer , Thomas Sartorius
发明人： Rodney Smith , James Dieffenderfer , Thomas Sartorius
IPC分类号： G06F15/00
CPC分类号： G06F9/3806 , G06F9/3836
摘要： A Branch Target Address Cache (BTAC) stores a plurality of entries, each BTAC entry associated with a block of two or more instructions that includes at least one branch instruction having been evaluated taken. The BTAC entry includes an indicator of which instruction within the associated block is a taken branch instruction. The BTAC entry also includes the Branch Target Address (BTA) of the taken branch. The block size may, but does not necessarily, correspond to the number of instructions per instruction cache line.
摘要翻译：分支目标地址缓存（BTAC）存储多个条目，每个BTAC条目与包括已经被评估的至少一个分支指令的两个或更多个指令的块相关联。 BTAC条目包括关联块内哪个指令是采取的分支指令的指示符。 BTAC条目还包括采集分支的分行目标地址（BTA）。块大小可以但不一定对应于每条指令高速缓存线的指令数。

32. 发明申请

US20050108497A1 Translation look aside buffer (TLB) with increased translational capacity for multi-threaded computer processes 失效
标题翻译：翻译看起来缓冲区（TLB）具有增加的多线程计算机进程的平移能力
公开(公告)号：US20050108497A1
公开(公告)日：2005-05-19
申请号：US10714282
申请日：2003-11-14
申请人： Jeffrey Bridges , Les DeBruyne , Robert Goldiez , Michael McIlvaine , Thomas Sartorius , Rodney Smith
发明人： Jeffrey Bridges , Les DeBruyne , Robert Goldiez , Michael McIlvaine , Thomas Sartorius , Rodney Smith
IPC分类号： G06F9/355 , G06F9/38 , G06F12/08 , G06F12/10
CPC分类号： G06F12/1036 , G06F9/342 , G06F9/3851
摘要： Method and apparatus for increasing the number of real memory addresses accessible through a translational look-aside buffer (TLB) by a multi thread CPU. The buffer entries include a virtual address, a real address and a special mode bit indicating whether the address represents one of a plurality of threads being processed by the CPU. If the special mode bit is set, the real address associated with the virtual address higher order bits are concatenated with the thread identification number being processed to obtain a real address. Buffer entries containing no special mode bit, or special mode bit set to 0, are processed by using the full length of the real address associated with the virtual address stored in the look-aside buffer (TLB).
摘要翻译：用于通过多线程CPU通过翻译后备缓冲器（TLB）来访问的实际存储器地址的数量的方法和装置。缓冲器条目包括虚地址，实地址和特殊模式位，指示地址是否表示CPU正在处理的多个线程中的一个。如果设置了特殊模式位，则与虚拟地址较高位相关联的实际地址与被处理的线程标识号连接以获得实际地址。通过使用与存储在后备缓冲区（TLB）中的虚拟地址相关联的实际地址的全长处理不包含特殊模式位或特殊模式位设置为0的缓冲区条目。

33. 发明申请

US20050060518A1 Speculative instruction issue in a simultaneously multithreaded processor 失效
标题翻译：同时多线程处理器中的推测性指令问题
公开(公告)号：US20050060518A1
公开(公告)日：2005-03-17
申请号：US10664384
申请日：2003-09-17
申请人： Victor Augsburg , Jeffrey Bridges , Michael McIlvaine , Thomas Sartorius , Rodney Smith
发明人： Victor Augsburg , Jeffrey Bridges , Michael McIlvaine , Thomas Sartorius , Rodney Smith
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/3836 , G06F9/3826 , G06F9/3851
摘要： A method for optimizing throughput in a microprocessor that is capable of processing multiple threads of instructions simultaneously. Instruction issue logic is provided between the input buffers and the pipeline of the microprocessor. The instruction issue logic speculatively issues instructions from a given thread based on the probability that the required operands will be available when the instruction reaches the stage in the pipeline where they are required. Issue of an instruction is blocked if the current pipeline conditions indicate that there is a significant probability that the instruction will need to stall in a shared resource to wait for operands. Once the probability that the instruction will stall is below a certain threshold, based on current pipeline conditions, the instruction is allowed to issue.
摘要翻译：一种用于优化微处理器中能够同时处理多个指令线程的吞吐量的方法。在输入缓冲器和微处理器的流水线之间提供指令发生逻辑。指令问题逻辑根据当指令到达需要的流水线中的阶段时，基于所需操作数将可用的概率来推测来自给定线程的指令。如果当前流水线条件表明指令需要在共享资源中停止以等待操作数的重要概率，则指令的发出被阻止。一旦指令停顿的概率低于某个阈值，则根据当前流水线条件，允许发出指令。

34. 发明申请

US20060218354A1 Global modified indicator to reduce power consumption on cache miss 有权
标题翻译：全局修改指标，以降低高速缓存未命中的功耗
公开(公告)号：US20060218354A1
公开(公告)日：2006-09-28
申请号：US11088383
申请日：2005-03-23
申请人： Thomas Sartorius , Victor Augsburg , James Dieffenderfer
发明人： Thomas Sartorius , Victor Augsburg , James Dieffenderfer
IPC分类号： G06F12/00 , G06F1/32
CPC分类号： G06F12/0804 , G06F2212/1028 , Y02D10/13
摘要： A processor includes a cache memory having at least one entry managed according to a copy-back algorithm. A global modified indicator (GMI) indicates whether any copy-back entry in the cache contains modified data. On a cache miss, if the GMI indicates that no copy-back entry in the cache contains modified data, data fetched from memory are written to the selected entry without first reading the entry. In a banked cache, two or more bank-GMIs may be associated with two or more banks. In an n-way set associative cache, n set-GMIs may be associated with the n sets. Suppressing the read to determine if the copy-back cache entry contains modified data improves processor performance and reduces power consumption.
摘要翻译：处理器包括具有根据回写算法管理的至少一个条目的高速缓冲存储器。全局修改指示符（GMI）指示高速缓存中是否有任何复制条目包含修改的数据。在缓存未命中时，如果GMI指示高速缓存中没有复制条目包含已修改的数据，则从内存中读取的数据将被写入所选条目，而无需先读入条目。在一个银行缓存中，两个或多个银行GMI可以与两个或更多个银行相关联。在n路集合关联高速缓存中，n个集合GMI可以与n个集合相关联。禁止读取以确定复制缓存条目是否包含修改的数据是否能够提高处理器性能并降低功耗。

35. 发明申请

US20060218335A1 Minimizing memory barriers when enforcing strongly-ordered requests in a weakly-ordered processing system 有权
公开(公告)号：US20060218335A1
公开(公告)日：2006-09-28
申请号：US11254939
申请日：2005-10-20
申请人： Richard Hofmann , James Dieffenderfer , Thomas Sartorius , Thomas Speier , Jaya Subramaniam Ganasan
发明人： Richard Hofmann , James Dieffenderfer , Thomas Sartorius , Thomas Speier , Jaya Subramaniam Ganasan
IPC分类号： G06F13/00
CPC分类号： G06F13/1621
摘要： The disclosure is directed to a weakly-ordered processing system and method for enforcing strongly-ordered memory access requests in a weakly-ordered processing system. The processing system includes a plurality of memory devices and a plurality of processors. A bus interconnect is configured to interface the processors to the memory devices. The bus interconnect is further configured to enforce an ordering constraint for a strongly-ordered memory access request from an originating processor to a target memory device by sending a memory barrier to each of the other memory devices accessible by the originating processor, except for those memory devices that the bus interconnect can confirm have no unexecuted memory access requests from the originating processor.

36. 发明申请

US20060282829A1 Method and apparatus for managing instruction flushing in a microprocessor's instruction pipeline 有权
标题翻译：用于在微处理器指令管线中管理指令冲洗的方法和装置
公开(公告)号：US20060282829A1
公开(公告)日：2006-12-14
申请号：US11149773
申请日：2005-06-10
申请人： Michael Mcllvaine , James Dieffenderfer , Thomas Sartorius
发明人： Michael Mcllvaine , James Dieffenderfer , Thomas Sartorius
IPC分类号： G06F9/44
CPC分类号： G06F9/3861 , G06F9/30072 , G06F9/3867 , G06F12/0855 , G06F12/0862 , G06F2212/6028
摘要： In one or more embodiments, a processor includes one or more circuits to flush instructions from an instruction pipeline on a selective basis responsive to detecting a branch misprediction, such that those instructions marked as being dependent on the branch instruction associated with the branch misprediction are flushed. Thus, the one or more circuits may be configured to mark instructions fetched into the processor's instruction pipeline(s) to indicate their branch prediction dependencies, directly or indirectly detect incorrect branch predictions, and directly or indirectly flush instructions in the instruction pipeline(s) that are marked as being dependent on an incorrect branch prediction.
摘要翻译：在一个或多个实施例中，处理器包括一个或多个电路，用于响应于检测到分支错误预测而选择性地刷新来自指令流水线的指令，使得标记为依赖于与分支错误预测相关联的分支指令的那些指令被刷新。因此，一个或多个电路可以被配置为标记被提取到处理器的指令流水线中以指示其分支预测依赖性的指令，直接或间接地检测不正确的分支预测，以及直接或间接地刷新指令流水线中的指令，被标记为依赖于不正确的分支预测。

37. 发明申请

US20060218358A1 Enforcing strongly-ordered requests in a weakly-ordered processing system 有权
标题翻译：在弱有序的处理系统中执行强有序的请求
公开(公告)号：US20060218358A1
公开(公告)日：2006-09-28
申请号：US11253307
申请日：2005-10-19
申请人： Richard Hofmann , Thomas Sartorius , Thomas Speier , Jaya Subramaniam Ganasan , James Dieffenderfer , James Sullivan
发明人： Richard Hofmann , Thomas Sartorius , Thomas Speier , Jaya Subramaniam Ganasan , James Dieffenderfer , James Sullivan
IPC分类号： G06F13/00 , G06F12/00
CPC分类号： G06F13/1621
摘要： The disclosure is directed to a weakly-ordered processing system and method for enforcing strongly-ordered memory access requests in a weakly-ordered processing system. The processing system includes a plurality of memory devices and a plurality of processors. Each of the processors are configured to generate memory access requests to one or more of the memory devices, with each of the memory access requests having an attribute that can be asserted to indicate a strongly-ordered request. The processing system further includes a bus interconnect configured to interface the processors to the memory devices, the bus interconnect being further configured to enforce ordering constraints on the memory access requests based on the attributes.
摘要翻译：本公开涉及一种用于在弱有序处理系统中强制执行强有序存储器访问请求的弱有序处理系统和方法。处理系统包括多个存储器件和多个处理器。每个处理器被配置为生成对一个或多个存储器设备的存储器访问请求，其中每个存储器访问请求具有可以被断言以指示强有序请求的属性。处理系统还包括被配置为将处理器与存储器设备接口的总线互连，总线互连还被配置为基于属性来强制对存储器访问请求的排序限制。

38. 发明申请

US20050055655A1 System on a chip bus with automatic pipeline stage insertion for timing closure 失效
标题翻译：系统具有自动流水线插入的片上总线，用于定时关闭
公开(公告)号：US20050055655A1
公开(公告)日：2005-03-10
申请号：US10971947
申请日：2004-10-22
申请人： Victor Augsburg , James Dieffenderfer , Bernard Drerup , Richard Hofmann , Thomas Sartorius , Barry Wolford
发明人： Victor Augsburg , James Dieffenderfer , Bernard Drerup , Richard Hofmann , Thomas Sartorius , Barry Wolford
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5045
摘要： A method of designing a system on a chip (SoC) to operate with varying latencies and frequencies. A layout of the chip is designed with specific placement of devices, including a bus controller, initiator, and target devices. The time for a signal to propagate from a source device to a destination device is determined relative to a default propagation time. A pipeline stage is then inserted into a bus path between said source device and destination device for each additional time the signal takes to propagate. Each device (i.e., initiators, targets, and bus controller) is designed with logic to control a protocol that functions with a variety of response latencies. With the additional logic, the devices do not need to be changed when pipeline stages are inserted in the various paths. Registers are utilized as the pipeline stages that are inserted within the paths.
摘要翻译：一种设计芯片上的系统（SoC）以在不同的延迟和频率下工作的方法。芯片的布局设计具有特定的器件布局，包括总线控制器，启动器和目标器件。相对于默认传播时间确定信号从源设备传播到目的地设备的时间。然后，在信号需要传播的每个附加时间，将流水线级插入到所述源设备和目的设备之间的总线路径中。每个设备（即，启动器，目标和总线控制器）被设计为具有控制以各种响应延迟起作用的协议的逻辑。使用附加逻辑，当管道级插入各种路径时，不需要更改设备。寄存器被用作插入到路径内的流水线级。

39. 发明申请

US20080109610A1 SELECTIVE SNOOPING BY SNOOP MASTERS TO LOCATE UPDATED DATA 失效
标题翻译：由SNOOP主人选择性地选择更新数据
公开(公告)号：US20080109610A1
公开(公告)日：2008-05-08
申请号：US11970599
申请日：2008-01-08
申请人： James Dieffenderfer , Bernard Drerup , Jaya Ganasan , Richard Hofmann , Thomas Sartorius , Thomas Speier , Barry Wolford
发明人： James Dieffenderfer , Bernard Drerup , Jaya Ganasan , Richard Hofmann , Thomas Sartorius , Thomas Speier , Barry Wolford
IPC分类号： G06F12/00
CPC分类号： G06F12/0831 , Y02D10/13
摘要： A method and structure for snooping cache memories of several snooping masters connected to a bus macro, wherein each non-originating snooping master has cache memory, and wherein some, but less than all the cache memories, may have the data requested by an originating snooping master and wherein the needed data in a non-originating snooping master is marked as updated, and wherein a main memory having addresses for all data is connected to the bus macro. Only those non-originating snooping masters which may have the requested data are queried. All the non-originating snooping masters that have been queried reply. If a non-originating snooping master has the requested data marked as updated, that non-originating snooping master returns the updated data to the originating snooping master and possibly to the main memory. If none of the non-originating snooping masters has the requested data marked as updated, then the requested data is read from main memory.
摘要翻译：一种用于窥探连接到总线宏的多个窥探主机的高速缓冲存储器的方法和结构，其中每个非起始侦听主机具有高速缓冲存储器，并且其中一些但是小于所有高速缓存存储器可以具有由始发侦听器请求的数据主站，并且其中非起始侦听主控器中的所需数据被标记为更新，并且其中具有用于所有数据的地址的主存储器连接到总线宏。只有那些可能具有请求的数据的非始发侦听主机才被查询。所有被查询的非始发侦听主人都回复。如果非始发侦听主机具有被标记为更新的请求数据，则该非起始侦听主机会将更新的数据返回给始发侦听主机，并将其返回到主内存。如果非始发侦听主机中没有一个被标记为已更新的请求数据，则从主存储器读取所请求的数据。

40. 发明申请

US20070094430A1 Method and apparatus to clear semaphore reservation 有权
标题翻译：清除信号量保留的方法和装置
公开(公告)号：US20070094430A1
公开(公告)日：2007-04-26
申请号：US11254391
申请日：2005-10-20
申请人： Thomas Speier , James Dieffenderfer , Thomas Sartorius , Jaya Prakash Ganasan
发明人： Thomas Speier , James Dieffenderfer , Thomas Sartorius , Jaya Prakash Ganasan
IPC分类号： G06F12/14
CPC分类号： G06F9/526
摘要： Semaphore operation manages exclusive access to a memory that is shared by a plurality of processing elements. Semaphore reservation status for exclusive access by a processing element is monitored by a memory controller. To clear an obsolete reservation status, a command signal is transmitted for a write operation to the memory while prohibiting update of the contents of a memory. The reservation status at the controller is changed from a reservation state to a non-reservation state in response to receipt of the command signal.
摘要翻译：信号量操作管理对由多个处理元件共享的存储器的独占访问。由处理元件独占访问的信号量预留状态由存储器控制器监视。为了清除过时的预约状态，在禁止更新存储器的内容的同时，向存储器发送用于写入操作的命令信号。响应于接收到命令信号，控制器的预约状态从预约状态改变为非预约状态。

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