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31. 发明授权

US5145795A Semiconductor device and method therefore 失效
标题翻译：半导体器件及其方法
公开(公告)号：US5145795A
公开(公告)日：1992-09-08
申请号：US543233
申请日：1990-06-25
申请人： Paul W. Sanders , Bernard W. Boland
发明人： Paul W. Sanders , Bernard W. Boland
IPC分类号： H01L21/762
CPC分类号： H01L21/76297 , H01L2224/48091 , H01L2224/73265 , H01L2924/1305 , H01L2924/13091 , H01L2924/30107 , H01L2924/3011 , Y10S148/168 , Y10S438/977
摘要： An improved high frequency dielectrically isolated (DIC) transistor (100) or integrated circuit is obtained by providing a highly doped single crystal semiconductor region (112) coupled to the device reference terminal (16') and extending between front (98) and rear (61) faces of the semiconductor die. This allows the reference terminal (16', 116) to be coupled to the package ground plane without use of wire bonds, thereby lowering the common mode impedance. The desired structure is formed in connection with DIC devices (100) by etching first (66) and second (77) nested cavities into a single crystal substrate (60). The cavities (66) form protruding islands (821, 822) of single crystal semiconductor having a height (80+68) about equal the final die thickness (110) and which, after conventional DIC processing using an oxide isolation layer (86) and a poly handle (88), are exposed by grinding away the poly handle (88) to expose the highly doped, single crystal reference terminal feed-through (112).
摘要翻译：通过提供耦合到器件参考端子（16'）并在前面（98）和后面（98）之间延伸的高掺杂单晶半导体区域（112），获得改进的高频介电隔离（DIC）晶体管（100）或集成电路 61）面。这允许参考端子（16'，116）在不使用引线接合的情况下耦合到封装接地层，从而降低共模阻抗。通过将第一（66）和第二（77）嵌套空穴蚀刻到单晶衬底（60）中，与DIC器件（100）相关地形成期望的结构。空腔（66）形成高度（80 + 68）的大约等于最终管芯厚度（110）的单晶半导体的突出岛（821,822），并且在使用氧化物隔离层（86）的常规DIC处理和通过研磨多晶硅手柄（88）以暴露高度掺杂的单晶参考端子馈通（112）来暴露多晶硅手柄（88）。

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