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31. 发明授权

US09490264B2 Device having a contact between semiconductor regions through a buried insulating layer, and process for fabricating said device 有权
标题翻译：具有通过掩埋绝缘层的半导体区域之间的接触的器件，以及用于制造所述器件的工艺
公开(公告)号：US09490264B2
公开(公告)日：2016-11-08
申请号：US12984466
申请日：2011-01-04
申请人： Carlos Mazure , Richard Ferrant
发明人： Carlos Mazure , Richard Ferrant
IPC分类号： H01L21/331 , H01L21/8222 , H01L27/12 , H01L21/74 , H01L21/84 , H01L27/108 , H01L29/732 , H01L29/78 , H01L29/786
CPC分类号： H01L27/1203 , H01L21/743 , H01L21/84 , H01L27/10802 , H01L27/10873 , H01L29/732 , H01L29/7841 , H01L29/78639
摘要： The invention relates to a semiconductor device produced on a semiconductor-on-insulator substrate that includes a thin layer of semiconductor material separated from a base substrate by a buried insulating layer, the device including a first conducting region in the thin layer, a second conducting region in the base substrate and a contact connecting the first region to the second region through the insulating layer. The invention also relates to a process for fabricating such semiconductor devices.
摘要翻译：本发明涉及一种在绝缘体上半导体衬底上制造的半导体器件，其包括通过掩埋绝缘层与基底衬底分离的半导体材料的薄层，该器件包括薄层中的第一导电区域，第二导电层区域和通过绝缘层将第一区域连接到第二区域的接触。本发明还涉及制造这种半导体器件的方法。

32. 发明授权

US09159400B2 Semiconductor memory having staggered sense amplifiers associated with a local column decoder 有权
标题翻译：具有与本地列解码器相关联的交错读出放大器的半导体存储器
公开(公告)号：US09159400B2
公开(公告)日：2015-10-13
申请号：US13422697
申请日：2012-03-16
申请人： Richard Ferrant , Gerhard Enders , Carlos Mazure
发明人： Richard Ferrant , Gerhard Enders , Carlos Mazure
IPC分类号： G11C7/06 , G11C11/4091 , G11C11/4097
CPC分类号： G11C11/4091 , G11C7/065 , G11C11/4097
摘要： A semiconductor memory having bit lines and wordlines crossing each other, a memory cell array formed by memory cells arranged in rows and columns on crossover points of the bit lines and wordlines, and sense amplifier banks arranged on opposite sides of the memory cell array. Each sense amplifier bank has staggered sense amplifiers connected to a bit line according to an interleaved arrangement whereby bit lines alternate in the direction of the wordlines between bit lines coupled to different sense amplifiers. This results in interconnect spaces parallel to the bit lines. Also, each sense amplifier bank includes a local column decoder for selecting a sense amplifier and which is staggered with the sense amplifiers and coupled to the sense amplifier by an output line running in an available interconnect space parallel to the bit lines.
摘要翻译：具有彼此交叉的位线和字线的半导体存储器，由位线和字线的交叉点上以列和列排列的存储单元形成的存储单元阵列以及布置在存储单元阵列的相对侧上的读出放大器组。每个读出放大器组具有根据交错布置连接到位线的交错读出放大器，由此位线在耦合到不同读出放大器的位线之间的字线方向上交替。这导致互连空间与位线平行。此外，每个读出放大器组包括本地列解码器，用于选择读出放大器，并与读出放大器交错，并通过在平行于位线的可用互连空间中运行的输出线耦合到读出放大器。

33. 发明授权

US09111593B2 Differential sense amplifier without dedicated precharge transistors 有权
标题翻译：差分放大器，无专用预充电晶体管
公开(公告)号：US09111593B2
公开(公告)日：2015-08-18
申请号：US13456057
申请日：2012-04-25
申请人： Richard Ferrant , Roland Thewes
发明人： Richard Ferrant , Roland Thewes
IPC分类号： G11C7/00 , G11C7/06 , G11C7/12 , G11C11/4091 , G11C11/4094
CPC分类号： G11C7/065 , G11C7/12 , G11C11/4091 , G11C11/4094
摘要： The invention relates to a differential sense amplifier for sensing data stored in a plurality of memory cells of a memory cell array, including a first CMOS inverter having an output connected to a first bit line and an input connected to a second bit line complementary to the first bit line, and a second CMOS inverter having an output connected to the second bit line and an input connected to the first bit line (BL). Each CMOS inverter includes a pull-up transistor and a pull-down transistor, with the sense amplifier having a pair of precharge transistors arranged to be respectively coupled to the first and second bit lines, to precharge the first and second bit lines to a precharge voltage. The precharge transistors are constituted by the pull-up transistors or by the pull-down transistors.
摘要翻译：本发明涉及用于感测存储在存储单元阵列的多个存储器单元中的数据的差分读出放大器，包括具有连接到第一位线的输出的第一CMOS反相器和连接到与第一位线互补的第二位线的输入第一位线和第二CMOS反相器，其具有连接到第二位线的输出和连接到第一位线（BL）的输入。每个CMOS反相器包括一个上拉晶体管和一个下拉晶体管，其中读出放大器具有一对分别耦合到第一和第二位线的预充电晶体管，以将第一和第二位线预充电到预充电电压。预充电晶体管由上拉晶体管或下拉晶体管构成。

34. 发明授权

US08654602B2 Pseudo-inverter circuit on SeOI 有权
标题翻译： SeOI上的伪逆变电路
公开(公告)号：US08654602B2
公开(公告)日：2014-02-18
申请号：US13495632
申请日：2012-06-13
申请人： Carlos Mazure , Richard Ferrant , Bich-Yen Nguyen
发明人： Carlos Mazure , Richard Ferrant , Bich-Yen Nguyen
IPC分类号： G11C8/00
CPC分类号： G11C8/08 , G11C11/4085 , G11C2211/4016
摘要： A circuit made on a semiconductor-on-insulator substrate. The circuit includes a first transistor having a first channel, a second transistor having a second channel, with the transistors provided in serial association between first and second terminals for applying a power supply potential, each of the transistors comprising a drain region and a source region in the thin layer, a channel extending between the source region and the drain region, and a front control gate located above the channel. Each transistor has a back control gate formed in the base substrate below the channel of the transistor and capable of being biased in order to modulate the threshold voltage of the transistor. At least one of the transistors is configured for operating in a depletion mode under the action of a back gate signal which will sufficiently modulate its threshold voltage.
摘要翻译：在绝缘体上半导体衬底上制成的电路。该电路包括具有第一通道的第一晶体管，具有第二通道的第二晶体管，晶体管以第一和第二端子串联连接的方式提供，以施加电源电位，每个晶体管包括漏极区域和源极区域在薄层中，在源极区域和漏极区域之间延伸的沟道以及位于沟道上方的前部控制栅极。每个晶体管具有形成在晶体管的沟道下方的基底衬底中的背控制栅极，并且能够被偏置以便调制晶体管的阈值电压。晶体管中的至少一个被配置为在充分调制其阈值电压的背栅信号的作用下以耗尽模式工作。

35. 发明授权

US08508289B2 Data-path cell on an SeOI substrate with a back control gate beneath the insulating layer 有权
标题翻译： SeOI衬底上的数据通道单元，在绝缘层下面带有一个后控制栅极
公开(公告)号：US08508289B2
公开(公告)日：2013-08-13
申请号：US13013580
申请日：2011-01-25
申请人： Carlos Mazure , Richard Ferrant
发明人： Carlos Mazure , Richard Ferrant
IPC分类号： G05F1/10 , H01L27/105 , G06F17/50
CPC分类号： H01L21/84 , H01L27/0207 , H01L27/11807 , H01L27/1203
摘要： This invention provides a semiconductor device structure formed on a conventional semiconductor-on-insulator (SeOI) substrate defined by a pattern defining at least one field-effect transistor having: in the thin film of the SeOI substrate, a source region, a drain region, a channel region, and a front control gate region formed above the channel region; and in the base substrate beneath the buried oxide of the SeOI substrate, a back control gate region, arranged under the channel region and configured to shift the threshold voltage of the transistor in response to bias voltages. This invention also provides patterns defining standard-cell-type circuit structures and data-path-cell type circuit structures that include arrays of the FET patterns provided by this invention. Such circuit structures also include back gate lines connecting the back gate control regions. This invention also provides methods of operating and designing such semiconductor device structures.
摘要翻译：本发明提供了一种半导体器件结构，其形成在传统的绝缘体上半导体（SeOI）衬底上，该衬底由限定至少一个场效应晶体管的图案限定，该场效应晶体管具有：在SeOI衬底的薄膜中，源极区，，沟道区和形成在沟道区上方的前控制栅区; 以及位于所述SeOI衬底的所述掩埋氧化物之下的所述基底衬底中，所述背面控制栅极区域布置在所述沟道区域下方并且被配置为响应于偏压而移位所述晶体管的阈值电压。本发明还提供了定义包括由本发明提供的FET图案的阵列的标准单元型电路结构和数据路径单元型电路结构的图案。这种电路结构还包括连接背栅极控制区域的后栅极线。本发明还提供了操作和设计这种半导体器件结构的方法。

36. 发明申请

US20110242926A1 PSEUDO-INVERTER CIRCUIT ON SeO1 有权
标题翻译： PSO1上的PSEUDO-INVERTER电路
公开(公告)号：US20110242926A1
公开(公告)日：2011-10-06
申请号：US12793553
申请日：2010-06-03
申请人： Carlos Mazure , Richard Ferrant , Bich-Yen Nguyen
发明人： Carlos Mazure , Richard Ferrant , Bich-Yen Nguyen
IPC分类号： G11C8/08 , G05F1/10
CPC分类号： G11C8/08 , G11C11/4085 , G11C2211/4016
摘要： A circuit made on a semiconductor-on-insulator substrate. The circuit includes a first transistor having a first channel, a second transistor having a second channel, with the transistors provided in serial association between first and second terminals for applying a power supply potential, each of the transistors comprising a drain region and a source region in the thin layer, a channel extending between the source region and the drain region, and a front control gate located above the channel. Each transistor has a back control gate formed in the base substrate below the channel of the transistor and capable of being biased in order to modulate the threshold voltage of the transistor. At least one of the transistors is configured for operating in a depletion mode under the action of a back gate signal which will sufficiently modulate its threshold voltage.
摘要翻译：在绝缘体上半导体衬底上制成的电路。该电路包括具有第一通道的第一晶体管，具有第二通道的第二晶体管，晶体管以第一和第二端子串联连接的方式提供，以施加电源电位，每个晶体管包括漏极区域和源极区域在薄层中，在源极区域和漏极区域之间延伸的沟道以及位于沟道上方的前部控制栅极。每个晶体管具有形成在晶体管的沟道下方的基底衬底中的背控制栅极，并且能够被偏置以便调制晶体管的阈值电压。晶体管中的至少一个被配置为在充分调制其阈值电压的背栅信号的作用下以耗尽模式工作。

37. 发明申请

US20090121269A1 INTEGRATED CIRCUIT COMPRISING A TRANSISTOR AND A CAPACITOR, AND FABRICATION METHOD 有权
标题翻译：包含晶体管和电容器的集成电路，以及制造方法
公开(公告)号：US20090121269A1
公开(公告)日：2009-05-14
申请号：US12173702
申请日：2008-07-15
申请人： Christian Caillat , Richard Ferrant
发明人： Christian Caillat , Richard Ferrant
IPC分类号： H01L27/108 , H01L21/8242
CPC分类号： H01L27/10823 , H01L27/0218 , H01L27/10829 , H01L27/10876 , H01L27/10885 , H01L27/1203
摘要： An integrated circuit includes a substrate and at least one active region. A transistor produced in the active region separated from the substrate. This transistor includes a source or drain first region and a drain or source second region which are connected by a channel. A gate structure is position on top of said channel and operates to control the channel. The gate structure is formed in a trench whose sidewalls have a shape which converges (narrows) in the width dimension towards the substrate. A capacitor is also formed having a first electrode, a second electrode and a dielectric layer between the electrodes. This capacitor is also formed in a trench. An electrode line is connected to the first electrode of the capacitor. The second electrode of the capacitor is formed in a layer shared in common with at least part of the drain or source second region of the transistor. A bit line is located beneath the gate structure. The integrated circuit may, for example, be a DRAM memory cell.
摘要翻译：集成电路包括衬底和至少一个有源区。在与基板分离的有源区中产生的晶体管。该晶体管包括源极或漏极第一区域以及通过沟道连接的漏极或源极第二区域。栅极结构位于所述通道的顶部并且用于控制通道。栅极结构形成在其侧壁具有朝向衬底的宽度尺寸收敛（窄））的形状的沟槽中。电容器也形成为具有在电极之间的第一电极，第二电极和电介质层。该电容器也形成在沟槽中。电极线连接到电容器的第一电极。电容器的第二电极形成在与晶体管的漏极或源极第二区域的至少一部分共同共享的层中。位线位于门结构下方。集成电路例如可以是DRAM存储单元。

38. 发明申请

US20080251848A1 Manufacturing method for homogenizing the environment of transistors and associated device 审中-公开
标题翻译：晶体管和相关器件的环境均匀化的制造方法
公开(公告)号：US20080251848A1
公开(公告)日：2008-10-16
申请号：US12082630
申请日：2008-04-11
申请人： Bertrand Borot , Richard Ferrant
发明人： Bertrand Borot , Richard Ferrant
IPC分类号： H01L29/00 , H01L21/336
CPC分类号： H01L27/0705 , H01L27/0207 , H01L27/088 , H01L27/11803 , H01L27/11807
摘要： A semiconductor device is provided that includes a plurality of patterns. Each pattern includes at least one field effect transistor. Each field effect transistor includes a source region, a drain region, a channel region, and a gate region formed above the channel region. A portion of the plurality of patterns is formed in a single active area of a semiconductor substrate, where the area delimited by an isolation region. One of the source region and the drain region of each adjacent pattern are formed in said active area.
摘要翻译：提供了包括多个图案的半导体器件。每个图案包括至少一个场效应晶体管。每个场效应晶体管包括源极区，漏极区，沟道区和形成在沟道区上方的栅极区。多个图案的一部分形成在半导体衬底的单个有源区域中，其中由隔离区限定的区域。每个相邻图案的源极区域和漏极区域之一形成在所述有源区域中。

39. 发明申请

US20080205114A1 Semiconductor memory device and method of operating same 有权
标题翻译：半导体存储器件及其操作方法
公开(公告)号：US20080205114A1
公开(公告)日：2008-08-28
申请号：US12082020
申请日：2008-04-08
申请人： Richard Ferrant , Serguei Okhonin , Eric Carman , Michel Bron
发明人： Richard Ferrant , Serguei Okhonin , Eric Carman , Michel Bron
IPC分类号： G11C5/06
CPC分类号： G11C11/404 , G11C7/18 , G11C8/08 , G11C11/406 , G11C11/40618 , G11C11/4097 , G11C2211/4016 , G11C2211/4065 , H01L21/84 , H01L27/10802 , H01L27/10844 , H01L27/1203 , H01L29/7841
摘要： There are many inventions described and illustrated herein. In a first aspect, the present invention is directed to a memory device and technique of reading data from and writing data into memory cells of the memory device. In this regard, in one embodiment of this aspect of the invention, the memory device and technique for operating that device that minimizes, reduces and/or eliminates the debilitating affects of the charge pumping phenomenon. This embodiment of the present invention employs control signals that minimize, reduce and/or eliminate transitions of the amplitudes and/or polarities. In another embodiment, the present invention is a semiconductor memory device including a memory array comprising a plurality of semiconductor dynamic random access memory cells arranged in a matrix of rows and columns. Each semiconductor dynamic random access memory cell includes a transistor having a source region, a drain region, a electrically floating body region disposed between and adjacent to the source region and the drain region, and a gate spaced apart from, and capacitively coupled to, the body region. Each transistor includes a first state representative of a first charge in the body region, and a second data state representative of a second charge in the body region. Further, each row of semiconductor dynamic random access memory cells includes an associated source line which is connected to only the semiconductor dynamic random access memory cells of the associated row.
摘要翻译：这里描述和说明了许多发明。在第一方面，本发明涉及一种从数据读取和将数据写入存储器件的存储单元的存储器件和技术。在这方面，在本发明的这个方面的一个实施例中，用于操作该装置的存储器件和技术使得最小化，减少和/或消除电荷泵送现象的衰弱影响。本发明的该实施例采用最小化，减少和/或消除幅度和/或极性的转变的控制信号。在另一个实施例中，本发明是一种包括存储阵列的半导体存储器件，该存储器阵列包括以行和列为矩阵排列的多个半导体动态随机存取存储器单元。每个半导体动态随机存取存储单元包括晶体管，其具有源极区，漏极区，设置在源极区和漏极区之间且与源极区和漏极区相邻的电浮动体区域，以及与该区域和漏极区域间隔开并电容耦合的栅极身体区域。每个晶体管包括代表身体区域中的第一电荷的第一状态和代表身体区域中的第二电荷的第二数据状态。此外，每排半导体动态随机存取存储器单元包括仅与相关行的半导体动态随机存取存储单元连接的相关联的源极线。

40. 发明授权

US07359229B2 Semiconductor memory device and method of operating same 有权
公开(公告)号：US07359229B2
公开(公告)日：2008-04-15
申请号：US11713284
申请日：2007-03-02
申请人： Richard Ferrant , Serguei Okhonin , Eric Carman , Michel Bron
发明人： Richard Ferrant , Serguei Okhonin , Eric Carman , Michel Bron
IPC分类号： G11C5/06 , G11C7/00
CPC分类号： G11C11/404 , G11C7/18 , G11C8/08 , G11C11/406 , G11C11/40618 , G11C11/4097 , G11C2211/4016 , G11C2211/4065 , H01L21/84 , H01L27/10802 , H01L27/10844 , H01L27/1203 , H01L29/7841
摘要： There are many inventions described and illustrated herein. In a first aspect, the present invention is directed to a memory device and technique of reading data from and writing data into memory cells of the memory device. In this regard, in one embodiment of this aspect of the invention, the memory device and technique for operating that device that minimizes, reduces and/or eliminates the debilitating affects of the charge pumping phenomenon. This embodiment of the present invention employs control signals that minimize, reduce and/or eliminate transitions of the amplitudes and/or polarities. In another embodiment, the present invention is a semiconductor memory device including a memory array comprising a plurality of semiconductor dynamic random access memory cells arranged in a matrix of rows and columns. Each semiconductor dynamic random access memory cell includes a transistor having a source region, a drain region, a electrically floating body region disposed between and adjacent to the source region and the drain region, and a gate spaced apart from, and capacitively coupled to, the body region. Each transistor includes a first state representative of a first charge in the body region, and a second data state representative of a second charge in the body region. Further, each row of semiconductor dynamic random access memory cells includes an associated source line which is connected to only the semiconductor dynamic random access memory cells of the associated row.

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