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1. 发明申请

US20100246237A1 ANTI-FUSE ELEMENT 有权
标题翻译：抗保护元件
公开(公告)号：US20100246237A1
公开(公告)日：2010-09-30
申请号：US12679278
申请日：2007-10-03
申请人： Bertrand Borot , Michel Zecri
发明人： Bertrand Borot , Michel Zecri
IPC分类号： G11C17/00 , H01H37/76
CPC分类号： G11C17/16 , G11C17/18
摘要： Programmable anti-fuse circuitry including at least one anti-fuse cell having a first anti-fuse device coupled between a supply voltage and a first node and a second anti-fuse device coupled between the first node and a ground voltage, and control logic coupled to the first node and arranged to generate a programming voltage having one of at least a first voltage level for breaking-down the first anti-fuse device but not the second anti-fuse device and coupling the first node to the supply voltage; and a second voltage level for breaking-down the second anti-fuse device but not the first anti-fuse device and coupling the first node to the ground voltage.
摘要翻译：可编程抗熔丝电路包括至少一个具有耦合在电源电压和第一节点之间的第一反熔丝器件和耦合在第一节点与地电压之间的第二反熔丝器件的反熔丝电池，以及控制逻辑耦合并且布置成产生具有至少第一电压电平之一的编程电压，用于分解第一反熔丝器件而不是第二反熔丝器件，并将第一节点耦合到电源电压; 以及用于分解第二反熔丝器件而不是第一反熔丝器件并将第一节点耦合到接地电压的第二电压电平。

2. 发明申请

US20070297253A1 MEASURING CIRCUIT FOR QUALIFYING A MEMORY LOCATED ON A SEMICONDUCTOR DEVICE 有权
标题翻译：测量位于半导体器件上的存储器的电路
公开(公告)号：US20070297253A1
公开(公告)日：2007-12-27
申请号：US11750456
申请日：2007-05-18
申请人： David Turgis , Bertrand Borot
发明人： David Turgis , Bertrand Borot
IPC分类号： G11C29/00
CPC分类号： G11C29/50 , G11C29/50012 , G11C2029/0401
摘要： A measuring circuit is provided for a memory integrated within a semiconductor device. The measuring circuit includes initializing means and an oscillating loop. The initializing means loadings two complementary values into at least two locations of the memory. The two locations are addressed by a first address and a second address. The oscillating loop comprises a logic circuit for alternatively generating the first address and the second address from data read from the memory so as to successively read data from the first and second memory locations to produce an oscillating signal that has a frequency that depends on internal parameters of the memory. Also provided is a method for qualifying a memory by initializing the memory by loading two complementary values into two locations, and generating an oscillating signal with a frequency that is dependent on internal parameters of the memory.
摘要翻译：为集成在半导体器件内的存储器提供测量电路。测量电路包括初始化装置和振荡环路。初始化装置将两个互补值加载到存储器的至少两个位置。两个位置由第一地址和第二地址寻址。振荡回路包括逻辑电路，用于从存储器读取的数据交替地产生第一地址和第二地址，从而连续地从第一和第二存储器位置读取数据，以产生具有取决于内部参数的频率的振荡信号的记忆。还提供了一种通过将两个互补值加载到两个位置来初始化存储器并且产生具有取决于存储器的内部参数的频率的振荡信号来限定存储器的方法。

3. 发明授权

US08254198B2 Anti-fuse element 有权
标题翻译：防熔丝元件
公开(公告)号：US08254198B2
公开(公告)日：2012-08-28
申请号：US12679278
申请日：2007-10-03
申请人： Bertrand Borot , Michel Zecri
发明人： Bertrand Borot , Michel Zecri
IPC分类号： G11C17/18 , G11C17/00 , H01H37/76
CPC分类号： G11C17/16 , G11C17/18
摘要： Programmable anti-fuse circuitry including at least one anti-fuse cell having a first anti-fuse device coupled between a supply voltage and a first node and a second anti-fuse device coupled between the first node and a ground voltage, and control logic coupled to the first node and arranged to generate a programming voltage having one of at least a first voltage level for breaking-down the first anti-fuse device but not the second anti-fuse device and coupling the first node to the supply voltage; and a second voltage level for breaking-down the second anti-fuse device but not the first anti-fuse device and coupling the first node to the ground voltage.
摘要翻译：可编程抗熔丝电路包括至少一个具有耦合在电源电压和第一节点之间的第一反熔丝器件和耦合在第一节点与地电压之间的第二反熔丝器件的反熔丝电池，以及控制逻辑耦合并且布置成产生具有至少第一电压电平之一的编程电压，用于分解第一反熔丝器件而不是第二反熔丝器件，并将第一节点耦合到电源电压; 以及用于分解第二反熔丝器件而不是第一反熔丝器件并将第一节点耦合到接地电压的第二电压电平。

4. 发明授权

US07755960B2 Memory including a performance test circuit 有权
标题翻译：内存包括一个性能测试电路
公开(公告)号：US07755960B2
公开(公告)日：2010-07-13
申请号：US12333426
申请日：2008-12-12
申请人： Bertrand Borot , Emmanuel Bechet
发明人： Bertrand Borot , Emmanuel Bechet
IPC分类号： G11C29/00
CPC分类号： G11C29/50 , G11C11/41 , G11C29/24 , G11C29/50012
摘要： A memory includes a plurality of memory cells each including a true data input connected to a true bit line and complementary data input connected to a complementary bit line, and two inverters connected head-to-tail firstly to the true data input and secondly to the complementary data input. The memory also includes a test circuit includes a plurality of test cells, each test cell includes a true data input connected to a complementary data input of the preceding test cell and a complementary data input connected to the true data input of the following test cell, the complementary data input of the last test cell being connected to the true data input of the first test cell, each test cell comprising a first inverter connected between the true data input and the complementary data input. The looped chain thus formed propagates a signal whose period is a function of the performance of the storage cells.
摘要翻译：存储器包括多个存储单元，每个存储单元包括连接到真位线的真实数据输入和连接到互补位线的互补数据输入，以及两个逆变器，其首先连接到真实数据输入端，其次是至补充数据输入。存储器还包括测试电路，其包括多个测试单元，每个测试单元包括连接到前一测试单元的互补数据输入端的真实数据输入端和连接到以下测试单元的真实数据输入端的互补数据输入端，最后一个测试单元的互补数据输入被连接到第一测试单元的真实数据输入，每个测试单元包括连接在真实数据输入和互补数据输入之间的第一反相器。如此形成的环形链传播其周期是存储单元的性能的函数的信号。

5. 发明授权

US07989914B2 Anti-fuse cell and its manufacturing process 有权
标题翻译：反熔丝电池及其制造工艺
公开(公告)号：US07989914B2
公开(公告)日：2011-08-02
申请号：US11793990
申请日：2005-12-23
申请人： Bertrand Borot , Roberto Maurizio Gonella , Sébastien Fabre
发明人： Bertrand Borot , Roberto Maurizio Gonella , Sébastien Fabre
IPC分类号： H01L29/00 , H01L21/44
CPC分类号： H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： An anti-fuse cell includes a standard MOS transistor of an integrated circuit, with source and drain regions covered with a metal silicide layer and at least one track of a resistive layer at least partially surrounding the MOS transistor, and adapted to pass a heating current such that the metal of said metal silicide diffuses across drain and/or source junctions.
摘要翻译：反熔丝单元包括集成电路的标准MOS晶体管，其源极和漏极区域被金属硅化物层覆盖，并且至少一个至少部分围绕MOS晶体管的电阻层的轨道，并且适于使加热电流使得所述金属硅化物的金属扩散穿过漏极和/或源极结。

6. 发明授权

US07884635B2 Integrated circuit, system and method including a performance test mode 有权
标题翻译：集成电路，系统和方法包括性能测试模式
公开(公告)号：US07884635B2
公开(公告)日：2011-02-08
申请号：US12033483
申请日：2008-02-19
申请人： Bertrand Borot , Emmanuel Bechet
发明人： Bertrand Borot , Emmanuel Bechet
IPC分类号： H03K19/00
CPC分类号： G01R31/318594 , G01R31/31725 , G01R31/318536
摘要： An integrated circuit includes N configurable cells each including one functional input, one output, one propagation input and one output. The circuit includes a functional mode in which the N configurable cells are coupled by their functional input and their output to logic blocks with which they cooperate to form at least one logic circuit. The disclosed circuit also includes a test mode in which the N configurable cells are coupled by their propagation input and their output to the logic blocks and in which the output of the Nth configurable cell is coupled to a functional input of the first logic block to form an oscillator.
摘要翻译：集成电路包括N个可配置单元，每个可配置单元包括一个功能输入，一个输出，一个传播输入和一个输出。该电路包括功能模式，其中N个可配置单元通过它们的功能输入耦合，并且它们的输出与它们协作的逻辑块形成至少一个逻辑电路。所公开的电路还包括测试模式，其中N个可配置单元通过其传播输入耦合，并且其输出耦合到逻辑块，并且其中第N个可配置单元的输出耦合到第一逻辑块的功能输入以形成一个振荡器。

7. 发明申请

US20090154273A1 MEMORY INCLUDING A PERFORMANCE TEST CIRCUIT 有权
标题翻译：内存包括性能测试电路
公开(公告)号：US20090154273A1
公开(公告)日：2009-06-18
申请号：US12333426
申请日：2008-12-12
申请人： Bertrand Borot , Emmanuel Bechet
发明人： Bertrand Borot , Emmanuel Bechet
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G11C29/50 , G11C11/41 , G11C29/24 , G11C29/50012
摘要： A memory includes a plurality of memory cells each including a true data input connected to a true bit line and complementary data input connected to a complementary bit line, and two inverters connected head-to-tail firstly to the true data input and secondly to the complementary data input. The memory also includes a test circuit includes a plurality of test cells, each test cell includes a true data input connected to a complementary data input of the preceding test cell and a complementary data input connected to the true data input of the following test cell, the complementary data input of the last test cell being connected to the true data input of the first test cell, each test cell comprising a first inverter connected between the true data input and the complementary data input. The looped chain thus formed propagates a signal whose period is a function of the performance of the storage cells.
摘要翻译：存储器包括多个存储单元，每个存储单元包括连接到真位线的真实数据输入和连接到互补位线的互补数据输入，以及两个逆变器，其首先连接到真实数据输入端，其次是至补充数据输入。存储器还包括测试电路，其包括多个测试单元，每个测试单元包括连接到前一测试单元的互补数据输入端的真实数据输入端和连接到以下测试单元的真实数据输入端的互补数据输入端，最后一个测试单元的互补数据输入被连接到第一测试单元的真实数据输入，每个测试单元包括连接在真实数据输入和互补数据输入之间的第一反相器。如此形成的环形链传播其周期是存储单元的性能的函数的信号。

8. 发明申请

US20090102014A1 Anti-Fuse Cell and Its Manufacturing Process 有权
标题翻译：防熔电池及其制造工艺
公开(公告)号：US20090102014A1
公开(公告)日：2009-04-23
申请号：US11793990
申请日：2005-12-23
申请人： Bertrand Borot , Roberto Maurizio Gonella , Sebastien Fabre
发明人： Bertrand Borot , Roberto Maurizio Gonella , Sebastien Fabre
IPC分类号： H01L23/525 , H01L21/44 , H01L21/336
CPC分类号： H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： An anti-fuse cell includes a standard MOS transistor of an integrated circuit, with source and drain regions covered with a metal silicide layer and at least one track of a resistive layer at least partially surrounding the MOS transistor, and adapted to pass a heating current such that the metal of said metal silicide diffuses across drain and/or source junctions.
摘要翻译：反熔丝单元包括集成电路的标准MOS晶体管，其源极和漏极区域被金属硅化物层覆盖，并且至少一个至少部分围绕MOS晶体管的电阻层的轨道，并且适于使加热电流使得所述金属硅化物的金属扩散穿过漏极和/或源极结。

9. 发明授权

US07320923B2 SRAM cell 有权
标题翻译： SRAM单元
公开(公告)号：US07320923B2
公开(公告)日：2008-01-22
申请号：US11305553
申请日：2005-12-16
申请人： Bertrand Borot , Philippe Coronel
发明人： Bertrand Borot , Philippe Coronel
IPC分类号： H01L21/331
CPC分类号： G11C11/412 , H01L27/11 , H01L27/1104
摘要： A method for forming a resistor of high value in a semiconductor substrate including forming a stack of a first insulating layer, a first conductive layer, a second insulating layer, and a third insulating layer, the third insulating layer being selectively etchable with respect to the second insulating layer; etching the stack, to expose the substrate and keep the stack in the form of a line; forming insulating spacers on the lateral walls of the line; performing an epitaxial growth of a single-crystal semiconductor on the substrate, on either side of the line; selectively removing the third insulating layer to partially expose the second insulating layer at a predetermined location; and depositing and etching a conductive material to fill the cavity formed by the previous removal of the third insulating layer.
摘要翻译：一种在包括形成第一绝缘层，第一导电层，第二绝缘层和第三绝缘层的堆叠的半导体衬底中形成高值电阻器的方法，所述第三绝缘层可相对于所述第一绝缘层，第二绝缘层; 蚀刻堆叠，露出衬底并将堆叠保持为线的形式; 在该线的侧壁上形成绝缘垫片; 在衬底的两侧进行单晶半导体的外延生长; 选择性地去除所述第三绝缘层以在预定位置部分地暴露所述第二绝缘层; 以及沉积和蚀刻导电材料以填充由先前去除第三绝缘层形成的空腔。

10. 发明申请

US20100187638A1 ANTI-FUSE CELL AND ITS MANUFACTURING PROCESS 审中-公开
标题翻译：防冻细胞及其制造方法
公开(公告)号：US20100187638A1
公开(公告)日：2010-07-29
申请号：US11722974
申请日：2005-12-23
申请人： Bertrand Borot , Roberto Maurizio Gonella , Sebastien Fabre
发明人： Bertrand Borot , Roberto Maurizio Gonella , Sebastien Fabre
IPC分类号： H01L23/525 , H01L21/768
CPC分类号： H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： An anti-fuse cell includes a standard MOS transistor of an integrated circuit, with source (7) and drain (8) regions covered with a metal silicide layer (12, 13), and at least one track (24) of a resistive layer at least partially surrounding said MOS transistor, and adapted to pass a heating current such that the metal of said metal silicide diffuses across drain and/or source junctions.
摘要翻译：反熔丝单元包括集成电路的标准MOS晶体管，源极（7）和漏极（8）区域被金属硅化物层（12,13）覆盖，以及至少一个电阻层的轨道（24）至少部分地围绕所述MOS晶体管，并且适于通过加热电流，使得所述金属硅化物的金属扩散穿过漏极和/或源极结。

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