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31. 发明申请

US20120043592A1 SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME 有权
标题翻译：半导体器件及其形成方法
公开(公告)号：US20120043592A1
公开(公告)日：2012-02-23
申请号：US13132985
申请日：2011-02-23
申请人： Chao Zhao , Wenwu Wang , Huilong Zhu
发明人： Chao Zhao , Wenwu Wang , Huilong Zhu
IPC分类号： H01L29/772 , H01L21/768
CPC分类号： H01L23/485 , H01L21/76847 , H01L23/53238 , H01L23/53252 , H01L23/53266 , H01L29/78 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a semiconductor device. The semiconductor device comprises contact plugs that comprise a first contact plug formed by a first barrier layer arranged on the source and drain regions and a tungsten layer arranged on the first barrier layer; and second contact plugs comprising a second barrier layer arranged on both of the metal gate and the first contact plug and a conductive layer arranged on the second barrier layer. The conductivity of the conductive layer is higher than that of the tungsten layer. A method for forming the semiconductor device is also provided. The present invention provides the advantage of enhancing the reliability of the device when using the copper contact technique.
摘要翻译：本发明提供一种半导体器件。半导体器件包括接触插塞，其包括由布置在源区和漏区上的第一阻挡层和布置在第一阻挡层上的钨层形成的第一接触插塞; 以及第二接触插塞，其包括布置在金属栅极和第一接触插塞两者上的第二阻挡层和布置在第二阻挡层上的导电层。导电层的导电性高于钨层。还提供了一种用于形成半导体器件的方法。本发明提供了当使用铜接触技术时提高器件的可靠性的优点。

32. 发明授权

US09224589B2 Method for eliminating contact bridge in contact hole process 有权
标题翻译：消除接触孔过程中的接触桥的方法
公开(公告)号：US09224589B2
公开(公告)日：2015-12-29
申请号：US13497768
申请日：2011-11-28
申请人： Guilei Wang , Junfeng Li , Chao Zhao
发明人： Guilei Wang , Junfeng Li , Chao Zhao
IPC分类号： H01L21/02 , H01L21/768 , C23C16/44 , C23C16/30 , C23C16/34 , C23C16/40 , C23C16/505 , C23C16/56
CPC分类号： H01L21/02 , C23C16/308 , C23C16/345 , C23C16/402 , C23C16/4404 , C23C16/505 , C23C16/56 , H01L21/76837
摘要： A method for eliminating contact bridge in a contact hole process is disclosed, wherein a cleaning menu comprising a multi-step adaptive protective thin film deposition process is provided, so that a stack adaptive protective thin film is formed on the sidewall of the chamber of the HDP CVD equipment. The stack adaptive protective thin film has good adhesivity, compactness and uniformity to protect the sidewall of the chamber of the HDP CVD equipment from being damaged by the plasma, and avoid the generation of defect particles, thereby improving the HDP CVD technical yield and eliminating the contact bridge phenomenon in the contact hole process.
摘要翻译：公开了一种用于消除接触孔工艺中的接触桥的方法，其中提供了包括多步自适应保护薄膜沉积工艺的清洁菜单，使得堆叠自适应保护薄膜形成在腔室的侧壁上 HDP CVD设备。叠层自适应保护薄膜具有良好的粘合性，紧凑性和均匀性，以保护HDP CVD设备室的侧壁不被等离子体损坏，并避免产生缺陷颗粒，从而提高HDP CVD技术产量并消除接触孔过程中的接触桥现象。

33. 发明申请

US20150035087A1 Method for Manufacturing Dummy Gate in Gate-Last Process and Dummy Gate in Gate-Last Process 有权
标题翻译：闸门最后过程中虚拟门制造方法及闸门最后过程中虚拟门的制作方法
公开(公告)号：US20150035087A1
公开(公告)日：2015-02-05
申请号：US14119864
申请日：2012-12-12
申请人： Chunlong Li , Junfeng Li , Jiang Yan , Chao Zhao
发明人： Chunlong Li , Junfeng Li , Jiang Yan , Chao Zhao
IPC分类号： H01L29/66 , H01L29/51 , H01L29/423
CPC分类号： H01L29/66545 , H01L21/28123 , H01L29/42364 , H01L29/513 , H01L29/518
摘要： A method for manufacturing a dummy gate in a gate-last process and a dummy gate in a gate-last process are provided. The method includes: providing a semiconductor substrate; growing a gate oxide layer on the semiconductor substrate; depositing bottom-layer amorphous silicon on the gate oxide layer; depositing an ONO structured hard mask on the bottom-layer amorphous silicon; depositing top-layer amorphous silicon on the ONO structured hard mask; depositing a hard mask layer on the top-layer amorphous silicon; forming photoresist lines on the hard mask layer, and trimming the formed photoresist lines so that the trimmed photoresist lines a width less than or equal to 22 nm; and etching the hard mask layer, the top-layer amorphous silicon, the ONO structured hard mask and the bottom-layer amorphous silicon in accordance with the trimmed photoresist lines, and removing the photoresist lines, the hard mask layer and the top-layer amorphous silicon.
摘要翻译：提供了一种在门最后处理中制造伪栅极的方法和在栅极最后工艺中的伪栅极。该方法包括：提供半导体衬底; 在半导体衬底上生长栅极氧化层; 在栅极氧化物层上沉积底层非晶硅; 在底层非晶硅上沉积ONO结构的硬掩模; 在ONO结构化的硬掩模上沉积顶层非晶硅; 在顶层非晶硅上沉积硬掩模层; 在硬掩模层上形成光致抗蚀剂线，并修整所形成的光致抗蚀剂线，使得修整的光致抗蚀剂线的宽度小于或等于22nm; 并根据修整的光致抗蚀剂线蚀刻硬掩模层，顶层非晶硅，ONO结构的硬掩模和底层非晶硅，并除去光致抗蚀剂线，硬掩模层和顶层无定形硅。

34. 发明申请

US20140332958A1 Method for Manufacturing Dummy Gate in Gate-Last Process and Dummy Gate in Gate-Last Process 有权
标题翻译：闸门最后过程中虚拟门制造方法及闸门最后过程中虚拟门的制作方法
公开(公告)号：US20140332958A1
公开(公告)日：2014-11-13
申请号：US14119862
申请日：2012-12-12
申请人： Chunlong Li , Junfeng Li , Jiang Yan , Chao Zhao
发明人： Chunlong Li , Junfeng Li , Jiang Yan , Chao Zhao
IPC分类号： H01L29/66 , H01L29/423 , H01L29/78 , H01L21/28
CPC分类号： H01L29/66545 , H01L21/2807 , H01L21/28123 , H01L29/4232 , H01L29/78
摘要： A method for manufacturing a dummy gate in a gate-last process is provided. The method includes: providing a semiconductor substrate; growing a gate oxide layer on the semiconductor substrate; depositing bottom-layer amorphous silicon on the gate oxide layer; depositing an ONO structured hard mask on the bottom-layer amorphous silicon; depositing top-layer amorphous silicon on the ONO structured hard mask; depositing a hard mask layer on the top-layer amorphous silicon; forming photoresist lines having a width ranging from 32 nm to 45 nm on the hard mask layer; and etching the hard mask layer, the top-layer amorphous silicon, the ONO structured hard mask and the bottom-layer amorphous silicon in accordance with the photoresist lines, and removing the photoresist lines, the hard mask layer and the top-layer α-Si. Correspondingly, a dummy gate in a gate-last process is also provided.
摘要翻译：提供了一种在门最后工艺中制造虚拟栅极的方法。该方法包括：提供半导体衬底; 在半导体衬底上生长栅极氧化层; 在栅极氧化物层上沉积底层非晶硅; 在底层非晶硅上沉积ONO结构的硬掩模; 在ONO结构化的硬掩模上沉积顶层非晶硅; 在顶层非晶硅上沉积硬掩模层; 在硬掩模层上形成宽度范围为32nm至45nm的光致抗蚀剂线; 根据光致抗蚀剂线蚀刻硬掩模层，顶层非晶硅，ONO结构的硬掩模和底层非晶硅，并除去光致抗蚀剂线，硬掩模层和顶层α- Si。相应地，还提供了最后进程中的虚拟门。

35. 发明授权

US08802518B2 Semiconducor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08802518B2
公开(公告)日：2014-08-12
申请号：US13395608
申请日：2011-10-17
申请人： Wenwu Wang , Chao Zhao , Kai Han , Dapeng Chen
发明人： Wenwu Wang , Chao Zhao , Kai Han , Dapeng Chen
IPC分类号： H01L29/66 , H01L21/8238 , H01L21/28 , H01L29/49 , H01L21/8234 , H01L29/51 , H01L29/423
CPC分类号： H01L21/82345 , H01L21/28114 , H01L21/823468 , H01L21/823828 , H01L21/823842 , H01L21/823864 , H01L29/42376 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/6653 , H01L29/66545 , H01L29/6656
摘要： A semiconductor device and a method for manufacturing the same, the method comprising: providing a semiconductor substrate; forming a dummy gate area on the substrate, forming spacers on sidewalls of the gate area, and forming source and drain areas in the semiconductor substrate on both sides of the dummy gate area, the dummy gate area comprising an interface layer and a dummy gate electrode; forming a dielectric cap layer on the dummy gate area and source and drain areas; planarizing the device with the dielectric cap layer on the source and drain areas as a stop layer; further removing the dummy gate electrode to expose the interface layer; and forming replacement gate area on the interface layer. The thickness of the gate groove may be controlled by the thickness of the dielectric cap layer, and the replacement gates of desired thickness and width may be further formed upon requirements. Thus, the aspect ratio of the gate groove is reduced and a sufficient low gate resistance is ensured.
摘要翻译：一种半导体器件及其制造方法，所述方法包括：提供半导体衬底; 在所述基板上形成虚拟栅极区域，在所述栅极区域的侧壁上形成间隔物，以及在所述伪栅极区域的两侧形成所述半导体基板中的源极和漏极区域，所述伪栅极区域包括界面层和虚拟栅极电极 ; 在虚拟栅极区域和源极和漏极区域上形成电介质盖层; 使源极和漏极区域上的电介质盖层平坦化作为停止层; 进一步去除虚拟栅电极以露出界面层; 并在界面层上形成替换栅区。栅极沟槽的厚度可以通过电介质盖层的厚度来控制，并且可以根据需要进一步形成所需厚度和宽度的替换栅极。因此，栅极沟槽的纵横比减小，并且确保了足够的低栅极电阻。

36. 发明授权

US08703567B2 Method for manufacturing a semiconductor device 有权
标题翻译：半导体器件的制造方法
公开(公告)号：US08703567B2
公开(公告)日：2014-04-22
申请号：US13497744
申请日：2011-11-29
申请人： Guilei Wang , Chunlong Li , Chao Zhao
发明人： Guilei Wang , Chunlong Li , Chao Zhao
IPC分类号： H01L21/336
CPC分类号： H01L29/1054 , H01L29/66651 , H01L29/7833
摘要： The present invention discloses a method for manufacturing a semiconductor device, comprising: forming an insulating isolation layer on a substrate; forming an insulating isolation layer trench in the insulating isolation layer; forming an active region layer in the insulating isolation layer trench; forming a semiconductor device structure in and above the active region layer; characterized in that the carrier mobility of the active region layer is higher than that of the substrate. Said active region is formed of a material different from that of the substrate, the carrier mobility in the channel region is enhanced, thereby the device response speed is improved and the device performance is enhanced. Unlike the existing STI manufacturing process, for the present invention, an STI is formed first, and then filling is performed to form an active region, thus avoiding the problem of generation of holes in STI, and improving the device reliability.
摘要翻译：本发明公开了一种制造半导体器件的方法，包括：在衬底上形成绝缘隔离层; 在绝缘隔离层中形成绝缘隔离层沟槽; 在绝缘隔离层沟槽中形成有源区; 在有源区域层中形成半导体器件结构; 其特征在于，有源区层的载流子迁移率高于基板的载流子迁移率。所述有源区由不同于衬底的材料形成，通道区域中的载流子迁移率增强，从而提高了器件响应速度并提高了器件性能。与现有的STI制造方法不同，对于本发明，首先形成STI，然后进行填充以形成有源区，从而避免STI中产生孔的问题，并提高器件的可靠性。

37. 发明申请

US20130313655A1 SEMICONDUCTOR DEVICE AND A METHOD FOR MANUFACTURING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20130313655A1
公开(公告)日：2013-11-28
申请号：US13878524
申请日：2012-07-18
申请人： Guilei Wang , Hushan Cui , Chao Zhao
发明人： Guilei Wang , Hushan Cui , Chao Zhao
IPC分类号： H01L29/78 , H01L29/66
CPC分类号： H01L29/7846 , H01L29/045 , H01L29/66553 , H01L29/66636
摘要： A semiconductor device comprises a substrate; a shallow trench isolation embedded in the substrate and forms at least one opening region; a channel region located in the opening region; a gate stack including a gate dielectric layer and a gate electrode layer, located above said channel region; a source/drain region located on both sides of the channel region, including a stress layer which provides strain for the channel region. A liner layer is provided between the shallow trench isolation and the stress layer, which serves as a crystal seed layer of the stress layer. A liner layer and a pad oxide layer are provided between the substrate and the shallow trench isolation. The liner layer is inserted between the STI and the stress layer of the source/drain region as a crystal seed layer or nucleating layer for epitaxial growth, thereby eliminating the STI edge effect during the source/drain strain engineering.
摘要翻译：半导体器件包括衬底; 嵌入衬底中的浅沟槽隔离物并形成至少一个开口区域; 位于所述开口区域中的通道区域; 包括位于所述沟道区上方的栅极介质层和栅极电极层的栅极堆叠; 位于沟道区两侧的源/漏区，包括为沟道区提供应变的应力层。衬底层设置在浅沟槽隔离层和应力层之间，其作为应力层的晶种子层。衬底层和衬垫氧化物层设置在衬底和浅沟槽隔离之间。衬垫层作为晶种层或用于外延生长的成核层插入到STI和源极/漏极区的应力层之间，从而消除了源极/漏极应变工程中的STI边缘效应。

38. 发明申请

US20130241004A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20130241004A1
公开(公告)日：2013-09-19
申请号：US13520618
申请日：2012-04-11
申请人： Huaxiang Yin , Zuozhen Fu , Qiuxia Xu , Chao Zhao , Dapeng Chen
发明人： Huaxiang Yin , Zuozhen Fu , Qiuxia Xu , Chao Zhao , Dapeng Chen
IPC分类号： H01L27/088 , H01L21/8236
CPC分类号： H01L21/823807 , H01L21/823842 , H01L29/4966 , H01L29/517 , H01L29/518 , H01L29/66545 , H01L29/7845
摘要： The present invention discloses a semiconductor device, comprising substrates, a plurality of gate stack structures on the substrate, a plurality of gate spacer structures on both sides of each gate stack structure, a plurality of source and drain regions in the substrate on both sides of each gate spacer structure, the plurality of gate spacer structures comprising a plurality of first gate stack structures and a plurality of second gate stack structures, wherein each of the first gate stack structures comprises a first gate insulating layer, a first work function metal layer, a second work function metal diffusion blocking layer, and a gate filling layer; Each of the second gate stack structures comprises a second gate insulating layer, a first work function metal layer, a second work function metal layer, and a gate filling layer, characterized in that the first work function metal layer has a first stress, and the gate filling layer has a second stress. Two metal gate layers of different types and/or intensity of stress are formed, respectively, thus different stresses are applied to the channel regions of different MOSFETs effectively and accurately, the device carrier mobility is enhanced simply and efficiently, and the device performance is also enhanced.
摘要翻译：本发明公开了一种半导体器件，包括衬底，衬底上的多个栅极堆叠结构，在每个栅极堆叠结构的两侧上的多个栅极间隔结构，在衬底的两侧的多个源极和漏极区域每个栅极间隔结构，所述多个栅极间隔结构包括多个第一栅极堆叠结构和多个第二栅极堆叠结构，其中所述第一栅极堆叠结构中的每一个包括第一栅极绝缘层，第一功函数金属层，第二功函数金属扩散阻挡层和栅极填充层; 每个第二栅极堆叠结构包括第二栅极绝缘层，第一功函数金属层，第二功函数金属层和栅极填充层，其特征在于，第一功函数金属层具有第一应力，并且栅极填充层具有第二应力。形成不同类型和/或应力强度的两个金属栅极层，从而有效且准确地对不同MOSFET的沟道区域施加不同的应力，简单高效地提高器件载流子迁移率，器件性能也是增强。

39. 发明申请

US20120178255A1 METHOD FOR IMPROVING WITHIN DIE UNIFORMITY OF METAL PLUG CHEMICAL MECHANICAL PLANARIZATION PROCESS IN GATE LAST ROUTE 有权
标题翻译：用于改善门槛最近路线中金属片化学机械平面化方法的均匀性的方法
公开(公告)号：US20120178255A1
公开(公告)日：2012-07-12
申请号：US13377889
申请日：2011-04-20
申请人： Tao Yang , Chao Zhao , Junfong Li
发明人： Tao Yang , Chao Zhao , Junfong Li
IPC分类号： H01L21/768
CPC分类号： H01L21/7684 , H01L21/3212 , H01L21/32135
摘要： A method for improving the within die uniformity of the metal plug CMP process in the gate last route is provided. Before performing the CMP process for forming the metal plug, a metal etching process is applied, so that the step height between the metal layers in the contact hole area and the non-contact hole area is greatly reduced. Therefore, the relatively small step height will exert a significantly less effect on the following CMP process, so that the step height will be limitedly transferred to the top of metal plug after finishing CMP process. In this way, the recess on top of the metal plug is largely reduced, so that a flat top of the metal plug is obtained, and within die uniformity and electrical properties the device are improved.
摘要翻译：提供了一种用于提高门最后路线中的金属塞CMP工艺的模内均匀性的方法。在进行用于形成金属插塞的CMP处理之前，应用金属蚀刻工艺，使得接触孔区域中的金属层与非接触孔区域之间的台阶高度大大降低。因此，相对较小的台阶高度将对下列CMP工艺产生显着影响较小，因此在完成CMP工艺后，台阶高度将有限地转移到金属插头的顶部。以这种方式，金属插头顶部的凹槽大大减小，从而获得金属插头的平坦的顶部，并且在模具的均匀性和电气特性中改进了该装置。

40. 发明申请

US20100207177A1 METHOD FOR PRODUCING A COPPER CONTACT 审中-公开
标题翻译：生产铜接触方法
公开(公告)号：US20100207177A1
公开(公告)日：2010-08-19
申请号：US12641945
申请日：2009-12-18
申请人： Chung-Shi Liu , Gerald Beyer , Steven Demuynck , Zsolt Tokei , Roger Palmans , Chao Zhao , Chen-Hua Yu
发明人： Chung-Shi Liu , Gerald Beyer , Steven Demuynck , Zsolt Tokei , Roger Palmans , Chao Zhao , Chen-Hua Yu
IPC分类号： H01L23/532 , H01L21/768 , H01L29/78 , H01L23/522
CPC分类号： H01L21/76843 , H01L21/76831 , H01L21/76855 , H01L21/76856 , H01L21/76864 , H01L21/76873 , H01L23/485 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A method for producing a contact through the pre-metal dielectric (PMD) layer of an integrated circuit, between the front end of line and the back end of line, and the device produced thereby are disclosed. The PMD layer includes oxygen. In one aspect, the method includes producing a hole in the PMD, depositing a conductive barrier layer at the bottom of the hole, depositing a CuMn alloy on the bottom and side walls of the hole, filling the remaining portion of the hole with Cu. The method further includes performing an anneal process to form a barrier on the side walls of the hole, wherein the barrier has an oxide including Mn. The method further includes performing a CMP process.
摘要翻译：公开了一种通过集成电路的前金属电介质（PMD）层之间的线的前端和后端之间产生接触的方法以及由此制造的器件。 PMD层包括氧气。一方面，该方法包括在PMD中产生孔，在孔的底部沉积导电阻挡层，在孔的底部和侧壁上沉积CuMn合金，用Cu填充孔的剩余部分。所述方法还包括进行退火处理以在所述孔的侧壁上形成阻挡层，其中所述势垒具有包括Mn的氧化物。该方法还包括执行CMP处理。

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