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31. 发明授权

US08502283B2 Strained fully depleted silicon on insulator semiconductor device 有权
标题翻译：应变完全耗尽的绝缘体上硅绝缘体器件
公开(公告)号：US08502283B2
公开(公告)日：2013-08-06
申请号：US11926655
申请日：2007-10-29
申请人： Qi Xiang , Niraj Subba , Witold P. Maszara , Zoran Krivokapic , Ming-Ren Lin
发明人： Qi Xiang , Niraj Subba , Witold P. Maszara , Zoran Krivokapic , Ming-Ren Lin
IPC分类号： H01L29/78
CPC分类号： H01L29/66772 , H01L29/66636 , H01L29/7842 , H01L29/7848 , H01L29/78639 , H01L29/78684 , Y10S438/938
摘要： A semiconductor substrate is provided having an insulator thereon with a semiconductor layer on the insulator. A deep trench isolation is formed, introducing strain to the semiconductor layer. A gate dielectric and a gate are formed on the semiconductor layer. A spacer is formed around the gate, and the semiconductor layer and the insulator are removed outside the spacer. Recessed source/drain are formed outside the spacer.
摘要翻译：提供了一种在绝缘体上具有半导体层的绝缘体的半导体衬底。形成深沟槽隔离，向半导体层引入应变。栅极电介质和栅极形成在半导体层上。在栅极周围形成间隔物，并且将半导体层和绝缘体去除在间隔物的外部。凹陷的源极/漏极形成在间隔物外部。

32. 发明授权

US08482963B1 Integrated circuits with asymmetric and stacked transistors 有权
标题翻译：具有不对称和堆叠晶体管的集成电路
公开(公告)号：US08482963B1
公开(公告)日：2013-07-09
申请号：US12629831
申请日：2009-12-02
申请人： Jun Liu , Yanzhong Xu , Shankar Sinha , Shih-Lin S. Lee , Jeffrey Xiaoqi Tung , Albert Ratnakumar , Qi Xiang , Irfan Rahim , Andy L. Lee , Jeffrey T. Watt , Srinivas Perisetty
发明人： Jun Liu , Yanzhong Xu , Shankar Sinha , Shih-Lin S. Lee , Jeffrey Xiaoqi Tung , Albert Ratnakumar , Qi Xiang , Irfan Rahim , Andy L. Lee , Jeffrey T. Watt , Srinivas Perisetty
IPC分类号： G11C11/00
CPC分类号： G11C11/412
摘要： Asymmetric transistors may be formed by creating pocket implants on one source-drain terminal of a transistor and not the other. Asymmetric transistors may also be formed using dual-gate structures having first and second gate conductors of different work functions. Stacked transistors may be formed by stacking two transistors of the same channel type in series. One of the source-drain terminals of each of the two transistors is connected to a common node. The gates of the two transistors are also connected together. The two transistors may have different threshold voltages. The threshold voltage of the transistor that is located higher in the stacked transistor may be provided with a lower threshold voltage than the other transistor in the stacked transistor. Stacked transistors may be used to reduce leakage currents in circuits such as memory cells. Asymmetric transistors may also be used in memory cells to reduce leakage.
摘要翻译：不对称晶体管可以通过在晶体管的一个源极 - 漏极端子上而不是另一个产生凹穴注入来形成。也可以使用具有不同功函数的第一和第二栅极导体的双栅结构来形成非对称晶体管。可以通过堆叠相同通道类型的两个晶体管串联形成堆叠晶体管。两个晶体管中的每一个的源极 - 漏极端子之一连接到公共节点。两个晶体管的栅极也连接在一起。两个晶体管可以具有不同的阈值电压。位于堆叠晶体管中较高的晶体管的阈值电压可以具有比堆叠晶体管中的另一个晶体管更低的阈值电压。堆叠的晶体管可用于减少诸如存储器单元的电路中的漏电流。不对称晶体管也可用于存储器单元中以减少泄漏。

33. 发明申请

US20090047770A1 METHOD OF FORMING ISOLATION REGIONS FOR INTEGRATED CIRCUITS 有权
标题翻译：形成集成电路隔离区的方法
公开(公告)号：US20090047770A1
公开(公告)日：2009-02-19
申请号：US12205361
申请日：2008-09-05
申请人： Haihong Wang , Minh-Van Ngo , Qi Xiang , Paul R. Besser , Eric N. Paton , Ming-Ren Lin
发明人： Haihong Wang , Minh-Van Ngo , Qi Xiang , Paul R. Besser , Eric N. Paton , Ming-Ren Lin
IPC分类号： H01L21/76
CPC分类号： H01L21/76224 , H01L21/823481 , H01L29/1054
摘要： A method of manufacturing an integrated circuit (IC) utilizes a shallow trench isolation (STI) technique. The shallow trench isolation technique is used in strained silicon (SMOS) process. The liner for the trench is formed from a semiconductor or metal layer which is deposited in a low temperature process which reduces germanium outgassing. The low temperature process can be a ALD process.
摘要翻译：集成电路（IC）的制造方法利用浅沟槽隔离（STI）技术。浅沟槽隔离技术用于应变硅（SMOS）工艺。用于沟槽的衬垫由半导体或金属层形成，该半导体或金属层在低温过程中沉积，这降低了锗除气。低温过程可以是ALD过程。

34. 发明授权

US07306997B2 Strained fully depleted silicon on insulator semiconductor device and manufacturing method therefor 失效
标题翻译：应变完全耗尽的绝缘体上硅绝缘体器件及其制造方法
公开(公告)号：US07306997B2
公开(公告)日：2007-12-11
申请号：US10986399
申请日：2004-11-10
申请人： Qi Xiang , Niraj Subba , Witold P. Maszara , Zoran Krivokapic , Ming-Ren Lin
发明人： Qi Xiang , Niraj Subba , Witold P. Maszara , Zoran Krivokapic , Ming-Ren Lin
IPC分类号： H01L21/336
CPC分类号： H01L29/66772 , H01L29/66636 , H01L29/7842 , H01L29/7848 , H01L29/78639 , H01L29/78684 , Y10S438/938
摘要： A semiconductor substrate is provided having an insulator thereon with a semiconductor layer on the insulator. A deep trench isolation is formed, introducing strain to the semiconductor layer. A gate dielectric and a gate are formed on the semiconductor layer. A spacer is formed around the gate, and the semiconductor layer and the insulator are removed outside the spacer. Recessed source/drain are formed outside the spacer.
摘要翻译：提供了一种在绝缘体上具有半导体层的绝缘体的半导体衬底。形成深沟槽隔离，向半导体层引入应变。栅极电介质和栅极形成在半导体层上。在栅极周围形成间隔物，并且将半导体层和绝缘体去除在间隔物的外部。凹陷的源极/漏极形成在间隔物外部。

35. 发明授权

US07091097B1 End-of-range defect minimization in semiconductor device 有权
标题翻译：半导体器件的范围内缺陷最小化
公开(公告)号：US07091097B1
公开(公告)日：2006-08-15
申请号：US10933424
申请日：2004-09-03
申请人： Eric N. Paton , Qi Xiang , Cyrus E. Tabery , Bin Yu , Robert B. Ogle
发明人： Eric N. Paton , Qi Xiang , Cyrus E. Tabery , Bin Yu , Robert B. Ogle
IPC分类号： H01L21/336
CPC分类号： H01L21/268 , H01L21/26506 , H01L21/26513 , H01L21/2658 , H01L29/6659 , H01L29/7833
摘要： A method of fabricating a semiconductor device comprises forming a gate electrode over a substrate and forming deep amorphous regions within the substrate. And implanting dopants to form deep source/drain regions at a depth less than that of the deep amorphous regions, partially re-crystallizing portions of the deep amorphous regions to reduce their depth, and re-crystallizing the reduced amorphous regions to form activated final source/drain regions.
摘要翻译：制造半导体器件的方法包括在衬底上形成栅电极并在衬底内形成深非晶区域。并且注入掺杂剂以在深非晶区域的深度处形成深的源极/漏极区域，部分地重新结晶深非晶区域的部分以减小它们的深度，并且将还原的非晶区域再结晶以形成激活的最终光源 /漏区。

36. 发明申请

US20050073022A1 Shallow trench isolation (STI) region with high-K liner and method of formation 失效
标题翻译：浅沟隔离（STI）区域具有高K衬垫和形成方法
公开(公告)号：US20050073022A1
公开(公告)日：2005-04-07
申请号：US10642916
申请日：2003-08-18
申请人： Olov Karlsson , HaiHong Wang , Bin Yu , Zoran Krivokapic , Qi Xiang
发明人： Olov Karlsson , HaiHong Wang , Bin Yu , Zoran Krivokapic , Qi Xiang
IPC分类号： H01L21/762 , H01L21/84 , H01L27/12 , H01L29/786 , H01L29/00
CPC分类号： H01L29/7842 , H01L21/76264 , H01L21/76283 , H01L21/84 , H01L27/1203 , H01L29/78654
摘要： A shallow trench isolation region formed in a layer of semiconductor material. The shallow trench isolation region includes a trench formed in the layer of semiconductor material, the trench being defined by sidewalls and a bottom; a liner within the trench formed from a high-K material, the liner conforming to the sidewalls and bottom of the trench; and a fill section made from isolating material, and disposed within and conforming to the high-K liner. A method of forming the shallow trench isolation region is also disclosed.
摘要翻译：形成在半导体材料层中的浅沟槽隔离区。浅沟槽隔离区域包括形成在半导体材料层中的沟槽，沟槽由侧壁和底部限定; 由高K材料形成的沟槽内的衬垫，衬垫符合沟槽的侧壁和底部; 以及由隔离材料制成并填充并符合高K衬里的填充部分。还公开了形成浅沟槽隔离区域的方法。

37. 发明申请

US20050054164A1 Strained silicon MOSFETs having reduced diffusion of n-type dopants 审中-公开
标题翻译：具有减小的n型掺杂剂扩散的应变硅MOSFET
公开(公告)号：US20050054164A1
公开(公告)日：2005-03-10
申请号：US10658611
申请日：2003-09-09
申请人： Qi Xiang
发明人： Qi Xiang
IPC分类号： H01L21/265 , H01L21/268 , H01L21/336 , H01L29/10
CPC分类号： H01L21/26586 , H01L21/268 , H01L29/1054 , H01L29/665 , H01L29/6659 , H01L29/66772 , H01L29/785
摘要： Processing is performed during fabrication of a strained silicon NMOS device to create point defects in silicon germanium portions of source regions, and optionally of drain regions, prior to activation of source and drain region dopants. The point defects retard diffusion of the n-type dopants in the silicon germanium material, effectively lengthening the duration of the diffusivity transient region and resulting in lower overall dopant diffusivity during activation.
摘要翻译：在制造应变硅NMOS器件期间进行处理，以在源极和漏极区掺杂剂激活之前在源极区的硅锗部分中以及任选的漏极区产生点缺陷。点缺陷阻碍了硅锗材料中n型掺杂剂的扩散，有效地延长了扩散性瞬态区的持续时间，并且在激活期间导致较低的总掺杂剂扩散率。

38. 发明授权

US06811448B1 Pre-cleaning for silicidation in an SMOS process 有权
标题翻译：在SMOS工艺中预硅化硅化
公开(公告)号：US06811448B1
公开(公告)日：2004-11-02
申请号：US10619879
申请日：2003-07-15
申请人： Eric N. Paton , Paul R. Besser , Qi Xiang
发明人： Eric N. Paton , Paul R. Besser , Qi Xiang
IPC分类号： H01L21302
CPC分类号： H01L21/02054 , H01L21/02046 , H01L21/02052 , H01L21/28518 , H01L29/665
摘要： A fabrication system utilizes a protocol for removing native oxide from a top surface of a wafer. An exposure to a plasma, such as a plasma containing hydrogen and argon can remove the native oxide from the top surface without causing excessive germanium contamination. The protocol can use a hydrogen fluoride dip. The hydrogen fluoride dip can be used before the plasma is used. The protocol allows better silicidation in SMOS devices.
摘要翻译：制造系统利用用于从晶片顶表面去除自然氧化物的协议。暴露于等离子体，例如含有氢气和氩气的等离子体可从顶表面除去天然氧化物，而不会引起过量的锗污染。该方案可以使用氟化氢浸渍。在使用等离子体之前可以使用氟化氢浸渍。该协议允许在SMOS器件中更好的硅化。

39. 发明授权

US06797602B1 Method of manufacturing a semiconductor device with supersaturated source/drain extensions and metal silicide contacts 有权
标题翻译：制造具有过饱和源极/漏极延伸部分和金属硅化物触点的半导体器件的方法
公开(公告)号：US06797602B1
公开(公告)日：2004-09-28
申请号：US10071207
申请日：2002-02-11
申请人： George Jonathan Kluth , Qi Xiang
发明人： George Jonathan Kluth , Qi Xiang
IPC分类号： H01L213205
CPC分类号： H01L29/6653 , H01L21/268 , H01L21/324 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/66628 , H01L29/7833 , H01L29/7834
摘要： Semiconductor devices, such as transistors, with a supersaturated concentration of dopant in the source/drain extension and metal silicide contacts enable the production of smaller, higher speed devices. Supersaturated source/drain extensions are subject to dopant diffusion out from the source/drain extension during high temperature metal silicide contact formation. The formation of lower temperature metal silicide contacts, such as nickel silicide contacts, prevents dopant diffusion and maintains the source/drain extensions in a supersaturated state throughout semiconductor device manufacturing.
摘要翻译：在源极/漏极延伸和金属硅化物触点中具有过饱和浓度的掺杂剂的晶体管等半导体器件能够生产更小更高速度的器件。在高温金属硅化物接触形成期间，过饱和源极/漏极延伸部分从源极/漏极延伸部分扩散出来。低温金属硅化物接触（例如硅化镍接触）的形成防止掺杂剂扩散，并且在整个半导体器件制造过程中将源极/漏极延伸部保持在过饱和状态。

40. 发明授权

US06787423B1 Strained-silicon semiconductor device 有权
标题翻译：应变硅半导体器件
公开(公告)号：US06787423B1
公开(公告)日：2004-09-07
申请号：US10314331
申请日：2002-12-09
申请人： Qi Xiang
发明人： Qi Xiang
IPC分类号： H01L21336
CPC分类号： H01L29/1054 , H01L21/76232 , H01L29/0653
摘要： High-speed semiconductor devices with reduced source/drain junction capacitance and reduced junction leakage based on strain silicon technology are fabricated by extending a shallow trench isolation region under the strained silicon layer. Embodiments include anisotropically etching the trench region and subsequently isotropically etching the trench to form laterally extending regions under the strained silicon layer. Embodiments also include filling the trench with an insulating material such that an air pocket is formed in the trench.
摘要翻译：通过在应变硅层下面扩展浅沟槽隔离区域，制造出具有较低源极/漏极结电容和基于应变硅技术的减少结漏电的半导体器件。实施例包括各向异性蚀刻沟槽区域，随后各向同性蚀刻沟槽，以在应变硅层下方形成横向延伸的区域。实施例还包括用绝缘材料填充沟槽，使得在沟槽中形成气穴。

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