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31. 发明申请

US20120256257A1 TRANSISTOR WITH BURIED FINS 有权
标题翻译：带有隐形金属的晶体管
公开(公告)号：US20120256257A1
公开(公告)日：2012-10-11
申请号：US13081509
申请日：2011-04-07
申请人： Tieh-Chiang Wu , Yi-Nan Chen , Hsien-Wen Liu
发明人： Tieh-Chiang Wu , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： H01L29/772
CPC分类号： H01L27/10879 , H01L27/10826 , H01L29/1037 , H01L29/4236 , H01L29/42376 , H01L29/78
摘要： The present invention disclosed a recessed gate transistor with buried fins. The recessed gate transistor with buried fins is disposed in an active region on a semiconductor substrate. Two isolation regions disposed in the semiconductor substrate, and sandwich the active region. A gate structure is disposed in the semiconductor substrate, wherein the gate structure includes: an upper part and a lower part. The upper part is disposed in the active region and a lower part having a front fin disposed in one of the two isolation regions, at least one middle fin disposed in the active region, and a last fin disposed in the other one of the two isolation regions, wherein the front fin are both elliptic cylindrical.
摘要翻译：本发明公开了一种具有埋地鳍片的凹陷式栅极晶体管。具有埋入散热片的嵌入式栅极晶体管设置在半导体衬底上的有源区中。两个隔离区域设置在半导体衬底中并夹持有源区。栅极结构设置在半导体衬底中，其中栅极结构包括：上部和下部。上部设置在有源区域中，下部具有设置在两个隔离区域之一中的前翅片，设置在有源区域中的至少一个中间翅片，以及设置在两个隔离物中的另一个中的最后一个翅片区域，其中前鳍都是椭圆柱形。

32. 发明申请

US20120256255A1 RECESSED TRENCH GATE STRUCTURE AND METHOD OF FABRICATING THE SAME 审中-公开
标题翻译：阻塞式闸门结构及其制造方法
公开(公告)号：US20120256255A1
公开(公告)日：2012-10-11
申请号：US13081498
申请日：2011-04-07
申请人： Tieh-Chiang Wu , Yi-Nan Chen , Hsien-Wen Liu
发明人： Tieh-Chiang Wu , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/78 , H01L29/1037 , H01L29/4236 , H01L29/42376 , H01L29/66553 , H01L29/66621
摘要： A recessed trench gate structure is provided. The recessed trench gate structure includes a substrate with a recessed trench, a gate dielectric layer disposed around an inner surface of the recessed trench, a lower gate conductor disposed at a lower portion of the recessed trench and on the gate dielectric layer. Specially, the lower gate conductor has a convex top surface. A spacer is disposed along an inner side wall of a upper portion of the recessed trench and a upper gate conductor is disposed on the lower gate conductor. The convex top surface can prevent the electric field from distributing not uniformly, so that the GIDL can be prevented.
摘要翻译：提供凹槽沟槽栅结构。所述凹槽沟槽栅极结构包括具有凹槽的衬底，设置在所述凹槽的内表面周围的栅极电介质层，设置在所述凹槽的下部和所述栅介质层上的下栅极导体。特别地，下栅极导体具有凸起的顶表面。间隔件沿着凹槽的上部的内侧壁设置，并且上栅极导体设置在下栅极导体上。凸顶表面可以防止电场不均匀分布，从而可以防止GIDL。

33. 发明申请

US20120256230A1 POWER DEVICE WITH TRENCHED GATE STRUCTURE AND METHOD OF FABRICATING THE SAME 有权
标题翻译：具有开关门结构的电力装置及其制造方法
公开(公告)号：US20120256230A1
公开(公告)日：2012-10-11
申请号：US13081500
申请日：2011-04-07
申请人： Tieh-Chiang Wu , Yi-Nan Chen , Hsien-Wen Liu
发明人： Tieh-Chiang Wu , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： H01L29/739 , H01L21/331
CPC分类号： H01L29/7397 , H01L29/4236 , H01L29/66348
摘要： A power device with trenched gate structure, includes: a substrate having a first face and a second face opposing to the first face, a body region of a first conductivity type disposed in the substrate, a base region of a second conductivity type disposed in the body region, a cathode region of the first conductivity type disposed in the base region, an anode region of the second conductivity type disposed in the substrate at the second face a trench disposed in the substrate and extending from the first face into the body region, and the cathode region encompassing the trench, wherein the trench has a wavelike sidewall, a gate structure disposed in the trench and an accumulation region disposed in the body region and along the wavelike sidewall. The wavelike sidewall can increase the base current of the bipolar transistor and increase the performance of the IGBT.
摘要翻译：具有沟槽栅极结构的功率器件包括：具有第一面和与第一面相对的第二面的衬底，设置在衬底中的第一导电类型的主体区域，设置在第二导电类型的基极区域设置在所述基底区域中的所述第一导电类型的阴极区域，所述第二导电类型的阳极区域设置在所述基板的所述第二面处，所述沟槽设置在所述基板中并且从所述第一面延伸到所述主体区域中，以及包围所述沟槽的阴极区域，其中所述沟槽具有波状侧壁，设置在所述沟槽中的栅极结构以及设置在所述体区中并沿着所述波浪形侧壁的堆积区域。波形侧壁可以增加双极晶体管的基极电流并增加IGBT的性能。

34. 发明授权

US08278732B1 Antifuse element for integrated circuit device 有权
标题翻译：集成电路器件用防尘元件
公开(公告)号：US08278732B1
公开(公告)日：2012-10-02
申请号：US13096995
申请日：2011-04-28
申请人： Jar-Ming Ho , Yi-Nan Chen , Hsien-Wen Liu
发明人： Jar-Ming Ho , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： H01L23/52
CPC分类号： H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： An antifuse element for an integrated circuit is provided, including a conductive region formed in a semiconductor substrate, extending along a first direction; a dielectric layer formed on a portion of the conductive region; a first conductive plug formed on the dielectric layer; a second conductive plug formed on another portion of the conductive region; and a first conductive member formed over the first and second conductive plugs, extending along a second direction perpendicular to the first direction; and a second conductive member formed over the second conductive plug extending along the second direction, wherein the first conductive member intersects with the conductive region, having a first overlapping area therebetween, and the dielectric layer and the conductive region have a second overlapping area therebetween, and a ratio between the first overlapping area and the second overlapping area is about 1.5:1 to 3:1.
摘要翻译：提供了一种用于集成电路的反熔丝元件，包括形成在半导体衬底中的导电区域，沿着第一方向延伸; 形成在所述导电区域的一部分上的电介质层; 形成在所述电介质层上的第一导电插塞; 形成在所述导电区域的另一部分上的第二导电插塞; 以及第一导电构件，形成在所述第一和第二导电插塞上，沿着垂直于所述第一方向的第二方向延伸; 以及形成在所述第二导电插塞上的第二导电构件，所述第二导电插塞沿着所述第二方向延伸，其中所述第一导电构件与所述导电区域相交，所述导电区域之间具有第一重叠区域，并且所述介电层和所述导电区域之间具有第二重叠区域并且第一重叠区域和第二重叠区域之间的比率为约1.5：1至3：1。

35. 发明申请

US20120149197A1 MANUFACTURING METHOD OF DEVICE AND PLANARIZATION PROCESS 有权
标题翻译：设备制造方法和平面化过程
公开(公告)号：US20120149197A1
公开(公告)日：2012-06-14
申请号：US12962666
申请日：2010-12-08
申请人： Chien-Mao Liao , Yi-Nan Chen
发明人： Chien-Mao Liao , Yi-Nan Chen
IPC分类号： H01L21/306
CPC分类号： H01L21/321 , H01L21/3105 , H01L21/76819 , H01L21/7684
摘要： A manufacturing method of a device is provided. In the manufacturing method, a substrate is provided. The substrate has a plurality of patterns and a plurality of openings formed thereon, and the openings are located among the patterns. A first liquid supporting layer is formed on the patterns, and the openings are filled with the first liquid supporting layer. The first liquid supporting layer is transformed into a first solid supporting layer. The first solid supporting layer includes a plurality of supporting elements formed in the openings, and the supporting elements are formed among the patterns. A treatment process is performed on the patterns. The first solid supporting layer that includes the supporting elements is transformed into a second liquid supporting layer. The second liquid supporting layer is removed.
摘要翻译：提供了一种装置的制造方法。在制造方法中，设置有基板。基板具有多个图案和形成在其上的多个开口，并且开口位于图案之间。在图案上形成第一液体支撑层，并且用第一液体支撑层填充开口。将第一液体支撑层转变成第一固体支撑层。第一固体支持层包括形成在开口中的多个支撑元件，并且支撑元件形成在图案之中。对图案进行处理。包括支撑元件的第一固体支持层被转化成第二液体支撑层。第二液体支撑层被去除。

36. 发明授权

US07285377B2 Fabrication method for a damascene bit line contact plug 有权
标题翻译：镶嵌位线接触插头的制造方法
公开(公告)号：US07285377B2
公开(公告)日：2007-10-23
申请号：US10715616
申请日：2003-11-18
申请人： Yi-Nan Chen , Jeng-Ping Lin , Chih-Ching Lin , Hui-Min Mao
发明人： Yi-Nan Chen , Jeng-Ping Lin , Chih-Ching Lin , Hui-Min Mao
IPC分类号： G03F7/00
CPC分类号： H01L21/76897 , H01L21/76885 , H01L27/105 , H01L27/1052 , H01L27/10888
摘要： A fabrication method for a damascene bit line contact plug. A semiconductor substrate has a first gate conductive structure, a second gate conductive structure and a source/drain region formed therebetween. A first conductive layer is formed in a space between the first gate conductive structure and the second gate conductive structure to be electrically connected to the source/drain region. An inter-layer dielectric with a planarized surface is formed to cover the first conductive layer, the first gate conductive structure, and the second gate conductive structure. A bit line contact hole is formed in the inter-layer dielectric to expose the top of the first conductive layer. A second conductive layer is formed in the bit line contact hole, in which the combination of the second conductive layer and the first conductive layer serves as a damascene bit line contact plug.
摘要翻译：镶嵌位线接触插头的制造方法。半导体衬底具有形成在其间的第一栅极导电结构，第二栅极导电结构和源极/漏极区。第一导电层形成在第一栅极导电结构和第二栅极导电结构之间的空间中，以电连接到源极/漏极区。形成具有平坦化表面的层间电介质以覆盖第一导电层，第一栅极导电结构和第二栅极导电结构。在层间电介质中形成位线接触孔，露出第一导电层的顶部。第二导电层形成在位线接触孔中，其中第二导电层和第一导电层的组合用作镶嵌位线接触插塞。

37. 发明申请

US20060127680A1 Multi-layer hard mask structure for etching deep trench in substrate 有权
公开(公告)号：US20060127680A1
公开(公告)日：2006-06-15
申请号：US11348626
申请日：2006-02-07
申请人： Kaan-Lu Tzou , Tzu-Ching Tsai , Yi-Nan Chen
发明人： Kaan-Lu Tzou , Tzu-Ching Tsai , Yi-Nan Chen
IPC分类号： B32B17/06 , B32B9/00
CPC分类号： H01L27/1087 , C03C15/00 , H01L21/0332 , H01L21/3081
摘要： A method for etching a deep trench in a substrate. A multi-layer hard mask structure is formed overlying the substrate, which includes a first hard mask layer and at least one second hard mask layer disposed thereon. The first hard mask layer is composed of a first boro-silicate glass (BSG) layer and an overlying first undoped silicon glass (USG) layer and the second is composed of a second BSG layer and an overlying second USG layer. A polysilicon layer is formed overlying the multi-layer hard mask structure and then etched to form an opening therein. The multi-layer hard mask structure and the underlying substrate under the opening are successively etched to simultaneously form the deep trench in the substrate and remove the polysilicon layer. The multi-layer hard mask structure is removed.

38. 发明授权

US07029753B2 Multi-layer hard mask structure for etching deep trench in substrate 有权
标题翻译：用于蚀刻衬底深沟槽的多层硬掩模结构
公开(公告)号：US07029753B2
公开(公告)日：2006-04-18
申请号：US10727790
申请日：2003-12-04
申请人： Kaan-Lu Tzou , Tzu-Ching Tsai , Yi-Nan Chen
发明人： Kaan-Lu Tzou , Tzu-Ching Tsai , Yi-Nan Chen
IPC分类号： B23B17/06
CPC分类号： H01L27/1087 , C03C15/00 , H01L21/0332 , H01L21/3081
摘要： A method for etching a deep trench in a substrate. A multi-layer hard mask structure is formed overlying the substrate, which includes a first hard mask layer and at least one second hard mask layer disposed thereon. The first hard mask layer is composed of a first boro-silicate glass (BSG) layer and an overlying first undoped silicon glass (USG) layer and the second is composed of a second BSG layer and an overlying second USG layer. A polysilicon layer is formed overlying the multi-layer hard mask structure and then etched to form an opening therein. The multi-layer hard mask structure and the underlying substrate under the opening are successively etched to simultaneously form the deep trench in the substrate and remove the polysilicon layer. The multi-layer hard mask structure is removed.
摘要翻译：一种用于蚀刻衬底中的深沟槽的方法。形成覆盖在基板上的多层硬掩模结构，其包括第一硬掩模层和设置在其上的至少一个第二硬掩模层。第一硬掩模层由第一硼硅酸盐玻璃（BSG）层和上覆的第一未掺杂硅玻璃（USG）层组成，第二硬质掩模层由第二BSG层和第二USG层组成。形成覆盖多层硬掩模结构的多晶硅层，然后蚀刻以形成其中的开口。连续蚀刻多层硬掩模结构和开口下方的底层基板，同时在衬底中形成深沟槽并去除多晶硅层。去除多层硬掩模结构。

39. 发明授权

US07009236B2 Memory device with vertical transistors and deep trench capacitors and method of fabricating the same 有权
标题翻译：具有垂直晶体管和深沟槽电容器的存储器件及其制造方法
公开(公告)号：US07009236B2
公开(公告)日：2006-03-07
申请号：US10691173
申请日：2003-10-22
申请人： Yi-Nan Chen , Hui-Min Mao , Chih-Yuan Hsiao , Ming-Cheng Chang
发明人： Yi-Nan Chen , Hui-Min Mao , Chih-Yuan Hsiao , Ming-Cheng Chang
IPC分类号： H01L27/108
CPC分类号： H01L27/10864 , H01L27/10867
摘要： A memory device with vertical transistors and deep trench capacitors. The device includes a substrate containing at least one deep trench and a capacitor deposited in the lower portion of the deep trench. A conducting structure, having a first conductive layer and a second conductive layer, is deposited on the trench capacitor. A ring shaped insulator is deposited on the sidewall and between the substrate and the first conductive layer. The first conductive layer is surrounded by the ring shaped insulator, and the second conductive layer is deposited on the first conductive layer and the ring shaped insulator. A diffusion barrier between the second conductive layer and the substrate of the deep trench is deposited on one side of the sidewall of the deep trench. A TTO is deposited on the conducting structure. A control gate is deposited on the TTO.
摘要翻译：具有垂直晶体管和深沟槽电容器的存储器件。该器件包括含有至少一个深沟槽和沉积在深沟槽的下部的电容器的衬底。具有第一导电层和第二导电层的导电结构沉积在沟槽电容器上。环形绝缘体沉积在侧壁上以及衬底和第一导电层之间。第一导电层被环形绝缘体包围，并且第二导电层沉积在第一导电层和环形绝缘体上。在深沟槽的侧壁的一侧上沉积第二导电层和深沟槽的衬底之间的扩散阻挡层。 TTO沉积在导电结构上。控制门被存放在TTO上。

40. 发明授权

US06992393B2 Interconnect structure and method for fabricating the same 有权
标题翻译：互连结构及其制造方法
公开(公告)号：US06992393B2
公开(公告)日：2006-01-31
申请号：US10708848
申请日：2004-03-29
申请人： Tse-Yao Huang , Yi-Nan Chen , Chih-Ching Lin
发明人： Tse-Yao Huang , Yi-Nan Chen , Chih-Ching Lin
IPC分类号： H01L23/48 , H01L23/52
CPC分类号： H01L21/7685 , H01L21/76802 , H01L21/76832 , H01L21/76837
摘要： A method for fabricating interconnects is provided. The method comprises forming a conducting line on a first dielectric layer; forming a first liner layer on the surfaces of the first dielectric layer and the conducting line; forming a second liner layer on the first liner layer; forming a second dielectric layer on the second liner layer, wherein the etching selectivity rate of the second dielectric layer is higher than the etching selectivity rate of the second liner; and patterning the second dielectric layer to form a contact window opening through the second liner layer and the first liner layer to expose the surface of the conducting line. Because the second dielectric layer having an etching rate higher than the etching rate of the second liner layer, the second liner layer can be used as an etch stop layer while patterning the second dielectric layer.
摘要翻译：提供一种用于制造互连的方法。该方法包括在第一电介质层上形成导线; 在所述第一介电层和所述导电线的表面上形成第一衬里层; 在所述第一衬里层上形成第二衬里层; 在所述第二衬里层上形成第二电介质层，其中所述第二电介质层的蚀刻选择率高于所述第二衬垫的蚀刻选择率; 以及图案化所述第二电介质层以形成穿过所述第二衬垫层和所述第一衬里层的接触窗口，以露出所述导电线的表面。由于第二电介质层的蚀刻速率高于第二衬垫层的蚀刻速率，所以第二衬里层可以用作蚀刻停止层，同时构图第二介电层。

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