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31. 发明授权

US06528362B1 Metal gate with CVD amorphous silicon layer for CMOS devices and method of making with a replacement gate process 有权
标题翻译：具有用于CMOS器件的CVD非晶硅层的金属栅极和用替代栅极工艺制造的方法
公开(公告)号：US06528362B1
公开(公告)日：2003-03-04
申请号：US09691181
申请日：2000-10-19
申请人： Paul R. Besser , Qi Xiang , Matthew S. Buynoski
发明人： Paul R. Besser , Qi Xiang , Matthew S. Buynoski
IPC分类号： H01L21336
CPC分类号： H01L21/28194 , H01L21/28061 , H01L29/4925 , H01L29/517 , H01L29/66545
摘要： A semiconductor structure and method for making the same provides a metal gate on a silicon substrate. The gate includes a high dielectric constant on the substrate, and a chemical vapor deposited layer of amorphous silicon on the high k gate dielectric. The metal is then formed on the CVD amorphous silicon layer. The work function of the metal gate is substantially the same as a polysilicon gate due to the presence of the CVD amorphous silicon layer.
摘要翻译：半导体结构及其制造方法在硅衬底上提供金属栅极。该栅极包括在该基板上的高介电常数和在该高k栅极电介质上的非晶硅化学气相沉积层。然后在CVD非晶硅层上形成金属。由于CVD非晶硅层的存在，金属栅极的功函数与多晶硅栅极基本相同。

32. 发明授权

US06518154B1 Method of forming semiconductor devices with differently composed metal-based gate electrodes 有权
标题翻译：用不同组合的金属基栅极形成半导体器件的方法
公开(公告)号：US06518154B1
公开(公告)日：2003-02-11
申请号：US09813310
申请日：2001-03-21
申请人： Matthew S. Buynoski , Qi Xiang , Paul R. Besser
发明人： Matthew S. Buynoski , Qi Xiang , Paul R. Besser
IPC分类号： H01L213205
CPC分类号： H01L29/495 , H01L21/28079 , H01L21/28097 , H01L21/823842 , H01L29/4975
摘要： MOS transistors and CMOS devices comprising a plurality of transistors including metal-based gate electrodes of different composition are formed by a process comprising: depositing a first blanket layer of a first metal on a thin gate insulator layer extending over first and second active device (e.g., a MOS transistor) precursor regions of a semiconductor substrate; selectively forming at least one masking layer segment on the first blanket layer overlying selective ones of the MOS transistor precursor regions; depositing a second blanket layer of a second metal or semi-metal, or silicon, over the thus-formed structure; effecting alloying or silicidation reaction between contacting portions of the first and second blanket layers overlying the other ones of the transistor precursor regions; exposing and selectively removing the masking layer segment; and simultaneously patterning the alloyed and unalloyed/unsilicided portions of the first blanket layer to form metal-based gate electrodes of different composition. The invention also includes MOS and CMOS devices comprising differently composed metal-based gate electrodes.
摘要翻译：包括多个晶体管的MOS晶体管和CMOS器件包括不同组成的金属基栅极，其方法包括：在第一和第二有源器件上延伸的薄栅极绝缘层上沉积第一金属的第一覆盖层（例如，，MOS晶体管）前驱体区域; 选择性地形成覆盖所述MOS晶体管前体区域中的选择性掩模层的所述第一覆盖层上的至少一个掩模层段; 在如此形成的结构上沉积第二金属或半金属或硅的第二覆盖层; 在覆盖晶体管前体区域中的另一层的第一和第二覆盖层的接触部分之间发生合金化或硅化反应; 曝光和选择性地去除掩模层段; 并且同时对第一覆盖层的合金化和非合金化/未硅化部分进行构图，以形成不同组成的金属基栅电极。本发明还包括包含不同组合的金属基栅极的MOS和CMOS器件。

33. 发明授权

US06297107B1 High dielectric constant materials as gate dielectrics 有权
标题翻译：高介电常数材料作为栅极电介质
公开(公告)号：US06297107B1
公开(公告)日：2001-10-02
申请号：US09691228
申请日：2000-10-19
申请人： Eric Paton , Matthew S. Byunoski , Paul R. Besser , Paul L. King , Qi Xiang
发明人： Eric Paton , Matthew S. Byunoski , Paul R. Besser , Paul L. King , Qi Xiang
IPC分类号： H01L21336
CPC分类号： H01L21/28185 , H01L21/28194 , H01L21/31691 , H01L29/517 , H01L29/66545
摘要： A semiconductor structure having a gate dielectric between a gate electrode and a semiconductor substrate is formed with a high dielectric metal oxide layer by replacing a sacrificial gate oxide. Embodiments include forming the metal oxide layer by applying a chemical solution deposition of a metalorganic on to an exposed surface of the substrate followed by pyrolizing the metalorganic residue to a metal oxide.
摘要翻译：通过替代牺牲栅极氧化物，在栅电极和半导体衬底之间具有栅极电介质的半导体结构形成有高介电金属氧化物层。实施例包括通过将金属有机物的化学溶液沉积施加到基板的暴露表面上，然后将金属有机残渣热解成金属氧化物来形成金属氧化物层。

34. 发明授权

US06951220B1 Method of decontaminating equipment 有权
标题翻译：去污设备的方法
公开(公告)号：US06951220B1
公开(公告)日：2005-10-04
申请号：US10288157
申请日：2002-11-05
申请人： Farzad Arasnia , Paul R. Besser , Minh V. Ngo , Qi Xiang
发明人： Farzad Arasnia , Paul R. Besser , Minh V. Ngo , Qi Xiang
IPC分类号： B08B7/00 , B08B9/00 , C23C16/44
CPC分类号： B08B7/00 , C23C16/4405 , Y10S134/902 , Y10S438/905
摘要： A method of performing decontamination of a chamber for use in an IC fabrication system includes providing wet oxygen or a mixture comprising hydrochloric gas and oxygen in the chamber and raising the temperature in the chamber from a first lower temperature to a second higher temperature to cause the wet oxygen or the mixture comprising hydrochloric gas and oxygen to react with the germanium.
摘要翻译：对用于IC制造系统的室进行净化的方法包括在室中提供湿氧气或包含盐酸气体和氧气的混合物，并将室中的温度从第一较低温度升至第二较高温度，以使湿氧气或包含氯化氢气体和氧气的混合物与锗反应。

35. 发明授权

US06440867B1 Metal gate with PVD amorphous silicon and silicide for CMOS devices and method of making the same with a replacement gate process 失效
标题翻译：具有用于CMOS器件的PVD非晶硅和硅化物的金属栅极以及用替换栅极工艺制造相同的方法
公开(公告)号：US06440867B1
公开(公告)日：2002-08-27
申请号：US09691180
申请日：2000-10-19
申请人： Paul R. Besser , Qi Xiang , Matthew S. Buynoski
发明人： Paul R. Besser , Qi Xiang , Matthew S. Buynoski
IPC分类号： H01L21302
CPC分类号： H01L29/66545 , H01L21/28061 , H01L21/28097 , H01L29/517
摘要： A semiconductor structure and method for making the same provides a metal gate on a silicon substrate. The gate includes a high dielectric constant on the substrate, and a physical vapor deposited (PVD) layer of amorphous silicon on the high k gate dielectric. The metal is then formed on the PVD amorphous silicon layer. An annealing process forms silicide in the gate, with a layer of silicon remaining unreacted. The work function of the metal gate is substantially the same as a polysilicon gate due to the presence of the PVD amorphous silicon layer.
摘要翻译：半导体结构及其制造方法在硅衬底上提供金属栅极。栅极在衬底上包括高介电常数，以及在高k栅极电介质上的非晶硅的物理气相沉积（PVD）层。然后在PVD非晶硅层上形成金属。退火工艺在栅极中形成硅化物，其中一层硅残留未反应。由于PVD非晶硅层的存在，金属栅极的功函数与多晶硅栅极基本相同。

36. 发明授权

US06440868B1 Metal gate with CVD amorphous silicon layer and silicide for CMOS devices and method of making with a replacement gate process 失效
标题翻译：具有CVD非晶硅层的金属栅极和用于CMOS器件的硅化物和用替代栅极工艺制造的方法
公开(公告)号：US06440868B1
公开(公告)日：2002-08-27
申请号：US09691259
申请日：2000-10-19
申请人： Paul R. Besser , Qi Xiang , Matthew S. Buynoski
发明人： Paul R. Besser , Qi Xiang , Matthew S. Buynoski
IPC分类号： H01L21302
CPC分类号： H01L21/28052 , H01L29/517 , H01L29/66545 , Y10S438/926
摘要： A semiconductor structure and method for making the same provides a metal gate on a silicon substrate. The gate includes a high dielectric constant on the substrate, and a chemical vapor deposited layer of amorphous silicon on the high k gate dielectric. The metal is then deposited on the CVD amorphous silicon layer. An annealing process forms silicide in the gate, with a layer of silicon remaining unreacted. The work function of the metal gate is substantially the same as a polysilicon gate due to the presence of the CVD amorphous silicon layer.
摘要翻译：半导体结构及其制造方法在硅衬底上提供金属栅极。该栅极包括在该基板上的高介电常数和在该高k栅极电介质上的非晶硅化学气相沉积层。然后将金属沉积在CVD非晶硅层上。退火工艺在栅极中形成硅化物，其中一层硅残留未反应。由于CVD非晶硅层的存在，金属栅极的功函数与多晶硅栅极基本相同。

37. 发明授权

US06376343B1 Reduction of metal silicide/silicon interface roughness by dopant implantation processing 有权
标题翻译：通过掺杂剂注入处理减少金属硅化物/硅界面粗糙度
公开(公告)号：US06376343B1
公开(公告)日：2002-04-23
申请号：US09812695
申请日：2001-03-21
申请人： Matthew S. Buynoski , Paul R. Besser , Qi Xiang
发明人： Matthew S. Buynoski , Paul R. Besser , Qi Xiang
IPC分类号： H01L21425
CPC分类号： H01L29/6659 , H01L21/26513 , H01L21/28518 , H01L21/823814 , H01L29/665
摘要： Deleterious roughness of metal silicide/doped Si interfaces arising during conventional salicide processing for forming shallow-depth source and drain junction regions of MOS transistors and/or CMOS devices due to poor compatibility of particular dopants and metal suicides is avoided, or at least substantially reduced, by implanting a first (main) dopant species having relatively good compatibility with the metal silicide, such that the maximum concentration thereof is at a depth above the depth to which silicidation reaction occurs and implanting a second (auxiliary) dopant species having relatively poor compatibility with the metal silicide, wherein the maximum concentration thereof is less than that of the first (main) dopant and is at a depth below the depth to which silicidation reaction occurs. The invention enjoys particular utility in forming NiSi layers on As-doped Si substrates.
摘要翻译：避免了由于特定掺杂剂和金属硅化物的不良相容性而形成浅晶体管和/或CMOS器件的浅深度源极和漏极结区域的常规自对准硅化物处理期间产生的金属硅化物/掺杂Si界面的有缺陷的粗糙度，或至少大大降低通过植入与金属硅化物具有相对良好的相容性的第一（主要）掺杂剂物质，使得其最大浓度在高于发生硅化反应的深度的深度处，并且注入具有相对较差相容性的第二（辅助）掺杂剂种类金属硅化物，其中其最大浓度小于第一（主要）掺杂剂的最大浓度，并且处于低于发生硅化反应的深度的深度。本发明特别适用于在掺杂Si的衬底上形成NiSi层。

38. 发明授权

US06589866B1 Metal gate with PVD amorphous silicon layer having implanted dopants for CMOS devices and method of making with a replacement gate process 有权
标题翻译：具有用于CMOS器件的注入掺杂剂的PVD非晶硅层的金属栅极和用替代栅极工艺制造的方法
公开(公告)号：US06589866B1
公开(公告)日：2003-07-08
申请号：US09691226
申请日：2000-10-19
申请人： Paul R. Besser , Qi Xiang , Matthew S. Buynoski
发明人： Paul R. Besser , Qi Xiang , Matthew S. Buynoski
IPC分类号： H01L2144
CPC分类号： H01L29/66545 , H01L21/28052 , H01L29/4933
摘要： A semiconductor structure and method for making the same provides a metal gate on a silicon substrate. The gate includes a high dielectric constant on the substrate, and a physical vapor deposited (PVD) layer of amorphous silicon on the high k gate dielectric. The metal is then formed on the PVD amorphous silicon layer. Additional dopants are implanted into the PVD amorphous silicon layer. An annealing process forms silicide in the gate, with a layer of silicon remaining unreacted. The work function of the metal gate is substantially the same as a polysilicon gate due to the presence of the PVD amorphous silicon layer, while the additional doping of the PVD amorphous silicon layer lowers the resistivity of the gate electrode.
摘要翻译：半导体结构及其制造方法在硅衬底上提供金属栅极。栅极在衬底上包括高介电常数，以及在高k栅极电介质上的非晶硅的物理气相沉积（PVD）层。然后在PVD非晶硅层上形成金属。另外的掺杂剂被注入到PVD非晶硅层中。退火工艺在栅极中形成硅化物，其中一层硅残留未反应。由于PVD非晶硅层的存在，金属栅极的功函数与多晶硅栅极基本相同，而PVD非晶硅层的附加掺杂降低了栅电极的电阻率。

39. 发明授权

US06436840B1 Metal gate with CVD amorphous silicon layer and a barrier layer for CMOS devices and method of making with a replacement gate process 失效
标题翻译：具有CVD非晶硅层的金属栅极和用于CMOS器件的阻挡层以及用替代栅极工艺制造的方法
公开(公告)号：US06436840B1
公开(公告)日：2002-08-20
申请号：US09691188
申请日：2000-10-19
申请人： Paul R. Besser , Matthew S. Buynoski , Qi Xiang
发明人： Paul R. Besser , Matthew S. Buynoski , Qi Xiang
IPC分类号： H01L21302
CPC分类号： H01L21/28194 , H01L21/28044 , H01L21/3146 , H01L29/4941 , H01L29/517 , Y10S438/926
摘要： A semiconductor structure and method for making the same provides a metal gate on a silicon substrate. The gate includes a high dielectric constant on the substrate, and a chemical vapor deposited layer of amorphous silicon on the high k gate dielectric. A barrier is then deposited on the CVD amorphous silicon layer. A metal is then formed on the barrier. The work function of the metal gate is substantially the same as a polysilicon gate due to the presence of the CVD amorphous silicon layer. The work function is preserved by the barrier during subsequent high temperature processing, due to the barrier which prevents interaction between the CVD amorphous silicon layer and the metal, which could otherwise form silicide and change the work function.
摘要翻译：半导体结构及其制造方法在硅衬底上提供金属栅极。该栅极包括在该基板上的高介电常数和在该高k栅极电介质上的非晶硅化学气相沉积层。然后在CVD非晶硅层上沉积阻挡层。然后在屏障上形成金属。由于CVD非晶硅层的存在，金属栅极的功函数与多晶硅栅极基本相同。由于防止CVD非晶硅层与金属之间的相互作用的屏障，因此在随后的高温处理期间，阻挡层保留功函数，否则可能形成硅化物并改变功函数。

40. 发明授权

US06583012B1 Semiconductor devices utilizing differently composed metal-based in-laid gate electrodes 有权
标题翻译：利用不同组合的金属基嵌入栅电极的半导体器件
公开(公告)号：US06583012B1
公开(公告)日：2003-06-24
申请号：US09781436
申请日：2001-02-13
申请人： Matthew S. Buynoski , Qi Xiang , Paul R. Besser
发明人： Matthew S. Buynoski , Qi Xiang , Paul R. Besser
IPC分类号： H01L218234
CPC分类号： H01L29/495 , H01L21/28079 , H01L21/28518 , H01L21/823842
摘要： MOS transistor and CMOS devices comprising a plurality of transistors including in-laid, metal-based gate electrodes of different composition are formed by a process comprising: depositing a first blanket layer of a first metal filling openings in an insulative layer at the bottom of which openings gate insulator layer segments of MOS transistor precursor regions formed in a semiconductor substrate are exposed; selectively forming at least one masking layer segment on the first blanket layer overlying selected ones of the MOS transistor precursor regions; depositing a second blanket layer of a second metal or silicon over the thus-formed structure, and effecting alloying or silicidation reaction between contacting portions of the first and second blanket layers overlying other ones of the MOS transistor precursor regions. Unnecessary layers remaining after alloying or silicidation reaction are then removed by performing planarization processing, e.g., by CMP. The invention also includes MOS and CMOS devices comprising differently composed in-laid, metal-based gate electrodes.
摘要翻译：包括多个晶体管的MOS晶体管和CMOS器件包括具有不同组成的嵌入式金属基栅极的多个晶体管，其特征在于，包括：在绝缘层的底部沉积第一金属填充开口的第一覆盖层，形成在半导体衬底中的MOS晶体管前体区的开口栅极绝缘体层段露出; 选择性地形成覆盖所选择的MOS晶体管前体区域的第一覆盖层上的至少一个掩模层段; 在如此形成的结构上沉积第二金属或硅的第二覆盖层，并且在覆盖其它MOS晶体管前体区域的第一和第二覆盖层的接触部分之间进行合金化或硅化反应。然后通过进行平坦化处理，例如通过CMP除去在合金化或硅化反应之后残留的不必要的层。本发明还包括包括不同组合的嵌入式金属基栅极的MOS和CMOS器件。

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