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31. 发明申请

US20070283208A1 SYSTEMS, METHODS, AND COMPUTER PROGRAM PRODUCTS FOR PROVIDING A TWO-BIT SYMBOL BUS ERROR CORRECTING CODE WITH BUS DIAGNOSTIC FEATURES 审中-公开
标题翻译：系统，方法和计算机程序产品，用于提供具有总线诊断功能的两位符号总线错误校正代码
公开(公告)号：US20070283208A1
公开(公告)日：2007-12-06
申请号：US11421537
申请日：2006-06-01
申请人： Timothy J. Dell , Patrick J. Meaney
发明人： Timothy J. Dell , Patrick J. Meaney
IPC分类号： H03M13/00
CPC分类号： H03M13/2906 , H03M13/098 , H03M13/19
摘要： Systems, method, and computer program products for providing a nested two-bit symbol bus error correcting code for transfer over a bus in two or more transfers Methods include constructing a nested error correcting code (ECC) scheme. The method includes receiving a Hamming distance n code including original checkbits. A symbol correcting code H-matrix framework is defined including specifying bit positions for the original checkbits and for additional checkbits associated with a symbol correcting code. The bit positions are specified such that the additional checkbits are in bit positions that are transferred over a bus in a transfer subsequent to a first transfer. A symbol correcting code H-matrix is created using the bit positions indicated by the framework by iteratively adding rows of H-matrix bits on a symbol column basis such that the symbol correcting code H-matrix describes the symbol correcting code, and the Hamming distance n code is preserved as a subset of the symbol correcting code H-matrix.
摘要翻译：用于提供用于在两个或多个传输中通过总线传送的嵌套两比特符号总线纠错码的系统，方法和计算机程序产品方法包括构建嵌套纠错码（ECC）方案。该方法包括接收包括原始检验位的汉明距离n码。定义符号校正码H矩阵框架，包括指定原始校验位的位位置和与符号校正码相关联的附加校验位。指定位位置，使得附加检验位处于在第一次传送之后的传输中通过总线传送的位位置。使用由框架指示的比特位置，通过在符号列上迭代地添加H矩阵比特行来创建符号校正码H矩阵，使得符号校正码H矩阵描述符号校正码，并且汉明距离 n代码被保留为符号校正码H矩阵的子集。

32. 发明申请

US20070283207A1 SYSTEMS, METHODS, AND COMPUTER PROGRAM PRODUCTS FOR PROVIDING A TWO-BIT SYMBOL BUS ERROR CORRECTING CODE WITH BUS TIMING IMPROVEMENTS 审中-公开
标题翻译：系统，方法和计算机程序产品，用于提供具有总线时序改进的两位符号总线错误校正代码
公开(公告)号：US20070283207A1
公开(公告)日：2007-12-06
申请号：US11421532
申请日：2006-06-01
申请人： Timothy J. Dell , Patrick J. Meaney
发明人： Timothy J. Dell , Patrick J. Meaney
IPC分类号： H03M13/00
CPC分类号： H03M13/098 , H03M13/19 , H03M13/2906
摘要： Systems, method, and computer program products for providing a nested two-bit symbol bus error correcting code scheme for transfer over a bus in two or more transfers. Methods include constructing a nested error correcting code (ECC) scheme. The method includes receiving a Hamming distance n code including original checkbits. A symbol correcting code H-matrix framework is defined including specifying bit positions for the original checkbits and for additional checkbits associated with a symbol correcting code. The bit positions are specified such that the additional checkbits are in bit positions that are transferred over a bus in a transfer subsequent to a first transfer. A symbol correcting code H-matrix is created using the bit positions indicated by the framework by iteratively adding rows of H-matrix bits on a symbol column basis such that the symbol correcting code H-matrix describes the symbol correcting code, and the Hamming distance n code is preserved as a subset of the symbol correcting code H-matrix.
摘要翻译：用于提供嵌套两比特符号总线纠错码方案的系统，方法和计算机程序产品，用于在两个或多个传输中通过总线进行传输。方法包括构建嵌套纠错码（ECC）方案。该方法包括接收包括原始检验位的汉明距离n码。定义符号校正码H矩阵框架，包括指定原始校验位的位位置和与符号校正码相关联的附加校验位。指定位位置，使得附加检验位处于在第一次传送之后的传输中通过总线传送的位位置。使用由框架指示的比特位置，通过在符号列上迭代地添加H矩阵比特行来创建符号校正码H矩阵，使得符号校正码H矩阵描述符号校正码，并且汉明距离 n代码被保留为符号校正码H矩阵的子集。

33. 发明授权

US06460157B1 Method system and program products for error correction code conversion 有权
标题翻译：方法系统和程序产品进行纠错码转换
公开(公告)号：US06460157B1
公开(公告)日：2002-10-01
申请号：US09450548
申请日：1999-11-30
申请人： Chin-Long Chen , Mu-Yue Hsiao , Patrick J. Meaney , William Wu Shen
发明人： Chin-Long Chen , Mu-Yue Hsiao , Patrick J. Meaney , William Wu Shen
IPC分类号： H03M1300
CPC分类号： G06F11/1008 , G11B20/18
摘要： Data is protected during conversion from one or more source error correction codes to one or more destination error correction codes by generating check bits of the destination error correction codes prior to a detection for errors in the source error correction codes. After commencing generation of these check bits, a detection is made for any errors in the source error correction codes. These errors are subsequently corrected in the destination error correction codes by complementing the erroneous bits of the destination error correction code. In addition, various logic reduction techniques may also be implemented to increase efficiency.
摘要翻译：数据在从一个或多个源纠错码到一个或多个目的地纠错码的转换期间通过在检测到源纠错码中的错误之前产生目的地纠错码的检查位来保护。在开始生成这些校验位之后，检测源纠错码中的任何错误。通过补充目的地纠错码的错误位，随后在目的地纠错码中校正这些误差。此外，还可以实现各种逻辑降低技术以提高效率。

34. 发明授权

US5692209A System resource conflict resolution apparatus 失效
标题翻译：系统资源冲突解决装置
公开(公告)号：US5692209A
公开(公告)日：1997-11-25
申请号：US484771
申请日：1995-06-07
申请人： Patrick J. Meaney , Adrian E. Seigler
发明人： Patrick J. Meaney , Adrian E. Seigler
IPC分类号： G06F12/06 , G06F1/32 , G06F9/38 , G06F9/46 , G06F9/50 , G06F12/16 , G06F13/18 , G06F15/00
CPC分类号： G06F9/5011 , G06F1/32 , G06F13/18 , G06F2209/507 , Y02B60/142
摘要： A system resource enable apparatus for enabling operations on a system resource including a register representing current and future operations on the resource, a pattern generator that applies a pattern corresponding to a requested resource operation to each of a plurality of requests for resource operations in a queue, compare logic that determines for each of the plurality of requests if the request will conflict with other resource operations by comparing the pattern applied to the request with the register, priority grant logic that grants priority to a request in the queue if no conflict is determined and to update the register according to the pattern applied to the request, and resource enable logic that enables operations on the resource according to the register.
摘要翻译：一种系统资源使能装置，用于对包括代表资源当前和未来操作的寄存器的系统资源进行操作，模式生成器，将与所请求的资源操作相对应的模式应用于队列中的资源操作的多个请求中的每一个比较逻辑，如果请求将与其他资源操作冲突，则通过将应用于该请求的模式与该寄存器进行比较来确定多个请求中的每个请求，优先级授权逻辑如果没有确定冲突则向队列中的请求授予优先权并根据应用于请求的模式来更新寄存器，以及根据寄存器对资源进行操作的资源使能逻辑。

35. 发明授权

US08914708B2 Bad wordline/array detection in memory 有权
标题翻译：内存中的字线/阵列检测不良
公开(公告)号：US08914708B2
公开(公告)日：2014-12-16
申请号：US13523971
申请日：2012-06-15
申请人： Patrick J. Meaney , Arthur J. O'Neill , Gary E. Strait
发明人： Patrick J. Meaney , Arthur J. O'Neill , Gary E. Strait
IPC分类号： G11C29/00 , H03M13/05 , G06F11/07 , G06F11/10
CPC分类号： H03M13/05 , G06F11/073 , G06F11/1008 , G06F11/1064 , G06F11/1666 , G06F11/20
摘要： A technique for error detection is provided. A controller is configured to detect errors by using error correcting code (ECC), and a cache includes independent ECC words for storing data. The controller detects the errors in the ECC words for a wordline that is read. The controller detects a first error in a first ECC word on the wordline and a second error in a second ECC word on the wordline. The controller determines that the wordline is a failing wordline based on detecting the first error in the first ECC word and the second error in the second ECC word.
摘要翻译：提供了一种错误检测技术。控制器被配置为通过使用纠错码（ECC）来检测错误，并且高速缓存包括用于存储数据的独立ECC字。控制器检测读取的字线的ECC字中的错误。控制器检测字线上的第一ECC字中的第一错误和字线上的第二ECC字中的第二错误。控制器基于检测第一ECC字中的第一错误和第二ECC字中的第二错误，确定字线是故障字线。

36. 发明授权

US08316284B2 Collecting failure information on error correction code (ECC) protected data 有权
标题翻译：收集有关纠错码（ECC）保护数据的故障信息
公开(公告)号：US08316284B2
公开(公告)日：2012-11-20
申请号：US12360402
申请日：2009-01-27
申请人： Arthur J. O'Neill , Patrick J. Meaney
发明人： Arthur J. O'Neill , Patrick J. Meaney
IPC分类号： H03M13/00 , G11C29/00
CPC分类号： G06F11/10
摘要： Methods of error correction code (ECC) debugging may comprise detecting whether a bit error has occurred; determining which bit or bits were in error; and using the bit error information for debug. The method may further comprise comparing ECC syndromes against one or more ECC syndrome patterns. The method may allow for accumulating bit error information, comparing error bit failures against a pattern, trapping data, counting errors, determining pick/drop information, or stopping the machine for debug.
摘要翻译：纠错码（ECC）调试方法可以包括检测是否发生位错误; 确定哪些位或位是错误的; 并使用位错误信息进行调试。该方法还可以包括比较ECC综合征与一个或多个ECC综合征模式。该方法可以允许累积位错误信息，将错误位故障与模式进行比较，捕获数据，计数错误，确定拾取/丢弃信息或停止机器进行调试。

37. 发明申请

US20120198309A1 CORRECTING MEMORY DEVICE AND MEMORY CHANNEL FAILURES IN THE PRESENCE OF KNOWN MEMORY DEVICE FAILURES 失效
标题翻译：在存在的存储器件故障存在的情况下修正存储器件和存储器通道故障
公开(公告)号：US20120198309A1
公开(公告)日：2012-08-02
申请号：US13016977
申请日：2011-01-29
申请人： Luiz C. Alves , Luis A. Lastras-Montano , Patrick J. Meaney , Eldee Stephens , Barry M. Trager
发明人： Luiz C. Alves , Luis A. Lastras-Montano , Patrick J. Meaney , Eldee Stephens , Barry M. Trager
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： G06F11/10 , H03M13/13 , H03M13/1515 , H03M13/152 , H03M13/19
摘要： Correcting memory device (chip) and memory channel failures in the presence of known memory device failures. A memory channel failure is located and corrected, or alternatively up to c chip failures are corrected and up to d chip failures are detected in the presence of up to u chips that are marked as suspect. A first stage of decoding is performed that results in recovering an estimate of correctable errors affecting the data or in declaring an uncorrectable error state. When an uncorrectable error state is declared, a second stage of decoding is performed to attempt to correct u erasures and a channel error in M iterations where the channel location is changed in each iteration. A correctable error is declared in response to exactly one of the M iterations being successful.
摘要翻译：在存在已知存储器件故障的情况下更正存储器件（芯片）和存储器通道故障。存储器通道故障被定位和校正，或者高达c个芯片故障被校正，并且在存在被标记为可疑的最多u个芯片的情况下，检测到高达d个芯片故障。执行解码的第一阶段，其导致恢复影响数据的可校正错误的估计或者宣告不可校正的错误状态。当声明不可校正的错误状态时，执行第二级解码以尝试在每次迭代中改变通道位置的M次迭代中纠正擦除和通道错误。响应正好一个M次迭代成功声明可纠正的错误。

38. 发明申请

US20120173936A1 CHANNEL MARKING FOR CHIP MARK OVERFLOW AND CALIBRATION ERRORS 有权
标题翻译： CHANNEL MARKING FOR CHIP MARK OVERFLOW和CALIBRATION ERRORS
公开(公告)号：US20120173936A1
公开(公告)日：2012-07-05
申请号：US12981017
申请日：2010-12-29
申请人： Judy S. Johnson , Luis A. Lastras-Montano , Patrick J. Meaney , Eldee Stephens
发明人： Judy S. Johnson , Luis A. Lastras-Montano , Patrick J. Meaney , Eldee Stephens
IPC分类号： G06F11/10
CPC分类号： G11C29/44 , G06F11/1044 , G06F11/1076 , G06F11/30 , G06F2211/1064
摘要： Marking memory chips as faulty when a fault is detected in data from the memory chip. Upon detecting that a plurality of memory chips are faulty, determining which of a plurality of memory channels contains the faulty memory chips. Marking one of a plurality of memory channels as failing in response to determining that the number of failing memory chips has exceeded a threshold.
摘要翻译：当从存储器芯片的数据中检测到故障时，将存储器芯片标记为故障。在检测到多个存储器芯片有故障时，确定多个存储器通道中的哪一个存储有故障的存储器芯片。响应于确定故障存储器芯片的数量已经超过阈值，将多个存储器通道中的一个标记为失败。

39. 发明申请

US20110320919A1 HIGH PERFORMANCE CACHE DIRECTORY ERROR CORRECTION CODE 失效
标题翻译：高性能缓存目录错误修正代码
公开(公告)号：US20110320919A1
公开(公告)日：2011-12-29
申请号：US12822889
申请日：2010-06-24
申请人： Ekaterina M. Ambroladze , Patrick J. Meaney , Arthur J. O'Neill, JR.
发明人： Ekaterina M. Ambroladze , Patrick J. Meaney , Arthur J. O'Neill, JR.
IPC分类号： H03M13/15 , G06F11/10
CPC分类号： G06F11/1064 , H03M13/19
摘要： Defining a set of correctable error and uncorrectable error syndrome code points, generating an error correction code (ECC) syndrome decode, regarding the uncorrectable error syndrome code points as “don't cares” and logically minimizing the ECC syndrome decode for the determination of the correctable error syndrome code points based on the regarding of the uncorrectable error syndrome code points as the “don't cares” whereby output data can be ignored for the uncorrectable error syndrome code points.
摘要翻译：定义一组可纠正的错误和不可校正的错误校正码代码点，产生纠错码（ECC）校正码解码，关于不可校正的错误校正码码点为“不关心”，并在逻辑上最小化ECC校验码解码以确定基于关于不可校正误差校验码码点的可校正误差校验码码点作为“不关心”，由此对于不可校正的误码校验码码点可以忽略输出数据。

40. 发明申请

US20110320918A1 ERROR CORRECTION AND DETECTION IN A REDUNDANT MEMORY SYSTEM 有权
标题翻译：冗余存储系统中的错误校正和检测
公开(公告)号：US20110320918A1
公开(公告)日：2011-12-29
申请号：US12822469
申请日：2010-06-24
申请人： Luis C. Alves , Luis A. Lastras-Montano , Patrick J. Meaney , Eldee Stephens , Barry M. Trager
发明人： Luis C. Alves , Luis A. Lastras-Montano , Patrick J. Meaney , Eldee Stephens , Barry M. Trager
IPC分类号： H03M13/07 , G06F11/10
CPC分类号： G06F11/1044 , G06F11/108 , H03M13/19 , H03M13/2906 , H03M13/3761
摘要： Error correction and detection in a redundant memory system including a a computer implemented method that includes receiving data including error correction code (ECC) bits, the receiving from a plurality of channels, each channel comprising a plurality of memory devices at memory device locations. The method also includes computing syndromes of the data; receiving a channel identifier of one of the channels; and removing a contribution of data received on the channel from the computed syndromes, the removing resulting in channel adjusted syndromes. The channel adjusted syndromes are decoded resulting in channel adjusted memory device locations of failing memory devices, the channel adjusted memory device locations corresponding to memory device locations.
摘要翻译：在包括计算机实现的方法的冗余存储器系统中的错误校正和检测，所述方法包括接收包括纠错码（ECC）位的数据，从多个信道接收每个信道包括存储器设备位置处的多个存储器件。该方法还包括计算数据的综合征; 接收一个频道的频道标识符; 以及从所计算的综合征中去除在所述信道上接收的数据的贡献，所述移除导致频道调整的综合征。频道调整后的综合征被解码，导致故障存储器件的通道调整的存储器件位置，对应于存储器件位置的通道调整的存储器件位置。

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