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1. 发明申请

US20130339822A1 BAD WORDLINE/ARRAY DETECTION IN MEMORY 有权
公开(公告)号：US20130339822A1
公开(公告)日：2013-12-19
申请号：US13523971
申请日：2012-06-15
申请人： Patrick J. Meaney , Arthur J. O'Neill , Gary E. Strait
发明人： Patrick J. Meaney , Arthur J. O'Neill , Gary E. Strait
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： H03M13/05 , G06F11/073 , G06F11/1008 , G06F11/1064 , G06F11/1666 , G06F11/20
摘要： A technique for error detection is provided. A controller is configured to detect errors by using error correcting code (ECC), and a cache includes independent ECC words for storing data. The controller detects the errors in the ECC words for a wordline that is read. The controller detects a first error in a first ECC word on the wordline and a second error in a second ECC word on the wordline. The controller determines that the wordline is a failing wordline based on detecting the first error in the first ECC word and the second error in the second ECC word.

2. 发明授权

US08914708B2 Bad wordline/array detection in memory 有权
标题翻译：内存中的字线/阵列检测不良
公开(公告)号：US08914708B2
公开(公告)日：2014-12-16
申请号：US13523971
申请日：2012-06-15
申请人： Patrick J. Meaney , Arthur J. O'Neill , Gary E. Strait
发明人： Patrick J. Meaney , Arthur J. O'Neill , Gary E. Strait
IPC分类号： G11C29/00 , H03M13/05 , G06F11/07 , G06F11/10
CPC分类号： H03M13/05 , G06F11/073 , G06F11/1008 , G06F11/1064 , G06F11/1666 , G06F11/20
摘要： A technique for error detection is provided. A controller is configured to detect errors by using error correcting code (ECC), and a cache includes independent ECC words for storing data. The controller detects the errors in the ECC words for a wordline that is read. The controller detects a first error in a first ECC word on the wordline and a second error in a second ECC word on the wordline. The controller determines that the wordline is a failing wordline based on detecting the first error in the first ECC word and the second error in the second ECC word.
摘要翻译：提供了一种错误检测技术。控制器被配置为通过使用纠错码（ECC）来检测错误，并且高速缓存包括用于存储数据的独立ECC字。控制器检测读取的字线的ECC字中的错误。控制器检测字线上的第一ECC字中的第一错误和字线上的第二ECC字中的第二错误。控制器基于检测第一ECC字中的第一错误和第二ECC字中的第二错误，确定字线是故障字线。

3. 发明申请

US20130339808A1 BITLINE DELETION 失效
公开(公告)号：US20130339808A1
公开(公告)日：2013-12-19
申请号：US13523633
申请日：2012-06-14
申请人： Ekaterina M. Ambroladze , Michael A. Blake , Michael Fee , Hieu T. Huynh , Patrick J. Meaney , Arthur J. O'Neill
发明人： Ekaterina M. Ambroladze , Michael A. Blake , Michael Fee , Hieu T. Huynh , Patrick J. Meaney , Arthur J. O'Neill
IPC分类号： G06F11/20
CPC分类号： G06F11/1064 , G06F11/073 , G06F11/076 , G06F11/08 , G11C2029/1204
摘要： Embodiments relate to a method including detecting a first error when reading a first cache line, recording a first address of the first error, detecting a second error when reading a second cache line and recording a second address of the second error. Embodiments also include comparing the first and second bitline address, comparing the first and second wordline address, activating a bitline delete mode based on matching first and second bitline addresses and not matching the first and second wordline addresses, detecting a third error when reading a third cache line, recording a third bitline address of the third error, comparing the second bitline address to a third bitline address and deleting a location corresponding to the third cache line from available cache locations based on the activated bitline delete mode and the third bitline address matching the second bitline address.
摘要翻译：实施例涉及一种方法，包括当读取第一高速缓存行时检测第一错误，记录第一错误的第一地址，在读取第二高速缓存行时检测第二错误并记录第二错误的第二地址。实施例还包括比较第一和第二位线地址，比较第一和第二字线地址，基于匹配的第一和第二位线地址激活位线删除模式，并且不匹配第一和第二字线地址，在读取第三位线时检测第三错误记录第三错误的第三位线地址，将第二位线地址与第三位线地址进行比较，并且基于激活的位线删除模式和第三位线地址匹配从可用高速缓存位置删除与第三高速缓存行相对应的位置第二个位线地址。

4. 发明授权

US08788891B2 Bitline deletion 失效
标题翻译：位线删除
公开(公告)号：US08788891B2
公开(公告)日：2014-07-22
申请号：US13523633
申请日：2012-06-14
申请人： Ekaterina M. Ambroladze , Michael A. Blake , Michael Fee , Hieu T. Huynh , Patrick J. Meaney , Arthur J. O'Neill
发明人： Ekaterina M. Ambroladze , Michael A. Blake , Michael Fee , Hieu T. Huynh , Patrick J. Meaney , Arthur J. O'Neill
IPC分类号： G06F11/00 , G11C29/00 , G06F11/10 , G11C29/12
CPC分类号： G06F11/1064 , G06F11/073 , G06F11/076 , G06F11/08 , G11C2029/1204
摘要： Embodiments relate to a method including detecting a first error when reading a first cache line, recording a first address of the first error, detecting a second error when reading a second cache line and recording a second address of the second error. Embodiments also include comparing the first and second bitline address, comparing the first and second wordline address, activating a bitline delete mode based on matching first and second bitline addresses and not matching the first and second wordline addresses, detecting a third error when reading a third cache line, recording a third bitline address of the third error, comparing the second bitline address to a third bitline address and deleting a location corresponding to the third cache line from available cache locations based on the activated bitline delete mode and the third bitline address matching the second bitline address.
摘要翻译：实施例涉及一种方法，包括当读取第一高速缓存行时检测第一错误，记录第一错误的第一地址，在读取第二高速缓存行时检测第二错误并记录第二错误的第二地址。实施例还包括比较第一和第二位线地址，比较第一和第二字线地址，基于匹配的第一和第二位线地址激活位线删除模式，并且不匹配第一和第二字线地址，在读取第三位线时检测第三错误记录第三错误的第三位线地址，将第二位线地址与第三位线地址进行比较，并且基于激活的位线删除模式和第三位线地址匹配从可用高速缓存位置删除与第三高速缓存行相对应的位置第二个位线地址。

5. 发明授权

US07502986B2 Method and apparatus for collecting failure information on error correction code (ECC) protected data 有权
标题翻译：收集有关纠错码（ECC）保护数据的故障信息的方法和装置
公开(公告)号：US07502986B2
公开(公告)日：2009-03-10
申请号：US11054575
申请日：2005-02-09
申请人： Arthur J. O'Neill , Patrick J. Meaney
发明人： Arthur J. O'Neill , Patrick J. Meaney
IPC分类号： H03M13/00
CPC分类号： G06F11/10
摘要： A method of error correction code (ECC) debugging for a system comprising, receiving data having an ECC, determining whether a data error has occurred, generating a syndrome of an error result, decoding flipped data bits, processing the received data and the decoded flipped bits to correct the data, outputting corrected data having an ECC, receiving a trap update signal, and saving the decoded flipped data bits responsive to receiving the trap update signal.
摘要翻译：一种用于系统的纠错码（ECC）调试的方法，包括：接收具有ECC的数据，确定是否已经发生数据错误，产生错误结果的综合征，翻转翻转的数据位，处理接收的数据和解码的翻转的位校正数据，输出具有ECC的校正数据，接收陷阱更新信号，以及响应于接收到陷阱更新信号而保存解码翻转数据位。

6. 发明授权

US08316284B2 Collecting failure information on error correction code (ECC) protected data 有权
标题翻译：收集有关纠错码（ECC）保护数据的故障信息
公开(公告)号：US08316284B2
公开(公告)日：2012-11-20
申请号：US12360402
申请日：2009-01-27
申请人： Arthur J. O'Neill , Patrick J. Meaney
发明人： Arthur J. O'Neill , Patrick J. Meaney
IPC分类号： H03M13/00 , G11C29/00
CPC分类号： G06F11/10
摘要： Methods of error correction code (ECC) debugging may comprise detecting whether a bit error has occurred; determining which bit or bits were in error; and using the bit error information for debug. The method may further comprise comparing ECC syndromes against one or more ECC syndrome patterns. The method may allow for accumulating bit error information, comparing error bit failures against a pattern, trapping data, counting errors, determining pick/drop information, or stopping the machine for debug.
摘要翻译：纠错码（ECC）调试方法可以包括检测是否发生位错误; 确定哪些位或位是错误的; 并使用位错误信息进行调试。该方法还可以包括比较ECC综合征与一个或多个ECC综合征模式。该方法可以允许累积位错误信息，将错误位故障与模式进行比较，捕获数据，计数错误，确定拾取/丢弃信息或停止机器进行调试。

7. 发明申请

US20090164874A1 Collecting Failure Information On Error Correction Code (ECC) Protected Data 有权
标题翻译：收集有关错误纠正码（ECC）受保护数据的故障信息
公开(公告)号：US20090164874A1
公开(公告)日：2009-06-25
申请号：US12360402
申请日：2009-01-27
申请人： Arthur J. O'Neill , Patrick J. Meaney
发明人： Arthur J. O'Neill , Patrick J. Meaney
IPC分类号： H03M13/15 , G06F11/10
CPC分类号： G06F11/10
摘要： Methods and means of error correction code (ECC) debugging may comprise detecting whether a bit error has occurred; determining which bit or bits were in error; and using the bit error information for debug. The method may further comprise comparing ECC syndromes against one or more ECC syndrome patterns. The method may allow for accumulating bit error information, comparing error bit failures against a pattern, trapping data, counting errors, determining pick/drop information, or stopping the machine for debug.
摘要翻译：纠错码（ECC）调试的方法和手段可以包括检测是否发生位错误; 确定哪些位或位是错误的; 并使用位错误信息进行调试。该方法还可以包括比较ECC综合征与一个或多个ECC综合征模式。该方法可以允许累积位错误信息，将错误位故障与模式进行比较，捕获数据，计数错误，确定拾取/丢弃信息或停止机器进行调试。

8. 发明授权

US08131937B2 Apparatus and method for improved data persistence within a multi-node system 有权
标题翻译：用于改善多节点系统内的数据持久性的装置和方法
公开(公告)号：US08131937B2
公开(公告)日：2012-03-06
申请号：US11766977
申请日：2007-06-22
申请人： Michael A. Blake , Harmony L. Helterhoff , Arthur J. O'Neill , Vesselina K. Papazova , Craig R. Walters
发明人： Michael A. Blake , Harmony L. Helterhoff , Arthur J. O'Neill , Vesselina K. Papazova , Craig R. Walters
IPC分类号： G06F13/00
CPC分类号： G06F12/084 , G06F12/0897 , G06F12/126
摘要： Improved access to retained data useful to a system is accomplished by managing data flow through cache associated with the processor(s) of a multi-node system. A data management facility operable with the processors and memory array directs the flow of data from the processors to the memory array by determining the path along which data evicted from a level of cache close to one of the processors is to return to a main memory and directing evicted data to be stored, if possible, in a horizontally associated cache.
摘要翻译：改进对对系统有用的保留数据的访问通过管理与多节点系统的处理器相关联的高速缓存的数据流来实现。可与处理器和存储器阵列一起操作的数据管理设备通过确定沿着哪个数据从处理器中的一个接收到的高速缓存驱逐出的数据返回到主存储器，从而将来自处理器的数据流引导到存储器阵列，如果可能的话，将被驱逐的数据存储在水平相关的缓存中。

9. 发明申请

US20130339606A1 REDUCING STORE OPERATION BUSY TIMES 有权
标题翻译：减少存储操作繁忙时间
公开(公告)号：US20130339606A1
公开(公告)日：2013-12-19
申请号：US13523567
申请日：2012-06-14
申请人： Deanna Postles Dunn Berger , Michael F. Fee , Christine C. Jones , Arthur J. O'Neill , Diane L. Orf
发明人： Deanna Postles Dunn Berger , Michael F. Fee , Christine C. Jones , Arthur J. O'Neill , Diane L. Orf
IPC分类号： G06F12/08
CPC分类号： G06F12/0806 , G06F9/38 , G06F9/3855 , G06F12/0855 , G11C7/22 , G11C2207/229 , Y02D10/13
摘要： A computer product for reducing store operation busy times is provided and relates to associating first and second platform registers with a cache array, determining that first and second store operations target a same wordline of the cache array, loading control information and data of the store operations into the platform registers and delaying a commit of the first store operation until the loading of the second platform register is complete. The method further includes committing the data from the platform registers using the control information from the platform registers to the wordline of the cache array at a same time to thereby reduce a busy time of the wordline of the cache array.
摘要翻译：提供了用于减少存储操作繁忙时间的计算机产品，并且涉及将第一和第二平台寄存器与高速缓存阵列相关联，确定第一和第二存储操作针对高速缓存阵列的相同字线，加载控制信息和存储操作的数据进入平台寄存器并延迟第一个存储操作的提交，直到第二个平台寄存器的加载完成。该方法还包括使用来自平台寄存器的控制信息将来自平台寄存器的数据同时提交到高速缓存阵列的字线，从而减少高速缓存阵列的字线的繁忙时间。

10. 发明申请

US20110320697A1 DYNAMICALLY SUPPORTING VARIABLE CACHE ARRAY BUSY AND ACCESS TIMES 失效
标题翻译：动态地支持可变缓存队列和访问时间
公开(公告)号：US20110320697A1
公开(公告)日：2011-12-29
申请号：US12822341
申请日：2010-06-24
申请人： Deanna P. Berger , Michael F. Fee , Arthur J. O'Neill
发明人： Deanna P. Berger , Michael F. Fee , Arthur J. O'Neill
IPC分类号： G06F12/08 , G06F12/02
CPC分类号： G06F12/0851
摘要： Various embodiments of the present invention manage access to a cache memory. In or more embodiments a request for a targeted interleave within a cache memory is received. The request is associated with an operation of a given type. The target is determined to be available. The request is granted in response to the determining that the target is available. A first interleave availability table associated with a first busy time associated with the cache memory is updated based on the operation associated with the request in response to granting the request. A second interleave availability table associated with a second busy time associated with the cache memory is updated based on the operation associated with the request in response to granting the request.
摘要翻译：本发明的各种实施例管理对高速缓冲存储器的访问。在一个或多个实施例中，接收对高速缓冲存储器内的目标交错的请求。该请求与给定类型的操作相关联。目标被确定为可用。响应于确定目标可用的请求被授予。基于与请求相关联的操作来响应于授予请求来更新与与高速缓冲存储器相关联的第一繁忙时间相关联的第一交错可用性表。基于与请求相关联的响应于响应于授予请求而更新与与高速缓冲存储器相关联的第二繁忙时间相关联的第二交织可用性表。

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