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    • 34. 发明授权
    • Projector
    • 投影机
    • US06572231B1
    • 2003-06-03
    • US09518187
    • 2000-03-02
    • Nobuo Watanabe
    • Nobuo Watanabe
    • G03B2116
    • H04N9/3141H04N9/3102
    • A projector is provided that includes a cooling structure which efficiently cools an electrooptic device, and which can cope with an increase in brightness of a light source and a reduction in size of the projector. A cooling fan for introducing cooling air is mounted above an air inlet, and a regulating fan for regulating the cooling air introduced by the cooling fan is mounted at a position opposing the cooling fan across an electrooptic device. For this reason, the cooling air is formed in a substantially linear shape, and the electrooptic device can be uniformly and efficiently cooled without cooling only parts of the electrooptic device. This allows a cooling structure to be obtained which can cope with an increase in brightness of a light source lamp serving as a light source and a reduction in size of a projector.
    • 提供了一种投影仪,其包括有效地冷却电光装置的冷却结构,并且能够应对光源的亮度的增加和投影仪的尺寸的减小。 用于引入冷却空气的冷却风扇安装在空气入口的上方,并且用于调节由冷却风扇引入的冷却空气的调节风扇安装在与电光装置相对的冷却风扇的位置上。 为此,冷却空气形成为大致直线状,电光装置可以均匀有效地冷却,而不会仅冷却电光装置的一部分。 由此,能够获得能够应对作为光源的光源灯的亮度的增加和投影仪的尺寸变小的冷却结构。
    • 37. 发明授权
    • Multiport field memory
    • 多端口字段内存
    • US5708618A
    • 1998-01-13
    • US658312
    • 1996-06-05
    • Haruki TodaNobuo Watanabe
    • Haruki TodaNobuo Watanabe
    • G11C11/401G11C7/00G11C7/10G11C8/16G11C11/41
    • G11C7/10G11C7/1006G11C7/103G11C8/16
    • A multiport field memory includes cell arrays, bit line pairs, gate transmission circuits connecting to the bit line pairs, ports, and a data cross-transmission circuit. The data cross-transmission circuit has first and second transfer gate circuit pairs (each pair connected in series and each pair connected to each bit line pair). The ports, each includes a register for temporarily storing data and for transferring the data from or to the memory cell through the bit line pairs. Each port is connected to each bit line pair through each first and second transfer gate circuit pair. The data cross-transmission control circuit has the first and second transfer gate control circuit pairs to transfer first and second gate drive control signals in order to connect the bit line pair to the registers. The first transfer gate circuit in one pair of the first and second transfer gate circuit pairs is connected to the second transfer gate circuit in the same pair or another pair of the first and second transfer gate circuit pairs in order to transfer the data through a desired port under the control of the cross-transmission control circuit.
    • 多端口场存储器包括单元阵列,位线对,连接到位线对的栅极传输电路,端口和数据交叉传输电路。 数据交叉传输电路具有第一和第二传输门电路对(每对串联连接,每对连接到每个位线对)。 端口各自包括用于临时存储数据并通过位线对将数据从存储器单元传送到存储器单元的寄存器。 每个端口通过每个第一和第二传输门电路对连接到每个位线对。 数据交叉传输控制电路具有第一和第二传输门控制电路对以传送第一和第二栅极驱动控制信号,以将位线对连接到寄存器。 一对第一和第二传输门电路对中的第一传输门电路连接到同一对或另一对第一和第二传输门电路对中的第二传输门电路,以便通过期望的 端口在交叉传输控制电路的控制下。
    • 38. 发明授权
    • Multiport DRAM
    • 多端口DRAM
    • US5247484A
    • 1993-09-21
    • US865229
    • 1992-04-08
    • Nobuo Watanabe
    • Nobuo Watanabe
    • G11C11/401G11C7/10G11C11/4096G11C11/41
    • G11C7/1006G11C11/4096G11C7/1075
    • A plurality of RAM blocks constituting a first RAM section and a second RAM section, respectively are arranged alternately in such a way that the inversion bit lines and the non-inversion bit lines of these RAM blocks are changed alternately block by block and further the two adjacent bit lines of the two adjacent RAM blocks are connected in common as a data line of the SAM blocks. By controlling data transfer control gates for switching on-off conditions of four bit lines of the two adjacent RAM blocks, it is possible to realize a cross transfer such that data can be transferred not only from the RAM blocks of the first RAM section and the second RAM section to the first SAM section and the second SAM section disposed as to correspond to the RAM sections, respectively, but also from the RAM blocks of the first RAM section to the SAM blocks of the adjacent second SAM section and additionally from the RAM blocks of the second RAM section to the RAM blocks of the adjacent first SAM section. Therefore, it is possible to continuously read and write data from and to the same RAM block, in addition to the alternate data read and write operation between the RAM blocks.
    • 构成第一RAM部分和第二RAM部分的多个RAM块分别以这样的方式交替布置,使得这些RAM块的反转位线和非反转位线交替地逐块改变,并且另外两个 两个相邻RAM块的相邻位线作为SAM块的数据线共同连接。 通过控制用于切换两个相邻RAM块的四位线的开关状态的数据传送控制门,可以实现交叉传送,使得不仅可以从第一RAM部分的RAM块和 第二RAM部分分配给第一SAM部分,第二SAM部分分别设置为对应于RAM部分,而且从第一RAM部分的RAM块到相邻的第二SAM部分的SAM块以及另外从RAM 第二RAM部分的块到相邻的第一SAM部分的RAM块。 因此,除了RAM块之间的备用数据读写操作之外,还可以连续读取和写入到同一RAM块中的数据。