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31. 发明申请

US20080237574A1 Metal-Base Nanowire Transistor 失效
标题翻译：金属基纳米线晶体管
公开(公告)号：US20080237574A1
公开(公告)日：2008-10-02
申请号：US12093790
申请日：2006-10-29
申请人： Prabhat Agarwal , Godfridus Adrianus Maria Hurkx
发明人： Prabhat Agarwal , Godfridus Adrianus Maria Hurkx
IPC分类号： H01L29/737
CPC分类号： H01L29/7606 , B82Y10/00 , H01L29/0665 , H01L29/0673 , Y10S977/936
摘要： A metal-base transistor is suggested. The transistor comprises a first and a second electrode (2, 6) and base electrode (6) to control current flow between the first and second electrode. The first electrode (2) is made from a semiconduction material. The base electrode (3) is a metal layer deposited on top of the semiconducting material forming the first electrode. According the invention the second electrode is formed by a semiconducting nanowire (6) being in electrical contact with the base electrode (3).
摘要翻译：建议使用金属晶体管。晶体管包括用于控制第一和第二电极之间的电流的第一和第二电极（2,6）和基极（6）。第一电极（2）由半导体材料制成。基极（3）是沉积在形成第一电极的半导体材料的顶部上的金属层。根据本发明，第二电极由与基极（3）电接触的半导体纳米线（6）形成。

32. 发明授权

US08330090B2 Photosensitive device and method of manufacturing a photosensitive device using nanowire diodes 有权
标题翻译：使用纳米线二极管制造感光装置的感光装置和方法
公开(公告)号：US08330090B2
公开(公告)日：2012-12-11
申请号：US12597263
申请日：2008-04-29
申请人： Prabhat Agarwal
发明人： Prabhat Agarwal
IPC分类号： G01J1/42
CPC分类号： H01L31/0352 , H01L27/1446
摘要： A photosensitive device (100), the photosensitive device (100) comprising a substrate (101) and a plurality of vertically aligned nanowire diodes (102 to 105) provided on and/or in the substrate (101).
摘要翻译：一种感光装置（100），所述感光装置（100）包括衬底（101）和设置在衬底（101）上和/或衬底（101）中的多个垂直排列的纳米线二极管（102至105）。

33. 发明授权

US07989844B2 Semiconductor device and method of manufacturing such a device 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07989844B2
公开(公告)日：2011-08-02
申请号：US10545736
申请日：2004-02-12
申请人： Rob Van Dalen , Prabhat Agarwal , Jan Willem Slotboom , Gerrit Elbert Johannes Koops
发明人： Rob Van Dalen , Prabhat Agarwal , Jan Willem Slotboom , Gerrit Elbert Johannes Koops
IPC分类号： H01L29/732 , H01L29/737
CPC分类号： H01L29/66242 , H01L29/7378
摘要： The invention relates to a semiconductor device with a substrate (11) and a semiconductor body (12) with a heterojunction bipolar, in particular npn, transistor with an emitter region (1), a base region (2) and a collector region (3), which are provided with, respectively, a first, a second and a third connection conductor (4, 5, 6), and wherein the bandgap of the base region (2) is smaller than that of the collector region (3) or of the emitter region (1), for example by the use of a silicon-germanium mixed crystal instead of pure silicon in the base region (2). Such a device is characterized by a very high speed, but its transistor shows a relatively low BVeeo. In a device (10) according to the invention the doping flux of the emitter region (1) is locally reduced by a further semiconductor region (20) of the second conductivity type which is embedded in the emitter region (1). In this way, on the one hand, a low-impedance emitter contact is ensured, while locally the Gummel number is increased without the drawbacks normally associated with such an increase. In this way, the hole current in the, npn, transistor is increased and thus the gain is decreased. The relatively high gain of a Si—Ge transistor is responsible for the low BVCeOf which is consequently avoided in a device (10) according to the invention. Preferably the further semiconductor region (20) is recessed in the emitter region (1) and said emitter region (1) preferably comprises a lower doped part that borders on the base region (2) and that is situated below the further semiconductor region (20). The invention also comprises a method of manufacturing a semiconductor device (10) according to the invention.
摘要翻译：本发明涉及具有衬底（11）和具有异质结双极性的半导体本体（12）的半导体器件，特别是具有发射极区域（1），基极区域（2）和集电极区域（3）的npn晶体管），其分别设置有第一，第二和第三连接导体（4,5,6），并且其中所述基极区域（2）的带隙小于所述集电极区域（3）的带隙或的发射极区域（1），例如通过在基极区域（2）中使用硅 - 锗混合晶体代替纯硅。这种器件的特点是非常高的速度，但其晶体管显示相对较低的BVeeo。在根据本发明的器件（10）中，发射极区域（1）的掺杂通量被嵌入在发射极区域（1）中的第二导电类型的另外的半导体区域（20）局部地减小。以这种方式，一方面，确保了低阻抗发射极接触，而局部地增加了Gummel数量，而没有通常与这种增加相关联的缺点。以这种方式，npn晶体管中的空穴电流增加，因此增益降低。 Si-Ge晶体管的相对高的增益负责在本发明的器件（10）中避免的低BVCeOf。优选地，另外的半导体区域（20）凹陷在发射极区域（1）中，并且所述发射极区域（1）优选地包括在基极区域（2）上接合并位于另外的半导体区域（20）下方的下部掺杂部分）。本发明还包括制造根据本发明的半导体器件（10）的方法。

34. 发明申请

US20110018065A1 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE 审中-公开
标题翻译：制造半导体器件和半导体器件的方法
公开(公告)号：US20110018065A1
公开(公告)日：2011-01-27
申请号：US12918398
申请日：2009-02-17
申请人： Gilberto Curatola , Prabhat Agarwal , Mark J. H. Van Dal , Vijayaraghavan Madakasira
发明人： Gilberto Curatola , Prabhat Agarwal , Mark J. H. Van Dal , Vijayaraghavan Madakasira
IPC分类号： H01L29/775 , H01L27/088 , H01L21/336
CPC分类号： H01L29/7854 , B82Y10/00 , H01L29/0665 , H01L29/0673 , H01L29/068 , H01L29/42392 , H01L29/66795 , H01L29/775
摘要： A method of manufacturing a semiconductor device is disclosed comprising providing an insulating carrier (10) such as an oxide wafer; providing a channel structure (20) between a source structure (12) and a drain structure (14) on said carrier (10); selectively removing a part of the channel structure (20), thereby forming a recess (22) between the channel structure (20) and the carrier (10); exposing the device to an annealing step such that the channel structure (20′) obtains a substantially cylindrical shape; forming a confinement layer (40) surrounding the substantially cylindrical channel structure (20′); growing an oxide layer (50) surrounding the confinement layer (40); and forming a gate structure (60) surrounding the oxide layer (50). The substantially cylindrical channel structure 20′ may comprise the semiconductor layer 30. A corresponding semiconductor device is also disclosed.
摘要翻译：公开了一种制造半导体器件的方法，其包括提供绝缘载体（10），例如氧化物晶片; 在所述载体（10）上的源极结构（12）和漏极结构（14）之间提供沟道结构（20）; 选择性地去除所述通道结构（20）的一部分，从而在所述通道结构（20）和所述载体（10）之间形成凹部（22）。将所述装置暴露于退火步骤，使得所述通道结构（20'）获得基本上圆柱形的形状; 形成围绕所述基本上圆柱形的通道结构（20'）的约束层（40）; 生长围绕限制层（40）的氧化物层（50）; 以及形成围绕所述氧化物层（50）的栅极结构（60）。基本上圆柱形的沟道结构20'可以包括半导体层30.还公开了相应的半导体器件。

35. 发明授权

US07838368B2 Nanoscale fet 有权
标题翻译：纳米级
公开(公告)号：US07838368B2
公开(公告)日：2010-11-23
申请号：US11632738
申请日：2005-07-12
申请人： Radu Surdeanu , Prabhat Agarwal , Abraham Rudolf Balkenende , Erik P. A. M. Bakkers
发明人： Radu Surdeanu , Prabhat Agarwal , Abraham Rudolf Balkenende , Erik P. A. M. Bakkers
IPC分类号： H01L21/336 , H01L29/775
CPC分类号： H01L29/78 , B82Y10/00 , B82Y40/00 , H01L29/0665 , H01L29/0673 , H01L29/20 , H01L29/76 , Y10S438/962 , Y10S977/762 , Y10S977/818 , Y10S977/938
摘要： A transistor device is formed of a continuous linear nanostructure having a source region, a drain region and a channel region between the source and drain regions. The source (20) and drain (26) regions are formed of nanowire ania the channel region (24) is in the form of a nanotube. An insulated gate (32) is provided adjacent to the channel region (24) for controlling conduction i ni the channel region between the source and drain regions.
摘要翻译：晶体管器件由具有源极区，漏极区和源极和漏极区之间的沟道区的连续线性纳米结构形成。源极（20）和漏极（26）区域由纳米线形成，沟道区域（24）呈纳米管形式。绝缘栅极（32）设置成邻近沟道区（24），用于控制源极和漏极区之间的沟道区。

36. 发明授权

US07660180B2 Dielectric antifuse for electro-thermally programmable device 有权
标题翻译：用于电热可编程器件的介质反熔丝
公开(公告)号：US07660180B2
公开(公告)日：2010-02-09
申请号：US11720320
申请日：2005-11-24
申请人： Hans M. B. Boeve , Karen Attenborough , Godefridus A. M. Hurkx , Prabhat Agarwal , Hendrik G. A. Huizing , Michael A. A. In'T Zandt , Jan W. Slotboom
发明人： Hans M. B. Boeve , Karen Attenborough , Godefridus A. M. Hurkx , Prabhat Agarwal , Hendrik G. A. Huizing , Michael A. A. In'T Zandt , Jan W. Slotboom
IPC分类号： G11C17/18
CPC分类号： G11C11/5678 , G11C13/0004 , H01L27/2409 , H01L45/06 , H01L45/1233 , H01L45/1246 , H01L45/144
摘要： A thermally programmable memory has a programmable element (20) of a thermally programmable resistance preferably of phase change material, material and a blown antifuse (80) located adjacent to the programmable material. Such a blown antifuse has a dielectric layer (100) surrounded by conductive layers (90, 110) to enable a brief high voltage to be applied across the dielectric to blow a small hole in the dielectric during manufacture to form a small conductive path which can be used as a tiny electrical heater for programming the material. Due to the current confinement by the hole, the volume of the material that must be heated in order to switch to a highly-resistive state is very small. As a result the programming power can be low.
摘要翻译：热可编程存储器具有可编程电阻的可编程电阻（20），优选地是相变材料的材料和位于可编程材料附近的吹制反熔丝（80）。这种吹制的反熔丝具有由导电层（90,110）包围的电介质层（100），以使得能够在制造期间在电介质两端施加短暂的高电压来吹动电介质中的小孔，以形成小导电路径，用作编程材料的微小电加热器。由于目前由孔的限制，为了切换到高电阻状态必须被加热的材料的体积非常小。因此，编程功率可能很低。

37. 发明申请

US20090200536A1 Method for manufacturing an electric device with a layer of conductive material contracted by nanowire 有权
标题翻译：制造具有由纳米线收缩的导电材料层的电气装置的方法
公开(公告)号：US20090200536A1
公开(公告)日：2009-08-13
申请号：US11631212
申请日：2005-06-28
申请人： Robertus Theodorus Franciscus Van Schaijk , Prabhat Agarwal , Erik Petrus Antonius Maria Bakkers , Martijn Henri Richard Lankhorst , Michiel Jos Van Duuren , Abraham Rudolf Balkenende , Louis Felix Feiner , Pierre Hermanus Woerlee
发明人： Robertus Theodorus Franciscus Van Schaijk , Prabhat Agarwal , Erik Petrus Antonius Maria Bakkers , Martijn Henri Richard Lankhorst , Michiel Jos Van Duuren , Abraham Rudolf Balkenende , Louis Felix Feiner , Pierre Hermanus Woerlee
IPC分类号： H01L47/00 , H01L21/3205
CPC分类号： H01L45/1273 , B82Y10/00 , G11C13/0004 , G11C13/025 , G11C2213/81 , H01L21/28525 , H01L21/76879 , H01L27/2409 , H01L27/2436 , H01L27/2472 , H01L27/2481 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/148 , H01L45/16
摘要： The electric device (100) according to the invention comprises a layer (107) of a memory material which has an electrical resistivity switchable between a first value and a second value. The memory material may be a phase change material. The electric device (100) further comprises a set of nanowires (NW) electrically connecting a first terminal (172) of the electric device and the layer (107) of memory material thereby enabling conduction of an electric current from the first terminal via the nanowires (NW) and the layer (107) of memory material to a second terminal (272) of the electric device. Each nanowire (NW) electrically contacts the layer (107) of memory material in a respective contact area. All contact areas are substantially identical. The method according to the invention is suited to manufacture the electric device (100) according to the invention.
摘要翻译：根据本发明的电子设备（100）包括存储材料的层（107），其具有可在第一值和第二值之间切换的电阻率。记忆材料可以是相变材料。电气设备（100）还包括电连接电子设备的第一端子（172）和存储器材料层（107）的一组纳米线（NW），从而能够经由纳米线传导来自第一端子的电流（NW）和存储器材料层（107）连接到电气设备的第二端子（272）。每个纳米线（NW）在相应的接触区域中电接触存储器材料的层（107）。所有接触区域基本相同。根据本发明的方法适用于制造根据本发明的电子设备（100）。

38. 发明申请

US20090114950A1 Semiconductor Device and Method of Manufacturing such a Device 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20090114950A1
公开(公告)日：2009-05-07
申请号：US11597533
申请日：2005-05-19
申请人： Prabhat Agarwal , Jan Willem Slotboom , Gerben Doornbos
发明人： Prabhat Agarwal , Jan Willem Slotboom , Gerben Doornbos
IPC分类号： H01L21/336 , H01L21/8249 , H01L21/8232 , H01L29/78 , H01L29/80 , H01L21/8234 , H01L21/8248
CPC分类号： H01L21/8249
摘要： The invention relates to a semiconductor device (10) comprising a substrate (11) and a semiconductor body (1) of silicon having a semiconductor layer structure comprising, in succession, a first and a second semiconductor layer (2, 3), and having a surface region of a first conductivity type which is provided with a field effect transistor (M) with a channel of a second conductivity type, opposite to the first conductivity type, wherein the surface region is provided with source and drain regions (4A, 4B) of the second conductivity type for the field effect transistor (M) and with—interposed between said source and drain regions—a channel region (3A) with a lower doping concentration which forms part of the second semiconductor layer (3) and with a buried first-conductivity-type semiconductor region (2A), buried below the channel region (3A), with a doping concentration that is much higher than that of the channel region (3A) and which forms part of the first semiconductor layer (2). According to the invention, the semiconductor body (1) is provided not only with the field effect transistor (M) but also with a bipolar transistor (B) with emitter, base and collector regions (5A, 5B, 5C) of respectively the second, the first and the second conductivity type, and the emitter region (5A) is formed in the second semiconductor layer (3) and the base region (5B) is formed in the first semiconductor layer (2). In this way a Bi(C)MOS IC (10) is obtained which is very suitable for high-frequency applications and which is easy to manufacture using a method according to the invention. Preferably the first semiconductor layer (2) comprises Si—Ge and is delta-doped, whereas the second semiconductor layer (3) comprises strained Si.
摘要翻译：本发明涉及一种半导体器件（10），它包括具有半导体层结构的硅衬底（12）和半导体本体（1），半导体层结构依次包括第一和第二半导体层（2,3），并且具有具有与第一导电类型相反的具有第二导电类型的沟道的场效应晶体管（M）的第一导电类型的表面区域，其中所述表面区域设置有源极和漏极区域（4A，4B））和用于场效应晶体管（M）的第二导电类型，并且插入在所述源极和漏极区之间 - 具有较低掺杂浓度的沟道区（3A），其形成第二半导体层（3）的一部分，并且具有埋入第一导电型半导体区域（2A），其掺杂在沟道区域（3A）的下方，掺杂浓度比沟道区域（3A）的掺杂浓度高得多，并且形成第一半导体层（2）的一部分，。根据本发明，半导体本体（1）不仅设置有场效应晶体管（M），而且还具有双极晶体管（B），发射极，基极和集电极区域（5A，5B，5C）分别为第二第一和第二导电类型和发射极区域（5A）形成在第二半导体层（3）中，并且基极区域（5B）形成在第一半导体层（2）中。以这种方式获得了非常适合于高频应用并且易于使用根据本发明的方法制造的Bi（C）MOS IC（10）。优选地，第一半导体层（2）包括Si-Ge并且是δ掺杂的，而第二半导体层（3）包括应变Si。

39. 发明申请

US20090065704A1 IMPLEMENTATION OF AVALANCHE PHOTO DIODES IN (BI) CMOS PROCESSES 有权
标题翻译：（BI）CMOS工艺中的AVALANCHE照相二极管的实现
公开(公告)号：US20090065704A1
公开(公告)日：2009-03-12
申请号：US12298206
申请日：2007-04-10
申请人： Anco Heringa , Thomas Frach , Prabhat Agarwal
发明人： Anco Heringa , Thomas Frach , Prabhat Agarwal
IPC分类号： G01T1/20 , H01L27/00 , H01L21/00
CPC分类号： H01L31/115 , H01L27/1446 , H01L31/107 , H01L31/1804 , Y02E10/547 , Y02P70/521
摘要： A radiation detector (46) includes a semiconductor layer(s) (12) formed on a substrate (14) and a scintillator (30) formed on the semiconductor layer(s) (12). The semiconductor layer(s) (12) includes an n−doped region (16) disposed adjacent to the substrate (14), and a p−doped region (18) disposed adjacent to the n−doped region (16). A trench (20) is formed within the semiconductor layer(s) (12) and around the p−doped region (18) and is filled with a material (22) that reduces pn junction curvature at the edges of the pn junction, which reduces breakdown at the edges. The scintillator (30) is disposed over and optically coupled to the p−doped regions (18). The radiation detector (46) further includes at least one conductive electrode (24) that electrically contacts the n−doped region.
摘要翻译：辐射检测器（46）包括形成在衬底（14）上的半导体层（12）和形成在半导体层（12）上的闪烁体（30）。半导体层（12）包括邻近衬底（14）设置的n掺杂区域（16）和邻近于n掺杂区域（16）设置的p掺杂区域（18）。沟槽（20）形成在半导体层（12）内并且围绕p掺杂区域（18）并且填充有减小pn结边缘处的pn结曲率的材料（22），其中减少边缘的破坏。闪烁体（30）设置在p掺杂区域（18）上并且光耦合到p掺杂区域（18）。辐射检测器（46）还包括与n掺杂区域电接触的至少一个导电电极（24）。

40. 发明申请

US20090045852A1 Low Voltage Differential Signalling Driver with Pre-Emphasis 有权
标题翻译：具有预加重功能的低压差分信号驱动器
公开(公告)号：US20090045852A1
公开(公告)日：2009-02-19
申请号：US12092556
申请日：2005-11-04
申请人： Prabhat Agarwal
发明人： Prabhat Agarwal
IPC分类号： H03K3/00
CPC分类号： H04L25/026 , H03K19/018528
摘要： There is provided a LVDS driver arranged to receive an input signal which switches between two voltage levels. The driver comprises a pre-emphasis block (405) for generating a pre-emphasis signal having a first voltage level for a time period T1 after each switch of the input signal, and a second voltage level at all other times, a differential pair of outputs for generating a differential output voltage across a load resistor (RI); and a driver circuit (401) comprising two parallel branches, each branch being connected to one output and each branch being arranged to receive the pre-emphasis signal. The driver is arranged so that the total current flowing through the driver circuit is constant, and during time period T1, the total current flowing through the driver circuit flows through the load resistor, thereby producing a differential output voltage and at all other times, only some of the total current flowing through the driver circuit flows through the load resistor, thereby reducing the differential output voltage.
摘要翻译：提供了一个LVDS驱动器，其布置成接收在两个电压电平之间切换的输入信号。驱动器包括预加重块（405），用于在输入信号的每次切换之后产生具有第一电压电平的时间段T1的预加重信号，以及在所有其他时间的第二电压电平的差分对用于产生负载电阻（RI）两端的差分输出电压的输出; 以及包括两个并行分支的驱动器电路（401），每个分支连接到一个输出端，每个分支被布置成接收预加重信号。驱动器被布置成使得流过驱动器电路的总电流是恒定的，并且在时间段T1期间，流过驱动器电路的总电流流过负载电阻器，从而产生差分输出电压，并且在所有其他时间仅仅流过驱动电路的一部分总电流流过负载电阻，从而降低差分输出电压。

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