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31. 发明申请

US20060115941A1 Method of fabricating transistor including buried insulating layer and transistor fabricated using the same 有权
标题翻译：制造包括埋入绝缘层的晶体管的方法和使用其制造的晶体管
公开(公告)号：US20060115941A1
公开(公告)日：2006-06-01
申请号：US11257369
申请日：2005-10-24
申请人： Dong-Suk Shin
发明人： Dong-Suk Shin
IPC分类号： H01L21/8234 , H01L21/336
CPC分类号： H01L29/66636 , H01L29/165 , H01L29/517 , H01L29/665 , H01L29/6653 , H01L29/66628 , H01L29/66772 , H01L29/7848 , H01L29/78621 , H01L29/78639
摘要： In a method of fabricating a transistor including a buried insulating layer and transistor fabricated using the same, the method includes sequentially forming a sacrificial layer and a top semiconductor layer on a single crystalline semiconductor substrate. A gate pattern is formed on the top semiconductor layer. A sacrificial spacer is formed to cover sidewalls of the gate pattern. An elevated semiconductor layer is grown on a portion of the top semiconductor layer adjacent to the sacrificial spacer. The sacrificial spacer is removed. A portion of the top semiconductor layer from which the sacrificial spacer is removed is etched until the sacrificial layer is exposed, thereby forming a recess, which separates the top semiconductor layer into a first top semiconductor layer pattern and a second top semiconductor layer pattern, which remain under the gate pattern and the elevated semiconductor layer, respectively. The sacrificial layer is selectively removed. A buried insulating layer is formed to fill a region from which the sacrificial layer is removed. A buried semiconductor layer is grown in the recess. An extending recess extends from the recess and is formed to expose the semiconductor substrate. The extending recess separates the buried insulating layer into a first buried insulating layer pattern and a second buried insulating layer pattern, which are self-aligned to the first and second top semiconductor layer patterns, respectively.
摘要翻译：在制造包括掩埋绝缘层的晶体管和使用其制造的晶体管的方法中，该方法包括在单晶半导体衬底上顺序地形成牺牲层和顶部半导体层。在顶部半导体层上形成栅极图案。形成牺牲隔离物以覆盖栅极图案的侧壁。在与牺牲间隔物相邻的顶部半导体层的一部分上生长升高的半导体层。去除牺牲隔离物。去除牺牲隔离物的顶部半导体层的一部分被蚀刻直到牺牲层被暴露，从而形成将顶部半导体层分离为第一顶部半导体层图案和第二顶部半导体层图案的凹部，其中分别保持在栅极图案和升高的半导体层之下。牺牲层被选择性地去除。形成掩埋绝缘层以填充去除牺牲层的区域。在凹槽中生长掩埋半导体层。延伸凹部从凹部延伸并形成为露出半导体衬底。延伸凹部将掩埋绝缘层分别分别与第一和第二顶部半导体层图案自对准的第一掩埋绝缘层图案和第二掩埋绝缘层图案。

32. 发明授权

US09431478B2 Semiconductor device and method of fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US09431478B2
公开(公告)日：2016-08-30
申请号：US14600142
申请日：2015-01-20
申请人： Yeong-Jong Jeong , Jeong-Yun Lee , Geo-Myung Shin , Dong-Suk Shin , Si-Hyung Lee , Seo-Jin Jeong
发明人： Yeong-Jong Jeong , Jeong-Yun Lee , Geo-Myung Shin , Dong-Suk Shin , Si-Hyung Lee , Seo-Jin Jeong
IPC分类号： H01L27/088 , H01L29/06 , H01L29/78 , B82Y10/00 , H01L29/775 , H01L29/41
CPC分类号： H01L29/7848 , B82Y10/00 , H01L21/823814 , H01L21/823821 , H01L21/823878 , H01L27/0886 , H01L27/0924 , H01L29/06 , H01L29/0653 , H01L29/0673 , H01L29/0847 , H01L29/1608 , H01L29/161 , H01L29/165 , H01L29/413 , H01L29/42392 , H01L29/775 , H01L29/78 , H01L29/7851 , H01L29/7853 , H01L29/78696
摘要： A semiconductor device includes a first multi-channel active pattern defined by a field insulating layer and extending along a first direction, the first multi-channel active pattern including a first portion having a top surface protruding further in an upward direction than a top surface of the field insulating layer and a second portion on both sides of the first portion, the second portion having sidewalls with a continuous profile and a top surface protruding further in the upward direction than the top surface of the field insulating layer and protruding in the upward direction less than the top surface of the first portion, a gate electrode on the first portion of the first multi-channel active pattern and extending along a second direction different from the first direction, and a first source/drain region on the second portion of the first multi-channel active pattern and contacting the field insulating layer.
摘要翻译：一种半导体器件包括由场绝缘层限定并沿着第一方向延伸的第一多沟道有源图案，该第一多沟道有源图案包括第一部分，该第一部分具有在向上方向上进一步向上方突出的顶表面，所述场绝缘层和所述第一部分的两侧上的第二部分，所述第二部分具有连续轮廓的侧壁和在所述场绝缘层的顶表面上向上方向突出的顶表面，并且在向上方向上突出小于第一部分的顶表面的第一部分上的栅电极，在第一多通道有源图案的第一部分上并且沿着不同于第一方向的第二方向延伸的栅电极，以及在第一部分的第二部分上的第一源极/漏极区域第一多通道有源图案并接触场绝缘层。

33. 发明授权

US08748299B2 Semiconductor devices having an epitaxial layer on active regions and shallow trench isolation regions 有权
标题翻译：具有在有源区上的外延层和浅沟槽隔离区的半导体器件
公开(公告)号：US08748299B2
公开(公告)日：2014-06-10
申请号：US12656752
申请日：2010-02-16
申请人： Dong-Suk Shin
发明人： Dong-Suk Shin
IPC分类号： H01L21/36 , H01L21/20
CPC分类号： H01L29/6656 , H01L21/76232 , H01L29/665 , H01L29/66651 , H01L29/78
摘要： A semiconductor device includes an isolation layer pattern, an epitaxial layer pattern, a gate insulation layer pattern and a gate electrode. The isolation layer pattern is formed on a substrate, and defines an active region in the substrate. The isolation layer pattern extends in a second direction. The epitaxial layer pattern is formed on the active region and the isolation layer pattern, and has a width larger than that of the active region in a first direction perpendicular to the second direction. The gate insulation layer pattern is formed on the epitaxial layer pattern. The gate electrode is formed on the gate insulation layer pattern.
摘要翻译：半导体器件包括隔离层图案，外延层图案，栅极绝缘层图案和栅电极。隔离层图案形成在衬底上，并且在衬底中限定有源区。隔离层图案沿第二方向延伸。外延层图案形成在有源区和隔离层图案上，并且在垂直于第二方向的第一方向上具有大于有源区的宽度的宽度。栅极绝缘层图案形成在外延层图案上。栅电极形成在栅极绝缘层图案上。

34. 发明授权

US08227308B2 Method of fabricating semiconductor integrated circuit device 有权
标题翻译：制造半导体集成电路器件的方法
公开(公告)号：US08227308B2
公开(公告)日：2012-07-24
申请号：US12647806
申请日：2009-12-28
申请人： Ha-Jin Lim , Dong-Suk Shin , Pan-Kwi Park , Jun-Jung Kim , Tae-Gyun Kim
发明人： Ha-Jin Lim , Dong-Suk Shin , Pan-Kwi Park , Jun-Jung Kim , Tae-Gyun Kim
IPC分类号： H01L21/8238
CPC分类号： H01L21/28518 , H01L29/665 , H01L29/78 , H01L29/7843
摘要： A method of fabricating a semiconductor integrated circuit (IC) device can include forming a first silicide layer on at least a portion of a transistor on a substrate, forming nitrogen in the first silicide layer to form a second silicide layer, forming a first stress layer having a tensile stress on the substrate having the transistor formed thereon, and irradiating the first stress layer with ultraviolet (UV) light to form a second stress layer having greater tensile stress than the first stress layer.
摘要翻译：制造半导体集成电路（IC）器件的方法可以包括在衬底上的晶体管的至少一部分上形成第一硅化物层，在第一硅化物层中形成氮以形成第二硅化物层，形成第一应力层在其上形成有晶体管的衬底上具有拉伸应力，并且用紫外线（UV）光照射第一应力层以形成具有比第一应力层更大的拉伸应力的第二应力层。

35. 发明申请

US20110018044A1 ETCH STOP LAYERS AND METHODS OF FORMING THE SAME 有权
标题翻译：蚀刻停止层及其形成方法
公开(公告)号：US20110018044A1
公开(公告)日：2011-01-27
申请号：US12841245
申请日：2010-07-22
申请人： HA-JIN LIM , Pan-Kwi Park , Dong-Suk Shin
发明人： HA-JIN LIM , Pan-Kwi Park , Dong-Suk Shin
IPC分类号： H01L29/78 , H01L29/94 , H01L27/092 , H01L21/31
CPC分类号： H01L29/76 , H01L21/823807 , H01L27/092 , H01L29/7843
摘要： A semiconductor device includes a MOSFET, and a plurality of stress layers disposed on the MOSFET, wherein the stress layers include a first stress layer disposed on the MOSFET and a second stress layer disposed on the first stress layer, the first stress layer has a first stress and the second stress layer has a second stress, and the first stress is different from the second stress.
摘要翻译：半导体器件包括MOSFET和设置在MOSFET上的多个应力层，其中应力层包括设置在MOSFET上的第一应力层和设置在第一应力层上的第二应力层，第一应力层具有第一应力层应力和第二应力层具有第二应力，并且第一应力不同于第二应力。

36. 发明授权

US07855126B2 Methods of fabricating a semiconductor device using a cyclic selective epitaxial growth technique and semiconductor devices formed using the same 有权
标题翻译：使用循环选择性外延生长技术制造半导体器件的方法和使用其形成的半导体器件
公开(公告)号：US07855126B2
公开(公告)日：2010-12-21
申请号：US12043587
申请日：2008-03-06
申请人： Dong-Suk Shin , Hong-Jae Shin
发明人： Dong-Suk Shin , Hong-Jae Shin
IPC分类号： H01L21/76
CPC分类号： H01L29/66636 , H01L29/165 , H01L29/6656 , H01L29/6659 , H01L29/66628 , H01L29/7834 , H01L29/7848
摘要： Devices and methods of fabricating a conductive pattern of such devices comprise a non-single crystalline semiconductor pattern formed on a single crystalline semiconductor substrate, an insulating spacer formed on a sidewall of the non-single crystalline semiconductor pattern, the non-single crystalline semiconductor pattern selectively recessed using a cyclic selective epitaxial growth (SEG) process, and a silicide layer formed on the recessed non-single crystalline semiconductor pattern.
摘要翻译：制造这种器件的导电图案的器件和方法包括形成在单晶半导体衬底上的非单晶半导体图案，形成在非单晶半导体图案的侧壁上的绝缘间隔物，非单晶半导体图案使用循环选择性外延生长（SEG）工艺选择性地凹陷，以及形成在凹陷的非单晶半导体图案上的硅化物层。

37. 发明授权

US07847609B2 Duty detecting circuit and duty cycle corrector including the same 有权
标题翻译：占空比检测电路和占空比校正器包括相同的
公开(公告)号：US07847609B2
公开(公告)日：2010-12-07
申请号：US12343859
申请日：2008-12-24
申请人： Dong-Suk Shin
发明人： Dong-Suk Shin
IPC分类号： H03K7/08
CPC分类号： H03K5/1565 , H03K5/159 , H03K5/26
摘要： A duty cycle corrector includes a duty adjusting unit configured to adjust a duty cycle of an input clock in response to a duty correction code and generate an output clock, a duty detecting unit configured to measure a difference between a high pulse width and a low pulse width of the output clock and output a difference value, and an accumulating unit configured to accumulate the difference value to generate the duty correction code.
摘要翻译：占空比校正器包括：占空比调整单元，被配置为响应于占空比校正码调整输入时钟的占空比并产生输出时钟;占空比检测单元，被配置为测量高脉冲宽度与低脉冲之间的差输出时钟的宽度并输出差值;以及累加单元，被配置为累积差值以生成占空比校正码。

38. 发明授权

US07808043B2 Semiconductor device and methods of fabricating the same including forming spacers and etch stop layers with stress properties 有权
标题翻译：半导体器件及其制造方法包括形成具有应力特性的间隔物和蚀刻停止层
公开(公告)号：US07808043B2
公开(公告)日：2010-10-05
申请号：US11525024
申请日：2006-09-22
申请人： Ki-Chul Kim , Dong-Suk Shin , Yong-Kuk Jeong
发明人： Ki-Chul Kim , Dong-Suk Shin , Yong-Kuk Jeong
IPC分类号： H01L29/74 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119 , H01L21/8238 , H01L21/4763
CPC分类号： H01L21/823807 , H01L21/823864
摘要： A semiconductor device having an etch stop layer and a method of fabricating the same are provided. The semiconductor device may include a substrate and a first gate electrode formed on the substrate. An auxiliary spacer may be formed on the sidewall of the first gate electrode. An etch stop layer may be formed on the substrate having the auxiliary spacer. The etch stop layer and the auxiliary spacer may be formed of a material having a same stress property.
摘要翻译：提供了具有蚀刻停止层的半导体器件及其制造方法。半导体器件可以包括形成在衬底上的衬底和第一栅电极。可以在第一栅电极的侧壁上形成辅助间隔物。可以在具有辅助间隔物的衬底上形成蚀刻停止层。蚀刻停止层和辅助间隔物可以由具有相同应力特性的材料形成。

39. 发明申请

US20100164573A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20100164573A1
公开(公告)日：2010-07-01
申请号：US12494355
申请日：2009-06-30
申请人： Ja-Beom Koo , Dong-Suk Shin
发明人： Ja-Beom Koo , Dong-Suk Shin
IPC分类号： H03L7/06
CPC分类号： H03L7/0812 , H03K5/133 , H03K2005/00026 , H03L7/087
摘要： A semiconductor device, includes a clock delay unit configured to include a plurality of delay units connected in series, where the delay amount of each delay unit varies depending on a level of a control voltage, for delaying a source clock to generate a feedback clock and mixing clocks outputted from the respective delay units to generate a frequency multiplication clock, a harmonic lock determination unit configured to determine whether a harmonic lock has occurred based on a frequency difference between the source clock and the frequency multiplication clock, and a control voltage generator configured to adjust a level of the control voltage based on a phase difference between the source clock and the feedback clock and a determination result of the harmonic lock determination unit.
摘要翻译：一种半导体器件，包括：时钟延迟单元，被配置为包括串联连接的多个延迟单元，其中每个延迟单元的延迟量根据控制电压的电平而变化，用于延迟源时钟以产生反馈时钟; 从相应的延迟单元输出的混合时钟以产生倍频时钟;谐波锁定确定单元，被配置为基于源时钟和倍频时钟之间的频率差来确定是否发生了谐波锁定;以及控制电压发生器，基于源时钟和反馈时钟之间的相位差以及谐波锁定确定单元的确定结果来调节控制电压的电平。

40. 发明授权

US07701010B2 Method of fabricating transistor including buried insulating layer and transistor fabricated using the same 有权
标题翻译：制造包括埋入绝缘层的晶体管的方法和使用其制造的晶体管
公开(公告)号：US07701010B2
公开(公告)日：2010-04-20
申请号：US12206225
申请日：2008-09-08
申请人： Dong-Suk Shin
发明人： Dong-Suk Shin
IPC分类号： H01L29/786
CPC分类号： H01L29/66636 , H01L29/165 , H01L29/517 , H01L29/665 , H01L29/6653 , H01L29/66628 , H01L29/66772 , H01L29/7848 , H01L29/78621 , H01L29/78639
摘要： In a method of fabricating a transistor including a buried insulating layer and transistor fabricated using the same, the method includes sequentially forming a sacrificial layer and a top semiconductor layer on a single crystalline semiconductor substrate. A gate pattern is formed on the top semiconductor layer. A sacrificial spacer is formed to cover sidewalls of the gate pattern. An elevated semiconductor layer is grown on a portion of the top semiconductor layer adjacent to the sacrificial spacer. The sacrificial spacer is removed. A portion of the top semiconductor layer from which the sacrificial spacer is removed is etched until the sacrificial layer is exposed, thereby forming a recess, which separates the top semiconductor layer into a first top semiconductor layer pattern and a second top semiconductor layer pattern, which remain under the gate pattern and the elevated semiconductor layer, respectively. The sacrificial layer is selectively removed. A buried insulating layer is formed to fill a region from which the sacrificial layer is removed. A buried semiconductor layer is grown in the recess. An extending recess extends from the recess and is formed to expose the semiconductor substrate. The extending recess separates the buried insulating layer into a first buried insulating layer pattern and a second buried insulating layer pattern, which are self-aligned to the first and second top semiconductor layer patterns, respectively.
摘要翻译：在制造包括掩埋绝缘层的晶体管和使用其制造的晶体管的方法中，该方法包括在单晶半导体衬底上顺序地形成牺牲层和顶部半导体层。在顶部半导体层上形成栅极图案。形成牺牲隔离物以覆盖栅极图案的侧壁。在与牺牲间隔物相邻的顶部半导体层的一部分上生长升高的半导体层。去除牺牲隔离物。去除牺牲隔离物的顶部半导体层的一部分被蚀刻直到牺牲层被暴露，从而形成将顶部半导体层分离为第一顶部半导体层图案和第二顶部半导体层图案的凹部，其中分别保持在栅极图案和升高的半导体层之下。牺牲层被选择性地去除。形成掩埋绝缘层以填充去除牺牲层的区域。在凹槽中生长掩埋半导体层。延伸凹部从凹部延伸并形成为露出半导体衬底。延伸凹部将掩埋绝缘层分别分别与第一和第二顶部半导体层图案自对准的第一掩埋绝缘层图案和第二掩埋绝缘层图案。

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