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31. 发明申请

US20110109381A1 Integrated Circuit Die Stacks With Rotationally Symmetric Vias 有权
标题翻译：具有旋转对称通孔的集成电路模块
公开(公告)号：US20110109381A1
公开(公告)日：2011-05-12
申请号：US12616563
申请日：2009-11-11
申请人： Jimmy G. Foster, SR. , Kyu-Hyoun Kim
发明人： Jimmy G. Foster, SR. , Kyu-Hyoun Kim
IPC分类号： H01L25/00 , H01L25/065 , H01L21/822
CPC分类号： H01L23/5384 , H01L21/822 , H01L25/0657 , H01L2224/16 , H01L2225/06527 , H01L2225/06541 , H01L2225/06555
摘要： An integrated circuit die stack including a first integrated circuit die mounted upon a substrate, the first die including pass-through vias (‘PTVs’) composed of conductive pathways through the first die with no connection to any circuitry on the first die; and a second integrated circuit die, identical to the first die, rotated with respect to the first die and mounted upon the first die, with the PTVs in the first die connecting signal lines from the substrate through the first die to through silicon vias (TSVs') in the second die composed of conductive pathways through the second die connected to electronic circuitry on the second die; with the TSVs and PTVs disposed upon each identical die so that the positions of the TSVs and PTVs on each identical die are rotationally symmetrical with respect to the TSVs and PTVs on the other identical die.
摘要翻译：一种集成电路管芯堆叠，其包括安装在衬底上的第一集成电路管芯，所述第一管芯包括由通过所述第一管芯的导电通路组成的通孔（“PTV”），其没有连接到所述第一管芯上的任何电路; 以及第一集成电路管芯，与第一管芯相同，相对于第一管芯旋转并安装在第一管芯上，第一管芯中的PTV将来自衬底的信号线通过第一管芯连接到硅通孔（TSV） '）在由连接到第二管芯上的电子电路的第二管芯的导电通路组成的第二管芯中; 其中TSV和PTV设置在每个相同的管芯上，使得每个相同管芯上的TSV和PTV的位置相对于另一相同管芯上的TSV和PTV旋转对称。

32. 发明授权

US07882417B2 Semiconductor memory device and memory system including the same 有权
标题翻译：半导体存储器件和包括其的存储器系统
公开(公告)号：US07882417B2
公开(公告)日：2011-02-01
申请号：US11705151
申请日：2007-02-12
申请人： Hoe-Ju Chung , Kyu-Hyoun Kim
发明人： Hoe-Ju Chung , Kyu-Hyoun Kim
IPC分类号： G11C29/00 , H03M13/29
CPC分类号： H03M13/29 , G06F11/08 , G06F11/1008 , G11C7/1006 , G11C29/42 , G11C2029/0411 , G11C2207/104
摘要： A semiconductor memory device and a memory system including the same are provided. The semiconductor memory device may include a first memory cell array block generating first data, a second memory cell array block generating second data, and first and second error detection code generators. The first error detection code generator may generate a first error detection code and may combine a portion of bits of the first error detection code with a portion of bits of a second error detection code to generate a first final error detection signal. The second error detection code generator may generate the second error detection code and may combine the remaining bits other than the portion of bits of the second error detection code with the remaining bits other than the portion of bits of the first error detection code to generate a second final error detection signal.
摘要翻译：提供一种半导体存储器件和包括该半导体存储器件的存储器系统。半导体存储器件可以包括产生第一数据的第一存储单元阵列块，产生第二数据的第二存储单元阵列块，以及第一和第二错误检测码发生器。第一错误检测码发生器可以产生第一错误检测码，并且可以将第一错误检测码的位的一部分与第二错误检测码的位的一部分组合以产生第一最终错误检测信号。第二错误检测码发生器可以产生第二错误检测码，并且可以将除了第二错误检测码的位的部分之外的其余位与除第一错误检测码的位的部分之外的其余位组合以产生第二最终错误检测信号。

33. 发明申请

US20100123216A1 Semiconductor integrated circuit including a power supply, semiconductor system including a semiconductor integrated circuit, and method of forming a semiconductor integrated circuit 失效
标题翻译：包括电源的半导体集成电路，包括半导体集成电路的半导体系统和形成半导体集成电路的方法
公开(公告)号：US20100123216A1
公开(公告)日：2010-05-20
申请号：US12656134
申请日：2010-01-19
申请人： Kyu-Hyoun Kim , Chang-Hyun Kim
发明人： Kyu-Hyoun Kim , Chang-Hyun Kim
IPC分类号： H01L29/92 , H01L21/02
CPC分类号： H01L23/58 , H01L23/5286 , H01L24/83 , H01L25/18 , H01L2224/48091 , H01L2224/48137 , H01L2224/83801 , H01L2924/01068 , H01L2924/14 , H01L2924/19104 , H01L2924/00014 , H01L2924/00
摘要： Provided are a semiconductor integrated circuit including a power supply, a semiconductor system including the semiconductor integrated circuit, and a method of forming the semiconductor integrated circuit. The semiconductor integrated circuit includes: a semiconductor substrate on a surface of which a plurality of electrical circuits and a plurality of power pads are mounted; an insulation layer stacked on the semiconductor substrate; a first conductive layer connected to a first power pad by a first via and stacked on the insulation layer; a second conductive layer connected to a second power pad by a second via, stacked on the insulation layer, and separated from the first insulation layer; and a power generation layer stacked on the first conductive layer and the second conductive layer and that generates voltage.
摘要翻译：提供了包括电源，包括半导体集成电路的半导体系统和形成半导体集成电路的方法的半导体集成电路。半导体集成电路包括：表面上安装有多个电路和多个电源焊盘的半导体衬底; 层叠在所述半导体基板上的绝缘层; 第一导电层，其通过第一通孔连接到第一功率垫并堆叠在所述绝缘层上; 通过第二通孔连接到第二功率垫的第二导电层，堆叠在绝缘层上并与第一绝缘层分离; 以及堆叠在第一导电层和第二导电层上并产生电压的发电层。

34. 发明授权

US07675158B2 Semiconductor integrated circuit including a power supply, and semiconductor system including a semiconductor integrated circuit 失效
标题翻译：包括电源的半导体集成电路和包括半导体集成电路的半导体系统
公开(公告)号：US07675158B2
公开(公告)日：2010-03-09
申请号：US11447943
申请日：2006-06-07
申请人： Kyu-Hyoun Kim , Chang-Hyun Kim
发明人： Kyu-Hyoun Kim , Chang-Hyun Kim
IPC分类号： H01L23/52 , H01L27/04 , H01L23/373 , H01L21/822
CPC分类号： H01L23/58 , H01L23/5286 , H01L24/83 , H01L25/18 , H01L2224/48091 , H01L2224/48137 , H01L2224/83801 , H01L2924/01068 , H01L2924/14 , H01L2924/19104 , H01L2924/00014 , H01L2924/00
摘要： Provided are a semiconductor integrated circuit including a power supply, a semiconductor system including the semiconductor integrated circuit, and a method of forming the semiconductor integrated circuit. The semiconductor integrated circuit includes: a semiconductor substrate on a surface of which a plurality of electrical circuits and a plurality of power pads are mounted; an insulation layer stacked on the semiconductor substrate; a first conductive layer connected to a first power pad by a first via and stacked on the insulation layer; a second conductive layer connected to a second power pad by a second via, stacked on the insulation layer, and separated from the first insulation layer; and a power generation layer stacked on the first conductive layer and the second conductive layer and that generates voltage.
摘要翻译：提供了包括电源，包括半导体集成电路的半导体系统和形成半导体集成电路的方法的半导体集成电路。半导体集成电路包括：表面上安装有多个电路和多个电源焊盘的半导体衬底; 层叠在所述半导体基板上的绝缘层; 第一导电层，其通过第一通孔连接到第一功率垫并堆叠在所述绝缘层上; 通过第二通孔连接到第二功率垫的第二导电层，堆叠在绝缘层上并与第一绝缘层分离; 以及堆叠在第一导电层和第二导电层上并产生电压的发电层。

35. 发明授权

US07573932B2 Spread spectrum clock generator 失效
标题翻译：扩频时钟发生器
公开(公告)号：US07573932B2
公开(公告)日：2009-08-11
申请号：US10837391
申请日：2004-04-29
申请人： Kyu-Hyoun Kim , Hoe-Ju Chung
发明人： Kyu-Hyoun Kim , Hoe-Ju Chung
IPC分类号： H04B1/00
CPC分类号： H04B15/02 , G06F1/08 , H03K5/133 , H03K5/156 , H03K2005/00071 , H04B2215/067
摘要： A spread spectrum clock generator includes a non-volatile memory to store control codes corresponding to a predetermined delay. A delay circuit receives a control code having a predetermined number of bits that determine a delay to apply to a fixed clock signal a period of time. The delay mitigates the electromagnetic interference caused by a periodic clock signal.
摘要翻译：扩频时钟发生器包括用于存储对应于预定延迟的控制码的非易失性存储器。延迟电路在一段时间内接收具有确定延迟的预定位数的控制码，以应用于固定时钟信号。该延迟减轻了周期性时钟信号引起的电磁干扰。

36. 发明申请

US20090113133A1 Synchronous Memory Having Shared CRC and Strobe Pin 失效
标题翻译：具有共享CRC和选通引脚的同步存储器
公开(公告)号：US20090113133A1
公开(公告)日：2009-04-30
申请号：US11923691
申请日：2007-10-25
申请人： Kyu-Hyoun Kim , Paul W. Coteus
发明人： Kyu-Hyoun Kim , Paul W. Coteus
IPC分类号： G06F12/00
CPC分类号： G06F13/1689 , G06F11/1004
摘要： A memory system having a memory element chip (DRAM) and a memory controller chips having a plurality of drivers and receivers and latches for transferred data. For writes clocks, write data and write for CRC (cyclic redundancy checks) is transferred to the DRAM from the memory controller and latched for error checking. The reads are clocked and the read data is received and transferred to a read data latch with also receives a clocked read strobe for verification of data integrity from DRAM. Each chip has a bi-functional pin that acts as a shared CRC pin during write and acts as a shared strobe pin during READ. Data transfers with the CRC signal and DQS signal are transferred across two paths CRC0/DQS and CRC1/DQS1. One could also transfer the CRC signal across one path with only the CRC0/DQS signal. Read operations have no CRC, and have no need for CRC because transfer errors during read can be detected by memory error correction coding (ECC). Write data provides source synchronous I/O data to said memory element chip needed for modem high speed memory communications.
摘要翻译：具有存储元件芯片（DRAM）的存储器系统和具有用于传送数据的多个驱动器和接收器以及锁存器的存储器控制器芯片。对于写时钟，写入数据和写入CRC（循环冗余校验）从存储器控制器传送到DRAM，并锁存进行错误检查。读取被计时，并且读取的数据被接收并被传送到读取数据锁存器，同时还接收用于从DRAM确认数据完整性的时钟读选通脉冲。每个芯片都有一个双功能引脚，在写入期间充当共享的CRC引脚，并在读取期间充当共享的选通引脚。具有CRC信号和DQS信号的数据传输通过两个路径CRC0 / DQS和CRC1 / DQS1传送。也可以通过CRC0 / DQS信号在一个路径上传送CRC信号。读操作没有CRC，并且不需要CRC，因为可以通过存储器纠错编码（ECC）来检测读取期间的传输错误。写入数据将源同步I / O数据提供给调制解调器高速存储器通信所需的所述存储器元件芯片。

37. 发明授权

US07439772B2 Level shifting circuit and method reducing leakage current 失效
标题翻译：电平移动电路和减少漏电流的方法
公开(公告)号：US07439772B2
公开(公告)日：2008-10-21
申请号：US11154725
申请日：2005-06-15
申请人： Chul-Woo Park , Kyu-Hyoun Kim , Beom-Sig Cho
发明人： Chul-Woo Park , Kyu-Hyoun Kim , Beom-Sig Cho
IPC分类号： H03K19/0175
CPC分类号： H03K19/018521 , H03K19/00361
摘要： A level shifting circuit and method that reduce leakage current are provided. The level shifting circuit includes: a logic circuit including a plurality of MOSFETs (metal-oxide-semiconductor field effect transistors) connected in series between an output terminal and a source, receiving an input signal having a first logic level and a second logic level, changing the input signal to a signal having a first logic level and a third logic level in response to a feedback signal supplied to one of the MOSFETs, and outputting the changed signal as an output signal; and a feedback circuit generating the feedback signal in response to the output signal.
摘要翻译：提供降低泄漏电流的电平移动电路和方法。电平移位电路包括：逻辑电路，包括串联连接在输出端和源之间的多个MOSFET（金属氧化物半导体场效应晶体管），接收具有第一逻辑电平和第二逻辑电平的输入信号，响应于提供给一个MOSFET的反馈信号，将输入信号改变为具有第一逻辑电平和第三逻辑电平的信号，并输出改变的信号作为输出信号; 以及响应于输出信号产生反馈信号的反馈电路。

38. 发明申请

US20070133247A1 Memory system having point-to-point (PTP) and point-to-two-point (PTTP) links between devices 有权
标题翻译：在设备之间具有点到点（PTP）和点到两点（PTTP）链路的存储器系统
公开(公告)号：US20070133247A1
公开(公告)日：2007-06-14
申请号：US11603648
申请日：2006-11-22
申请人： Jae-Jun Lee , Joo-Sun Choi , Kyu-Hyoun Kim , Kwang-Soo Park
发明人： Jae-Jun Lee , Joo-Sun Choi , Kyu-Hyoun Kim , Kwang-Soo Park
IPC分类号： G11C5/06
CPC分类号： G11C5/063
摘要： A memory system has first and second primary memories and first and second secondary memories coupled to the first and second primary memories, respectively, the coupling comprising at least one point-to-point connection. A memory module includes at least two of the first and second primary and first and second secondary memories. A first connection element, such as a connector or solder, connects the memory module to a mother board. A second connection element, such as a connector or solder, connects at least one other of the first and second primary and first and second secondary memories to the mother board. At least one of the memories on the first memory module is coupled to at least one of the other memories. The memory system also includes a memory controller which is connected to the primary memories by a point-to-two-point link.
摘要翻译：存储器系统具有第一和第二主存储器以及分别耦合到第一和第二主存储器的第一和第二辅助存储器，耦合器包括至少一个点到点连接。存储器模块包括第一和第二主要和第一和第二辅助存储器中的至少两个。诸如连接器或焊料的第一连接元件将存储器模块连接到母板。诸如连接器或焊料的第二连接元件将第一和第二初级和第二和第二辅助存储器中的至少一个连接到母板。第一存储器模块上的至少一个存储器耦合到至少一个其他存储器。存储器系统还包括存储器控制器，其通过点对二点链接连接到主存储器。

39. 发明申请

US20070109058A1 Differential amplifier, differential amplifying method, and phase locked loop and delay locked loop using the same 有权
标题翻译：差分放大器，差分放大法，锁相环和延迟锁相环使用相同
公开(公告)号：US20070109058A1
公开(公告)日：2007-05-17
申请号：US11594448
申请日：2006-11-08
申请人： Jin-Young Kim , Kyu-Hyoun Kim
发明人： Jin-Young Kim , Kyu-Hyoun Kim
IPC分类号： H03B27/00
CPC分类号： H03F3/45183 , H03F2203/45371 , H03K5/1565 , H03K2005/00052 , H03L7/08 , H03L7/0812 , H03L7/0996
摘要： A differential amplifier includes an input stage, a biasing unit and a load unit. The input stage receives a first phase signal and at least two phase signals among odd-numbered phase signals, wherein an average of phases of the at least two phase signals has a phase difference of substantially 180 degrees from the first phase signal. The biasing unit is coupled between the input stage and a first power voltage. The load unit is coupled between the input stage and a second power voltage, and configured to output a differential output signal based on differentially amplifying of the first phase signal and the at least two phase signals. Therefore, a duty cycle distortion in an output signal of a duty cycle correction circuit can be prevented.
摘要翻译：差分放大器包括输入级，偏置单元和负载单元。输入级在奇数相位信号中接收第一相位信号和至少两个相位信号，其中至少两个相位信号的相位平均值具有与第一相位信号基本上180度的相位差。偏压单元耦合在输入级和第一电源电压之间。负载单元耦合在输入级和第二电源电压之间，并且被配置为基于第一相位信号和至少两个相位信号的差分放大来输出差分输出信号。因此，可以防止占空比校正电路的输出信号中的占空比失真。

40. 发明授权

US07057433B2 Delay-Locked Loop (DLL) capable of directly receiving external clock signals 失效
标题翻译：能够直接接收外部时钟信号的延迟锁定环（DLL）
公开(公告)号：US07057433B2
公开(公告)日：2006-06-06
申请号：US10774933
申请日：2004-02-09
申请人： Guen-Hee Cho , Kyu-Hyoun Kim
发明人： Guen-Hee Cho , Kyu-Hyoun Kim
IPC分类号： H03L7/00
CPC分类号： H03L7/0814
摘要： A delay-locked loop (DLL) capable of directly receiving external clock signals is provided. The DLL comprises a level selector, a control signal generator, and an internal clock signal generator. The level selector receives an external clock signal, and directly outputs the external clock signal, or changes a level of the external clock signal and outputs a changed external clock signal, in response to a control signal. The control signal generator generates the control signal. The internal clock signal generator receives an output signal of the level selector and the external clock signal, and generates an internal clock signal synchronized to a phase of an output signal of the level selector.
摘要翻译：提供能够直接接收外部时钟信号的延迟锁定环（DLL）。 DLL包括电平选择器，控制信号发生器和内部时钟信号发生器。电平选择器接收外部时钟信号，并且响应于控制信号直接输出外部时钟信号，或改变外部时钟信号的电平并输出改变的外部时钟信号。控制信号发生器产生控制信号。内部时钟信号发生器接收电平选择器和外部时钟信号的输出信号，并且产生与电平选择器的输出信号的相位同步的内部时钟信号。

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