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31. 发明授权

US08055838B2 Apparatus and method for autonomically suspending and resuming logical partitions when I/O reconfiguration is required 有权
标题翻译：需要I / O重新配置时，自动暂停和恢复逻辑分区的装置和方法
公开(公告)号：US08055838B2
公开(公告)日：2011-11-08
申请号：US10624808
申请日：2003-07-22
申请人： David Alan Bailey , William Joseph Armstrong , Naresh Nayar , Gregory Michael Nordstrom
发明人： David Alan Bailey , William Joseph Armstrong , Naresh Nayar , Gregory Michael Nordstrom
IPC分类号： G06F13/10
CPC分类号： G06F9/5077
摘要： A partition manager includes an I/O reconfiguration mechanism and a logical partition suspend/resume mechanism that work together to perform autonomic I/O reconfiguration in a logically partitioned computer system. When I/O reconfiguration is required, the affected logical partitions are suspended, the I/O is reconfigured, and the affected logical partitions are resumed. Because the logical partitions are suspended during I/O reconfiguration, any ghost packet that may occur when the I/O is reconfigured is ignored.
摘要翻译：分区管理器包括I / O重新配置机制和逻辑分区挂起/恢复机制，其协同工作以在逻辑分区的计算机系统中执行自主I / O重新配置。当需要I / O重新配置时，受影响的逻辑分区将被挂起，重新配置I / O，并恢复受影响的逻辑分区。因为逻辑分区在I / O重新配置期间被挂起，所以当I / O被重新配置时可能发生的任何ghost数据包被忽略。

32. 发明授权

US08019962B2 System and method for tracking the memory state of a migrating logical partition 有权
标题翻译：用于跟踪迁移逻辑分区的内存状态的系统和方法
公开(公告)号：US08019962B2
公开(公告)日：2011-09-13
申请号：US11735809
申请日：2007-04-16
申请人： William Joseph Armstrong , Michael J. Corrigan , Stuart Zachary Jacobs , David Anthony Larson , Naresh Nayar , Wade Byron Ouren
发明人： William Joseph Armstrong , Michael J. Corrigan , Stuart Zachary Jacobs , David Anthony Larson , Naresh Nayar , Wade Byron Ouren
IPC分类号： G06F12/00
CPC分类号： G06F12/10 , G06F9/4856 , G06F9/5077 , G06F12/08 , G06F12/1036 , G06F12/109
摘要： An apparatus, program product and method for tracking the state of a migrating logical partition. Embodiments may use the state to determine the readiness and/or appropriateness of a page of the logical partition for transferring. The state may include a value or other data used to track changes affecting the page or the relative ease and/or appropriateness of migrating the page. A page manager table with entries corresponding to the state of each page of the logical partition may be used to track the state while the logical partition continues to run during a migration.
摘要翻译：用于跟踪迁移逻辑分区的状态的装置，程序产品和方法。实施例可以使用该状态来确定用于传送的逻辑分区的页面的准备和/或适当性。状态可以包括用于跟踪影响页面的变化的值或其他数据，或迁移页面的相对容易度和/或适当性。可以使用具有与逻辑分区的每个页面的状态对应的条目的页面管理器表来跟踪状态，同时逻辑分区在迁移期间继续运行。

33. 发明授权

US07822942B2 Selectively invalidating entries in an address translation cache 有权
标题翻译：选择性地使地址转换缓存中的条目无效
公开(公告)号：US07822942B2
公开(公告)日：2010-10-26
申请号：US12054538
申请日：2008-03-25
申请人： Michael J. Corrigan , Paul LuVerne Godtland , Joaquin Hinojosa , Cathy May , Naresh Nayar , Edward John Silha
发明人： Michael J. Corrigan , Paul LuVerne Godtland , Joaquin Hinojosa , Cathy May , Naresh Nayar , Edward John Silha
IPC分类号： G06F13/00
CPC分类号： G06F12/1036 , G06F12/126 , G06F2212/1016 , G06F2212/683
摘要： An apparatus and method selectively invalidate entries in an address translation cache instead of invalidating all, or nearly all, entries. One or more translation mode bits are provided in each entry in the address translation cache. These translation mode bits may be set according to the addressing mode used to create the cache entry. One or more “hint bits” are defined in an instruction that allow specifying which of the entries in the address translation cache are selectively preserved during an invalidation operation according to the value(s) of the translation mode bit(s). In the alternative, multiple instructions may be defined to preserve entries in the address translation cache that have specified addressing modes. In this manner, more intelligence is used to recognize that some entries in the address translation cache may be valid after a task or partition switch, and may therefore be retained, while other entries are invalidated.
摘要翻译：一种装置和方法选择性地使地址转换高速缓存中的条目无效，而不是使所有或几乎所有条目无效。在地址转换高速缓存中的每个条目中提供一个或多个翻译模式位。可以根据用于创建高速缓存条目的寻址模式来设置这些转换模式位。在指令中定义一个或多个“提示位”，该指令允许根据翻译模式位的值来指定在无效操作期间选择性地保留地址转换高速缓存中的哪些条目。在替代方案中，可以定义多个指令以保留具有指定寻址模式的地址转换高速缓存中的条目。以这种方式，使用更多的智能来识别地址转换高速缓存中的一些条目在任务或分区切换之后可能是有效的，并且因此可以被保留，而其他条目无效。

34. 发明授权

US07765428B2 Replacing a failing physical processor 有权
标题翻译：更换故障物理处理器
公开(公告)号：US07765428B2
公开(公告)日：2010-07-27
申请号：US12330087
申请日：2008-12-08
申请人： William J. Armstrong , Naresh Nayar , Gary R. Ricard
发明人： William J. Armstrong , Naresh Nayar , Gary R. Ricard
IPC分类号： G06F11/00
CPC分类号： G06F11/203 , G06F9/5066 , G06F11/2025 , G06F11/2035
摘要： Replacing a failing physical processor in a computer supporting multiple logical partitions, where the logical partitions include dedicated partitions and shared processor partitions, the dedicated partitions are supported by virtual processors having assigned physical processors, and the shared processor partitions are supported by pools of virtual processors. The pools of virtual processors have assigned physical processors. Embodiments operate generally by assigning priorities to the dedicated partitions and to the pools of virtual processors; detecting a checkstop of a failing physical processor; retrieving the failing physical processor's state; replacing by a hypervisor the failing physical processor with a replacement physical processor assigned to a dedicated partition or pool, which dedicated partition or pool has the lowest priority among the priorities of the dedicated partitions and pools; and assigning the retrieved state of the failing physical processor as the state of the replacement physical processor.
摘要翻译：在支持多个逻辑分区（其中逻辑分区包括专用分区和共享处理器分区）的计算机中替换故障物理处理器，专用分区由具有分配的物理处理器的虚拟处理器支持，并且共享处理器分区由虚拟处理器池支持。虚拟处理器池分配了物理处理器。实施例通常通过将优先级分配给专用分区和虚拟处理器池来进行操作; 检测故障物理处理器的检查停止; 检索故障物理处理器的状态; 由管理程序替换故障物理处理器，其中分配给专用分区或池的替换物理处理器，专用分区或池在专用分区和池的优先级中具有最低优先级; 以及将所述故障物理处理器的检索状态分配为所述替换物理处理器的状态。

35. 发明申请

US20090138220A1 Power-aware line intervention for a multiprocessor directory-based coherency protocol 审中-公开
标题翻译：基于多处理器目录的一致性协议的功率感知线路干预
公开(公告)号：US20090138220A1
公开(公告)日：2009-05-28
申请号：US11946551
申请日：2007-11-28
申请人： Robert H. Bell, JR. , Louis B. Capps, JR. , Thomas E. Cook , Michael J. Shapiro , Naresh Nayar
发明人： Robert H. Bell, JR. , Louis B. Capps, JR. , Thomas E. Cook , Michael J. Shapiro , Naresh Nayar
IPC分类号： G01R21/02 , G06F12/08
CPC分类号： G06F12/0817 , Y02D10/13
摘要： A directory-based coherency method, system and program are provided for intervening a requested cache line from a plurality of candidate memory sources in a multiprocessor system on the basis of the sensed temperature or power dissipation value at each memory source. By providing temperature or power dissipation sensors in each of the candidate memory sources (e.g., at cores, cache memories, memory controller, etc.) that share a requested cache line, control logic may be used to determine which memory source should source the cache line by using the power sensor signals to signal only the memory source with acceptable power dissipation to provide the cache line to the requester.
摘要翻译：基于目录的一致性方法，系统和程序被提供用于基于每个存储器源处的感测温度或功率耗散值来在多处理器系统中从多个候选存储器源插入所请求的高速缓存行。通过在共享所请求的高速缓存行的每个候选存储器源（例如，在内核，高速缓冲存储器，存储器控制器等）中提供温度或功率耗散传感器，可以使用控制逻辑来确定哪个存储器源应该来源于高速缓存通过使用功率传感器信号仅以可接受的功率消耗信号通知存储器源，以向请求器提供高速缓存线。

36. 发明申请

US20080168258A1 Method and Apparatus For Selecting the Architecture Level to Which a Processor Appears to Conform 有权
标题翻译：用于选择处理器符合的架构级别的方法和设备
公开(公告)号：US20080168258A1
公开(公告)日：2008-07-10
申请号：US11621393
申请日：2007-01-09
申请人： William J. Armstrong , Richard L. Arndt , Michael J. Corrigan , Giles R. Frazier , Timothy R. Marchini , Cathy May , Naresh Nayar , John T. O'Quin
发明人： William J. Armstrong , Richard L. Arndt , Michael J. Corrigan , Giles R. Frazier , Timothy R. Marchini , Cathy May , Naresh Nayar , John T. O'Quin
IPC分类号： G06F15/76 , G06F9/30
CPC分类号： G06F9/30101 , G06F9/30181 , G06F9/468
摘要： A method and system for selecting the architecture level to which a processor appears to conform within a computing environment when executing specific logical partitions or programs and performing migration among different levels of processor architecture. The method utilizes a “processor compatibility register” (PCR) that controls the level of the architecture that the processor appears to support. In one embodiment, the PCR is accessible only to super-privileged software. The super-privileged software sets bits in the PCR that specify the architecture level that the processor is to appear to support so that when the program runs on the processor, the processor behaves in accordance with the architecture level for which the program was designed.
摘要翻译：一种用于在执行特定逻辑分区或程序并且在不同级别的处理器架构之间执行迁移时，选择处理器在计算环境内符合的架构级别的方法和系统。该方法利用“处理器兼容性寄存器”（PCR）来控制处理器似乎支持的架构级别。在一个实施方案中，PCR仅可用于超特权软件。超级特权软件设置PCR中的位，指定处理器将要支持的架构级别，以便当程序在处理器上运行时，处理器的行为与程序设计的架构级别相符。

37. 发明申请

US20080134188A1 DEALLOCATION OF COMPUTER DATA IN A MULTITHREADED COMPUTER 失效
公开(公告)号：US20080134188A1
公开(公告)日：2008-06-05
申请号：US11970816
申请日：2008-01-08
申请人： William Joseph Armstrong , Peter Joseph Heyrman , Naresh Nayar
发明人： William Joseph Armstrong , Peter Joseph Heyrman , Naresh Nayar
IPC分类号： G06F9/46
CPC分类号： G06F9/52 , G06F9/5016 , G06F9/5022 , Y10S707/99953 , Y10S707/99957
摘要： An apparatus, program product and method support the deallocation of a data structure in a multithreaded computer without requiring the use of computationally expensive semaphores or spin locks. Specifically, access to a data structure is governed by a shared pointer that, when a request is received to deallocate the data structure, is initially set to a value that indicates to any thread that later accesses the pointer that the data structure is not available. In addition, to address any thread that already holds a copy of the shared pointer, and thus is capable of accessing the data structure via the shared pointer after the initiation of the request, all such threads are monitored to determine whether any thread is still using the shared pointer by determining whether any thread is executing program code that is capable of using the shared pointer to access the data structure. Once this condition is met, it is ensured that no thread can potentially access the data structure via the shared pointer, and as such, the data structure may then be deallocated.

38. 发明授权

US07376948B2 Selective generation of an asynchronous notification for a partition management operation in a logically-partitioned computer 有权
标题翻译：在逻辑分区的计算机中选择性地生成分区管理操作的异步通知
公开(公告)号：US07376948B2
公开(公告)日：2008-05-20
申请号：US10422425
申请日：2003-04-24
申请人： William Joseph Armstrong , Naresh Nayar , Gregory Michael Nordstrom , Timothy Joseph Torzewski
发明人： William Joseph Armstrong , Naresh Nayar , Gregory Michael Nordstrom , Timothy Joseph Torzewski
IPC分类号： G06F9/455 , G06F9/46 , G06F9/54 , G06F12/08
CPC分类号： G06F9/5077 , G06F9/542 , G06F2209/543 , G06F2209/544
摘要： A logically-partitioned computer, program product and method utilize a flexible and adaptable communication interface between a partition and a partition manager, which permits optimal handling of partition management operations such as state change operations and the like over a wide variety of circumstances. In particular, a partition is permitted to indicate, in connection with a request to perform a partition management operation, whether an asynchronous notification should be generated or suppressed in association with the performance of the partition management operation by a partition manager. As a result, asynchronous notifications are selectively generated in association with the performance of partition management operations based upon indications in the requests made by partitions for such operations.
摘要翻译：逻辑分区计算机，程序产品和方法利用分区和分区管理器之间的灵活且可适应的通信接口，其允许在各种情况下最佳地处理诸如状态改变操作等的分区管理操作。特别地，允许分区结合执行分区管理操作的请求来指示是否应该由分区管理器执行分区管理操作来生成或抑制异步通知。因此，基于由用于这种操作的分区所做的请求中的指示，与分区管理操作的执行相关联地选择性地生成异步通知。

39. 发明申请

US20080072079A1 System and Method for Implementing Predictive Capacity on Demand for Systems With Active Power Management 审中-公开
标题翻译：用于有源电力管理系统实现预期容量需求的系统和方法
公开(公告)号：US20080072079A1
公开(公告)日：2008-03-20
申请号：US11532333
申请日：2006-09-15
申请人： Andreas Bieswanger , Andrew Geissler , Hye-Young McCreary , Naresh Nayar , Freeman L. Rawson
发明人： Andreas Bieswanger , Andrew Geissler , Hye-Young McCreary , Naresh Nayar , Freeman L. Rawson
IPC分类号： G06F1/00
CPC分类号： G06F1/3203 , G06F1/3287 , G06F1/3293 , Y02D10/122 , Y02D10/171
摘要： A method, apparatus, and computer-usable medium for predicting capacity on a data processing system. According to a preferred embodiment of the present invention, a capacity manager estimates an incremental power value utilize for activating and maintaining an additional processor in the data processing system. The capacity manager calculates a power headroom value. In response to calculating the power headroom value, the capacity manager determines whether an adjustment power headroom value is required. The capacity manager calculates a projected capacity value added by the additional processor to the data processing system.
摘要翻译：一种用于预测数据处理系统的容量的方法，装置和计算机可用介质。根据本发明的优选实施例，容量管理器估计用于激活和维护数据处理系统中的附加处理器的增量功率值。容量管理器计算功率余量值。响应于计算功率余量值，容量管理器确定是否需要调节功率余量值。容量管理器计算由附加处理器添加到数据处理系统的预计容量值。

40. 发明申请

US20060230400A1 Allocating entitled processor cycles for preempted virtual processors 失效
公开(公告)号：US20060230400A1
公开(公告)日：2006-10-12
申请号：US11094712
申请日：2005-03-30
申请人： William Armstrong , Naresh Nayar
发明人： William Armstrong , Naresh Nayar
IPC分类号： G06F9/455
CPC分类号： G06F9/5077 , G06F9/4881
摘要： A method, apparatus, system, and signal-bearing medium that, in an embodiment, calculate a preemption credit for a partition if a virtual processor is preempted and the partition is unable to receive an entitled capacity of physical processor cycles during a dispatch window. The preemption credit is the portion of the entitled capacity that the partition is unable to receive. As long as the partition has a remaining preemption credit, in subsequent dispatch windows, a portion of the preemption credit is allocated to the virtual processor, and the preemption credit is reduced. In this way, in an embodiment, shared processor partitions may be ensured of receiving their entitled allocation of processor cycles.

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