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31. 发明授权

US08759915B2 Semiconductor field-effect transistor, memory cell and memory device 有权
标题翻译：半导体场效应晶体管，存储单元和存储器件
公开(公告)号：US08759915B2
公开(公告)日：2014-06-24
申请号：US12293534
申请日：2006-03-20
申请人： Paolo Rolandi , Cristiano Calligaro , Luigi Pascucci
发明人： Paolo Rolandi , Cristiano Calligaro , Luigi Pascucci
IPC分类号： H01L21/02
CPC分类号： H01L27/11551 , H01L21/8221 , H01L27/0688 , H01L27/1052 , H01L27/115 , H01L27/1203 , H01L29/7832
摘要： Semiconductor device formed by a first conductive strip of semiconductor material; a control gate region of semiconductor material, facing a channel portion of the first conductive strip, and an insulation region arranged between the first conductive strip and the control gate region. The first conductive strip includes a conduction line having a first conductivity type and a control line having a second conductivity type, arranged adjacent and in electrical contact with each other, and the conduction line forms the channel portion, a first conduction portion and a second conduction portion arranged on opposite sides of the channel portion.
摘要翻译：由半导体材料的第一导电条形成的半导体器件; 半导体材料的控制栅极区域，面对第一导电条的沟道部分，以及布置在第一导电条和控制栅极区域之间的绝缘区域。第一导电带包括具有第一导电类型的导线和具有彼此相邻并且彼此电接触布置的第二导电类型的控制线，并且导线形成沟道部分，第一导电部分和第二导电部分布置在通道部分的相对侧上。

32. 发明授权

US08635398B2 Execute-in-place mode configuration for serial non-volatile memory 有权
标题翻译：串行非易失性存储器的就地模式配置
公开(公告)号：US08635398B2
公开(公告)日：2014-01-21
申请号：US13143078
申请日：2008-12-30
申请人： Paolo Rolandi , Sandra Lospalluti , Raffaele Bufano , Stefano Andreoli , Tommaso Zerilli
发明人： Paolo Rolandi , Sandra Lospalluti , Raffaele Bufano , Stefano Andreoli , Tommaso Zerilli
IPC分类号： G06F12/00
CPC分类号： G06F12/0246 , G06F9/30098 , G06F9/44573 , G06F2212/72 , G06F2212/7206 , G11C16/26 , G11C2216/30
摘要： Example embodiments for configuring a serial non-volatile memory device for an execute-in-place mode may comprise a non-volatile configuration register to store an execute-in-place mode value that may be read at least in part in response to power being applied to the memory device.
摘要翻译：用于配置用于就地执行模式的串行非易失性存储器件的示例性实施例可以包括非易失性配置寄存器，用于存储至少部分地响应于功率而被读取的就地执行模式值应用于存储器件。

33. 发明申请

US20120110246A1 EXECUTE-IN-PLACE MODE CONFIGURATION FOR SERIAL NON-VOLATILE MEMORY 有权
标题翻译：串行非易失性存储器的EXECUTE-IN-PLACE MODE CONFIGURATION
公开(公告)号：US20120110246A1
公开(公告)日：2012-05-03
申请号：US13143078
申请日：2008-12-30
申请人： Paolo Rolandi , Sandra Lospalluti , Raffaele Bufano , Stefano Andreoli , Tommaso Zerilli
发明人： Paolo Rolandi , Sandra Lospalluti , Raffaele Bufano , Stefano Andreoli , Tommaso Zerilli
IPC分类号： G06F12/00
CPC分类号： G06F12/0246 , G06F9/30098 , G06F9/44573 , G06F2212/72 , G06F2212/7206 , G11C16/26 , G11C2216/30
摘要： Example embodiments for configuring a serial non-volatile memory device for an execute-in-place mode may comprise a non-volatile configuration register to store an execute-in-place mode value that may be read at least in part in response to power being applied to the memory device.
摘要翻译：用于配置用于就地执行模式的串行非易失性存储器件的示例性实施例可以包括非易失性配置寄存器，用于存储至少部分地响应于功率而被读取的就地执行模式值应用于存储器件。

34. 发明申请

US20090180328A1 Method for Accessing in Reading, Writing and Programming to a NAND Non-Volatile Memory Electronic Device Monolithically Integrated on Semiconductor 有权
标题翻译：用于在NAND非易失性存储器电子器件中进行读写写入和编程的方法，其集成在半导体上
公开(公告)号：US20090180328A1
公开(公告)日：2009-07-16
申请号：US12409740
申请日：2009-03-24
申请人： Luigi Pascucci , Paolo Rolandi
发明人： Luigi Pascucci , Paolo Rolandi
IPC分类号： G11C16/06
CPC分类号： G11C5/066 , G11C7/1018 , G11C7/1045 , G11C16/0483 , G11C16/08 , G11C2207/105
摘要： A method for accessing, in reading, programming, and erasing a semiconductor-integrated non-volatile memory device of the Flash EEPROM type with a NAND architecture having at least one memory matrix organized in rows or word lines and columns or bit lines, and wherein, for the memory, a plurality of additional address pins are provided. The method provides both an access protocol of the asynchronous type and a protocol of the extended type allowing to address, directly and in parallel, a memory extended portion by loading an address register associated with the additional pins in two successive clock pulses. A third multi-sequential access mode and a parallel additional bus referring to the additional address pins are also provided to allow a double addressing mode, sequential and in parallel.
摘要翻译：一种用于以具有至少一个以行或字线和列或位线组织的存储矩阵的NAND架构来访问，读取，编程和擦除闪存EEPROM类型的半导体集成非易失性存储器件的方法，其中为了存储器，提供了多个附加的地址引脚。该方法提供异步类型的访问协议和扩展类型的协议，允许通过在两个连续的时钟脉冲中加载与附加引脚相关联的地址寄存器来直接和并行地寻址存储器扩展部分。还提供了第三个多次访问模式和引用附加地址引脚的并行附加总线，以允许双寻址模式，顺序和并行。

35. 发明授权

US07447103B2 Row decoder circuit for electrically programmable and erasable non volatile memories 有权
标题翻译：行解码器电路，用于电可编程和可擦除非易失性存储器
公开(公告)号：US07447103B2
公开(公告)日：2008-11-04
申请号：US11504539
申请日：2006-08-14
申请人： Paolo Rolandi
发明人： Paolo Rolandi
IPC分类号： G11C8/00
CPC分类号： G11C8/10 , G11C16/16
摘要： The invention relates to a row decoder circuit for non volatile memory devices of the electrically programmable and erasable type, for example of the Flash EEPROM type having a NOR architecture. The proposed row decoder circuit allows to carry out the erasing step very quickly, for example with a granularity emulating at least 16kB and even overcoming by at least 2kB Flash memories of the NAND type. The memory can thus maintain high performances in terms of random access speed but shows a high erasing speed typical of memory architectures of the NAND type.
摘要翻译：本发明涉及一种用于电可编程和可擦除类型的非易失性存储器件的行解码器电路，例如具有NOR架构的闪速EEPROM类型。所提出的行解码器电路允许非常快速地执行擦除步骤，例如以至少16kB的粒度进行甚至由NAND类型的至少2kB的闪存进行克服的粒度。因此，存储器可以在随机访问速度方面保持高性能，但是显示出NAND类型的存储器架构的典型的高擦除速度。

36. 发明授权

US07397702B2 Read/verify circuit for multilevel memory cells with ramp read voltage, and read/verify method thereof 有权
标题翻译：具有斜坡读取电压的多电平存储单元的读取/验证电路及其读取/验证方法
公开(公告)号：US07397702B2
公开(公告)日：2008-07-08
申请号：US11178240
申请日：2005-07-08
申请人： Paolo Rolandi , Luigi Pascucci
发明人： Paolo Rolandi , Luigi Pascucci
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C11/5642 , G11C16/28 , G11C16/3454 , G11C16/3459 , G11C2211/5634
摘要： A read/verify circuit for multilevel memory cells includes: a read terminal selectively connectable to a plurality of array cells, having respective array threshold voltages; a plurality of reference cells, having respective reference threshold voltages; and a plurality of threshold-detection circuits, for detecting the array thresholds and the reference thresholds. In particular, the read terminal and the reference cells are each connected to a respective threshold-detection circuit. Each threshold-detection circuit is provided with a respective detector element of a resistive type, set so as to be traversed by a current response to turning-on of the respective array cell or reference cell associated thereto.
摘要翻译：用于多电平存储器单元的读/验电路包括：可选择地连接到具有相应阵列阈值电压的多个阵列单元的读终端; 多个参考单元，具有各自的参考阈值电压; 以及用于检测阵列阈值和参考阈值的多个阈值检测电路。特别地，读取终端和参考单元各自连接到相应的阈值检测电路。每个阈值检测电路设置有电阻型的相应检测器元件，其被设置为通过与其相关联的相应阵列单元或参考单元的导通的电流响应来遍历。

37. 发明申请

US20070279996A1 METHOD AND SYSTEM FOR REFRESHING A MEMORY DEVICE DURING READING THEREOF 有权
标题翻译：在读取存储器件时刷新的方法和系统
公开(公告)号：US20070279996A1
公开(公告)日：2007-12-06
申请号：US11695552
申请日：2007-04-02
申请人： Paolo Rolandi , Luigi Pascucci
发明人： Paolo Rolandi , Luigi Pascucci
IPC分类号： G11C16/06
CPC分类号： G11C16/3431 , G11C11/5628 , G11C16/3418
摘要： A refresh circuit for refreshing a memory device is proposed. The refresh circuit includes: reading means for reading a set of memory cells, the reading means including means for applying a biasing voltage having a substantially monotone time pattern to the memory cells and to a set of reference cells each one having a reference threshold voltage, means for detecting the reaching of a comparison current by a cell current of each memory cell and by a reference current of each reference cell, and means for determining a condition of each memory cell according to a temporal relation of the reaching of the comparison current by the corresponding cell current and the reference currents, and writing means for applying a writing voltage to at least one selected of the memory cells; the refresh circuit further includes control means for enabling the writing means during at least part of the application of the biasing voltage after the determination of the condition of each selected memory cell.
摘要翻译：提出了刷新存储器件的刷新电路。刷新电路包括：用于读取一组存储单元的读取装置，所述读取装置包括用于向存储单元施加具有基本上单调的时间模式的偏置电压的装置和具有参考阈值电压的一组参考单元，用于通过每个存储单元的单元电流和每个参考单元的参考电流来检测比较电流达到的装置，以及用于根据达到比较电流的时间关系确定每个存储单元的状态的装置对应的单元电流和参考电流;以及写入装置，用于向至少一个选择的存储单元施加写入电压; 刷新电路还包括控制装置，用于在确定每个所选择的存储单元的状态之后，在施加偏置电压的至少一部分期间使写入装置能够使能。

38. 发明申请

US20070041263A1 Row decoder circuit for electrically programmable and erasable non volatile memories 有权
标题翻译：行解码器电路，用于电可编程和可擦除非易失性存储器
公开(公告)号：US20070041263A1
公开(公告)日：2007-02-22
申请号：US11504539
申请日：2006-08-14
申请人： Paolo Rolandi
发明人： Paolo Rolandi
IPC分类号： G11C8/00
CPC分类号： G11C8/10 , G11C16/16
摘要： The invention relates to a row decoder circuit for non volatile memory devices of the electrically programmable and erasable type, for example of the Flash EEPROM type having a NOR architecture. The proposed row decoder circuit allows to carry out the erasing step very quickly, for example with a granularity emulating at least 16 kB and even overcoming by at least 2 kB Flash memories of the NAND type. The memory can thus maintain high performances in terms of random access speed but shows a high erasing speed typical of memory architectures of the NAND type.
摘要翻译：本发明涉及一种用于电可编程和可擦除类型的非易失性存储器件的行解码器电路，例如具有NOR架构的闪速EEPROM类型。所提出的行解码器电路允许非常快速地执行擦除步骤，例如，以至少16kB的粒度并且甚至由NAND类型的至少2kB的闪存来克服的粒度。因此，存储器可以在随机访问速度方面保持高性能，但是显示出NAND类型的存储器架构的典型的高擦除速度。

39. 发明申请

US20060268650A1 Row decoder circuit and related system and method 有权
公开(公告)号：US20060268650A1
公开(公告)日：2006-11-30
申请号：US11434564
申请日：2006-05-15
申请人： Luigi Pascucci , Paolo Rolandi
发明人： Luigi Pascucci , Paolo Rolandi
IPC分类号： G11C8/00
CPC分类号： G11C8/10 , G11C16/08
摘要： A row decoder circuit is described of the type comprising at least one input stage connected to a first supply voltage reference and to an output stage connected to a second supply voltage reference, the output stage having at least one output terminal connected to a word line of a memory matrix. The row decoder circuit further comprises a biasing device, connected to a third supply voltage reference and comprising at least one generator of a negative voltage connected to a divider, in turn connected to a first biasing terminal of the biasing device. In particular, the first biasing terminal is connected to at least one input stage in correspondence with bulk terminals of MOS transistors comprised in the input stage and it is suitable for supplying it with a first negative voltage.

40. 发明申请

US20060239076A1 NON-VOLATILE MEMORY ELECTRONIC DEVICE WITH NAND STRUCTURE BEING MONOLITHICALLY INTEGRATED ON SEMICONDUCTOR 有权
标题翻译：具有NAND结构的非易失性存储器件电子器件单一集成在半导体
公开(公告)号：US20060239076A1
公开(公告)日：2006-10-26
申请号：US11279385
申请日：2006-04-11
申请人： Luigi Pascucci , Paolo Rolandi
发明人： Luigi Pascucci , Paolo Rolandi
IPC分类号： G11C16/04
CPC分类号： G11C16/08 , G11C16/0408 , G11C16/0483 , G11C16/12 , G11C16/24 , Y10T29/49002
摘要： A non-volatile memory electronic device is integrated on a semiconductor and is of the Flash EEPROM type with a NAND architecture including at least one memory matrix divided into physical sectors, intended as smallest erasable units, and organized in rows or word lines and columns or bit lines of memory cells. At least one row or word line of a given physical sector is electrically connected to at least one row or word line of an adjacent physical sector to form a single logic sector being erasable, with the source terminals of the corresponding cells of the pair of connected rows referring to a same selection line of a source line.
摘要翻译：非易失性存储器电子器件集成在半导体上，并且具有闪存EEPROM类型，其具有NAND架构，其包括分成物理扇区的至少一个存储器矩阵，其被设计为最小的可擦除单元，并且被组织成行或字线和列或位线的存储单元。给定物理扇区的至少一行或字线电连接到相邻物理扇区的至少一行或字线，以形成可擦除的单个逻辑扇区，其中一对连接的相应小区的源终端行指向源行的相同选择行。

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