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31. 发明申请

US20120314480A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20120314480A1
公开(公告)日：2012-12-13
申请号：US13490713
申请日：2012-06-07
申请人： Junya ONISHI , Nobuyoshi Awaya , Mitsuru Nakura , Kazuya Ishihara
发明人： Junya ONISHI , Nobuyoshi Awaya , Mitsuru Nakura , Kazuya Ishihara
IPC分类号： G11C11/00
CPC分类号： G06F11/1048 , G11C13/004 , G11C13/0061 , G11C2029/0411
摘要： In a semiconductor memory device using a variable resistive element made of a metal oxide for storing information, a voltage amplitude of a writing voltage pulse for changing the variable resistive element to a high resistance state is set within a voltage range in which the resistance value of the high resistance state after the change increases with time. The voltage amplitude is set within the voltage range in which the resistance value of the high resistance state after the change increases toward a predetermined peak with increase in voltage amplitude. When a data error is detected by the ECC circuit, it is estimated that the data that should be in the low resistance state changes to the high resistance state, and the variable resistive elements of all memory cells from which the error is detected are written to the low resistance state to correct the error bit.
摘要翻译：在使用由金属氧化物制成的可变电阻元件用于存储信息的半导体存储器件中，将可变电阻元件改变为高电阻状态的写入电压脉冲的电压幅度设定在电阻值变化后的高电阻状态随时间而增加。电压幅度设定在电压范围内，随着电压振幅的增加，变化后的高电阻状态的电阻值向预定的峰值增加。当ECC电路检测到数据错误时，估计应该处于低电阻状态的数据变为高电阻状态，并且将检测到错误的所有存储单元的可变电阻元件写入低电阻状态来纠正错误位。

32. 发明申请

US20120025163A1 NON-VOLATILE SEMICONDUCTOR DEVICE 有权
标题翻译：非挥发性半导体器件
公开(公告)号：US20120025163A1
公开(公告)日：2012-02-02
申请号：US13182696
申请日：2011-07-14
申请人： Junya ONISHI , Shinobu Yamazaki , Kazuya Ishihara , Yushi Inoue , Yukio Tamai , Nobuyoshi Awaya
发明人： Junya ONISHI , Shinobu Yamazaki , Kazuya Ishihara , Yushi Inoue , Yukio Tamai , Nobuyoshi Awaya
IPC分类号： H01L45/00
CPC分类号： H01L45/04 , H01L27/2436 , H01L45/1233 , H01L45/146
摘要： A variable resistance element that can stably perform a switching operation with a property variation being reduced by suppressing a sharp current that accompanies completion of forming process, and a non-volatile semiconductor memory device including the variable resistance element are realized. The non-volatile semiconductor memory device uses the variable resistance element for storing information in which a resistance changing layer is interposed between a first electrode and a second electrode, and a buffer layer is inserted between the first electrode and the resistance changing layer where a switching interface is formed. The buffer layer and the resistance changing layer include n-type metal oxides, and materials of the buffer layer and the resistance changing layer are selected such that energy at a bottom of a conduction band of the n-type metal oxide configuring the buffer layer is lower than that of the n-type metal oxide configuring the resistance changing layer.
摘要翻译：通过抑制伴随着成形处理的完成的尖锐电流，可以稳定地进行具有特性变化的开关动作的可变电阻元件，以及包括该可变电阻元件的非易失性半导体存储器件。非易失性半导体存储器件使用可变电阻元件来存储在第一电极和第二电极之间插入电阻变化层的信息，并且缓冲层插入在第一电极和电阻变化层之间，其中开关界面形成。缓冲层和电阻变化层包括n型金属氧化物，并且选择缓冲层和电阻变化层的材料，使得构成缓冲层的n型金属氧化物的导带的底部的能量为低于构成电阻变化层的n型金属氧化物。

33. 发明申请

US20110228586A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20110228586A1
公开(公告)日：2011-09-22
申请号：US13044892
申请日：2011-03-10
申请人： Suguru KAWABATA , Shinobu Yamazaki , Yoshiji Ohta , Kazuya Ishihara , Nobuyoshi Awaya , Akio Kitagawa , Kazuya Nakayama
发明人： Suguru KAWABATA , Shinobu Yamazaki , Yoshiji Ohta , Kazuya Ishihara , Nobuyoshi Awaya , Akio Kitagawa , Kazuya Nakayama
IPC分类号： G11C11/34
CPC分类号： G11C13/004 , G11C2013/0045 , G11C2213/71 , G11C2213/72 , G11C2213/77
摘要： A nonvolatile semiconductor memory device includes a bit voltage adjusting circuit which, for each bit line, fixes potentials of a selected bit line and a non-selected bit line to a predetermined potential to perform a memory operation and a data voltage adjusting circuit which, for each data line, fixes potentials of a selected data line and a non-selected data line to a predetermined potential to perform a memory operation. Each of the voltage adjusting circuits includes an operational amplifier and a transistor, a voltage required for a memory operation is input to the non-inverted input terminal of the operational amplifier, and the inverted input terminal of the operational amplifier is connected to the bit line or the data line, so that the potential of the bit line or the data line is fixed to a potential of the non-inverted input terminal of the operational amplifier.
摘要翻译：非易失性半导体存储器件包括：位电压调整电路，对于每个位线，将选定位线和非选定位线的电位固定到预定电位以执行存储器操作，以及数据电压调整电路，每个数据线将所选数据线和未选择的数据线的电位固定到预定电位以执行存储器操作。每个电压调节电路包括运算放大器和晶体管，将存储器操作所需的电压输入到运算放大器的非反相输入端，运算放大器的反相输入端连接到位线或数据线，使得位线或数据线的电位固定为运算放大器的非反相输入端的电位。

34. 发明授权

US08023312B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US08023312B2
公开(公告)日：2011-09-20
申请号：US12515286
申请日：2007-11-05
申请人： Shinobu Yamazaki , Yasunari Hosoi , Nobuyoshi Awaya , Shinichi Sato , Kenichi Tanaka
发明人： Shinobu Yamazaki , Yasunari Hosoi , Nobuyoshi Awaya , Shinichi Sato , Kenichi Tanaka
IPC分类号： G11C11/00
CPC分类号： H01L27/101 , G11C13/0007 , G11C13/003 , G11C2213/15 , G11C2213/32 , G11C2213/34 , G11C2213/71 , G11C2213/72 , G11C2213/76 , G11C2213/77 , G11C2213/79 , H01L27/2409 , H01L27/2463 , H01L27/2481 , H01L45/04 , H01L45/1233 , H01L45/145 , H01L45/146 , H01L45/1633
摘要： A nonvolatile semiconductor memory device include: a two terminal structured variable resistive element, wherein resistive characteristics defined by current-voltage characteristics at both ends transit between low and high resistance states stably by applying a voltage satisfying predetermined conditions to the both ends. A transition from the low resistance state to the high resistance state occurs by applying a voltage of a first polarity whose absolute value is at or higher than first threshold voltage, and the reverse transition occurs by applying a voltage of a second polarity whose absolute value is at or higher than a second threshold voltage. A load circuit is connected to the variable resistive element in series having an adjustable load resistance. A voltage generation circuit applies a voltage to both ends of a serial circuit. The variable resistive element can transit between the states by adjusting a resistance of the load circuit.
摘要翻译：非易失性半导体存储器件包括：二端结构可变电阻元件，其中由两端的电流 - 电压特性限定的电阻特性通过向两端施加满足预定条件的电压来稳定地传递低电阻状态和高电阻状态。通过施加绝对值等于或高于第一阈值电压的第一极性的电压而发生从低电阻状态向高电阻状态的转变，并且通过施加绝对值为绝对值的第二极性的电压，等于或高于第二阈值电压。负载电路与可变负载电阻串联连接到可变电阻元件。电压产生电路向串联电路的两端施加电压。可变电阻元件可以通过调整负载电路的电阻在状态之间转换。

35. 发明授权

US07952909B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US07952909B2
公开(公告)日：2011-05-31
申请号：US12517025
申请日：2007-11-05
申请人： Kohji Inoue , Yasunari Hosoi , Shigeo Ohnishi , Nobuyoshi Awaya
发明人： Kohji Inoue , Yasunari Hosoi , Shigeo Ohnishi , Nobuyoshi Awaya
IPC分类号： G11C11/00
CPC分类号： G11C13/0007 , G11C13/0026 , G11C13/0038 , G11C13/0069 , G11C2013/009 , G11C2213/15 , G11C2213/32 , G11C2213/34 , G11C2213/72 , G11C2213/77 , G11C2213/79 , H01L27/101 , H01L27/1021 , H01L27/2409 , H01L27/2436 , H01L45/04 , H01L45/1233 , H01L45/145 , H01L45/146 , H01L45/1633
摘要： Provided is a nonvolatile semiconductor device capable of performing writing operations of different resistance changes for memory cells having variable resistive elements whose resistive characteristics are changed by voltage applications, individually and simultaneously. The device includes: a load resistive characteristic variable circuit for each bit line connected commonly with the memory cells on the same column for selecting one of two load resistive characteristics according to a first writing operation where the resistive characteristics of the variable resistive element to be written transit from a low resistance state to a high resistance state or a second writing operation where they transit reversely; and a writing voltage pulse application circuit for applying a first voltage pulse in a first writing operation and a second voltage pulse in a second writing operation to the memory cells to be written through the load resistive characteristic variable circuits and the bit limes.
摘要翻译：提供了一种非易失性半导体器件，其能够对具有可变电阻元件的存储单元进行不同的电阻变化的写入操作，该电阻元件的电阻特性单独并同时由电压应用而改变。该装置包括：用于与同一列上的存储器单元共同连接的每个位线的负载电阻特性可变电路，用于根据要写入的可变电阻元件的电阻特性的第一写入操作来选择两个负载电阻特性中的一个从低电阻状态转移到高电阻状态或其反向转发的第二写入操作; 以及写入电压脉冲施加电路，用于将第一写入操作中的第一电压脉冲和第二写入操作中的第二电压脉冲施加到要通过负载电阻特性可变电路和位灰分写入的存储单元。

36. 发明申请

US20100080038A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20100080038A1
公开(公告)日：2010-04-01
申请号：US12563349
申请日：2009-09-21
申请人： Nobuyoshi Awaya , Takashi Nakano
发明人： Nobuyoshi Awaya , Takashi Nakano
IPC分类号： G11C11/00 , G11C7/00 , H01L47/00
CPC分类号： G11C13/0007 , G11C11/005 , G11C13/0004 , G11C13/0011 , G11C13/0033 , G11C14/00 , G11C14/0045 , G11C2211/4016 , G11C2213/31 , H01L27/2436 , H01L27/2454 , H01L27/2472 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/146
摘要： An inexpensive nonvolatile memory having high performance which makes random write and readout possible an unlimited number of times is provided. A unit memory cell is formed of a MISFET having a channel body that is electrically isolated from a semiconductor substrate and a resistance change element having a two-terminal structure with one end electrically connected to a drain of the MISFET. The MISFET functions as a volatile memory element, and the resistance change element functions as a nonvolatile memory element, so that information stored in the MISFET is copied to the resistance change element before the power is turned OFF and information stored in the resistance change element is transferred to the MISFET when the power is turned ON, and thus, the MISFET is used as a volatile memory which makes random write and readout possible.
摘要翻译：提供了具有高性能的便宜的非易失性存储器，其使得随机写入和读出可能无限次。单元存储单元由具有与半导体基板电隔离的沟道体的MISFET和具有与MISFET的漏极电连接的一端的两端结构的电阻变化元件形成。 MISFET用作易失性存储元件，并且电阻变化元件用作非易失性存储元件，使得存储在MISFET中的信息在电源断开之前被复制到电阻变化元件，并且存储在电阻变化元件中的信息是当电源接通时转移到MISFET，因此，MISFET被用作使随机写入和读出成为可能的易失性存储器。

37. 发明授权

US07112527B2 Manufacturing method for short distance wiring layers and long distance wiring layers in a semiconductor device 有权
标题翻译：在半导体器件中的短距离布线层和长距离布线层的制造方法
公开(公告)号：US07112527B2
公开(公告)日：2006-09-26
申请号：US10839257
申请日：2004-05-06
申请人： Nobuyoshi Awaya
发明人： Nobuyoshi Awaya
IPC分类号： H01L21/4763
CPC分类号： H01L23/5222 , H01L21/76838 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A semiconductor device having regions for forming a plurality of functional blocks and a region for forming wiring layers for connecting the functional blocks, wherein each of the regions for forming the functional blocks includes a multilayer wiring, and the region for forming the wiring layers for connecting adjacent functional blocks includes a coaxial line comprised of a signal line and a ground line surrounding the signal line via an insulating film.
摘要翻译：一种具有用于形成多个功能块的区域的半导体器件和用于形成用于连接功能块的布线层的区域，其中用于形成功能块的各个区域包括多层布线，以及用于形成用于连接的布线层的区域相邻的功能块包括由信号线和经由绝缘膜围绕信号线的接地线组成的同轴线。

38. 发明授权

US07045840B2 Nonvolatile semiconductor memory device comprising a variable resistive element containing a perovskite-type crystal structure 有权
标题翻译：包括含有钙钛矿型晶体结构的可变电阻元件的非易失性半导体存储器件
公开(公告)号：US07045840B2
公开(公告)日：2006-05-16
申请号：US11001744
申请日：2004-12-01
申请人： Yukio Tamai , Nobuyoshi Awaya , Shinji Kobayashi , Hidechika Kawazoe , Toshimasa Suzuki , Hidetoshi Masuda , Naoto Hagiwara , Yuji Matsushita , Yuji Nishi
发明人： Yukio Tamai , Nobuyoshi Awaya , Shinji Kobayashi , Hidechika Kawazoe , Toshimasa Suzuki , Hidetoshi Masuda , Naoto Hagiwara , Yuji Matsushita , Yuji Nishi
IPC分类号： H01L29/76
CPC分类号： G11C13/0007 , G11C2213/31 , G11C2213/52 , G11C2213/79 , H01L27/2436 , H01L45/04 , H01L45/1233 , H01L45/1253 , H01L45/147 , H01L45/1625
摘要： In a nonvolatile semiconductor memory device including a variable resistive element formed by sequentially stacking a lower electrode, a variable resistor with a perovskite-type crystal structure, and an upper electrode, at least one of the lower electrode and the upper electrode is a particulate electrode configured to include a particulate conductor aggregate so that the contact area with the variable resistor at an interface is effectively reduced to realize high initial resistance of the variable resistive element. Further, a film of the variable resistor is preferably formed so as to be in a highly crystalline state.
摘要翻译：在包括通过顺序堆叠下电极，具有钙钛矿型晶体结构的可变电阻器和上电极形成的可变电阻元件的非易失性半导体存储器件中，下电极和上电极中的至少一个是颗粒电极被配置为包括颗粒状导体集合体，使得在界面处与可变电阻器的接触面积被有效地减小以实现可变电阻元件的高初始电阻。此外，可变电阻器的膜优选形成为高度结晶的状态。

39. 发明授权

US07027322B2 EPIR device and semiconductor devices utilizing the same 失效
标题翻译： EPIR器件和利用其的半导体器件
公开(公告)号：US07027322B2
公开(公告)日：2006-04-11
申请号：US10790238
申请日：2004-03-02
申请人： Toshimasa Suzuki , Yuji Nishi , Masayuki Fujimoto , Nobuyoshi Awaya , Kohji Inoue , Keizo Sakiyama
发明人： Toshimasa Suzuki , Yuji Nishi , Masayuki Fujimoto , Nobuyoshi Awaya , Kohji Inoue , Keizo Sakiyama
IPC分类号： G11C11/00
CPC分类号： G11C13/0007 , B82Y10/00 , G11C2213/31 , H01L45/04 , H01L45/1233 , H01L45/1253 , H01L45/147 , H01L45/1625
摘要： There is provided an EPIR device which is excellent in mass productivity and high in practical utility.The EPIR device includes a lower electrode layer, a CMR thin film layer and an upper electrode layer which are laminated in this order on any of various substrates. A Pt polycrystal thin film 10 forming the lower electrode layer includes columnar Pt crystal grains 10A, 10B, 10C, . . . and over 90% of these crystal grains is oriented to a (1 1 1) face. Columnar PCMO crystal grain groups 20A, 20B, 20C, . . . are respectively locally grown epitaxially on the respective outermost surfaces of the Pt crystal grains 10A, 10B, 10C, . . . . Then, the crystal faces of the crystal grains included in the PCMO crystal grain groups 20A, 20B, 20C, . . . and vertical in the substrate surface normal direction are any one of (1 0 0)p, (1 1 0)p and (1 1 1)p planes.
摘要翻译：提供了具有优异的批量生产率和高实用性的EPIR装置。 EPIR器件包括下列电极层，CMR薄膜层和上电极层，它们以任何各种衬底依次层叠。形成下电极层的Pt多晶薄膜10包括柱状Pt晶粒10 A，10 B，10 C。。。并且超过90％的这些晶粒取向为（111）面。柱状PCMO晶粒组20 A，20 B，20 C，。。分别在Pt晶粒10 A，10 B，10 C的各自的最外表面上外延地局部生长。。。。然后，包含在PCMO晶粒组20A，20B，20C中的晶粒的晶面。。。并且在衬底表面法线方向上的垂直方向是（110）p1，（111）p1和（111）中的任何一个p < / SUB>飞机。

40. 发明授权

US06891261B2 Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US06891261B2
公开(公告)日：2005-05-10
申请号：US09986051
申请日：2001-11-07
申请人： Nobuyoshi Awaya
发明人： Nobuyoshi Awaya
IPC分类号： H01L23/52 , H01L21/3205 , H01L21/768 , H01L21/82 , H01L23/522 , H01L23/48 , H01L29/00 , H01L29/40
CPC分类号： H01L23/5222 , H01L21/76838 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A semiconductor device having regions for forming a plurality of functional blocks and a region for forming wiring layers for connecting the functional blocks, wherein each of the regions for forming the functional blocks includes a multilayer wiring, and the region for forming the wiring layers for connecting adjacent functional blocks includes a coaxial line comprised of a signal line and a ground line surrounding the signal line via an insulating film.
摘要翻译：一种具有用于形成多个功能块的区域的半导体器件和用于形成用于连接功能块的布线层的区域，其中用于形成功能块的各个区域包括多层布线，以及用于形成用于连接的布线层的区域相邻的功能块包括由信号线和经由绝缘膜围绕信号线的接地线组成的同轴线。

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