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31. 发明授权

US5455790A High density EEPROM cell array which can selectively erase each byte of data in each row of the array 失效
标题翻译：高密度EEPROM单元阵列，可以选择性地擦除阵列每行数据的每个字节
公开(公告)号：US5455790A
公开(公告)日：1995-10-03
申请号：US243466
申请日：1994-05-16
申请人： Michael J. Hart , Albert M. Bergemont
发明人： Michael J. Hart , Albert M. Bergemont
IPC分类号： G11C16/10 , G11C16/14 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , H01L29/68
CPC分类号： G11C16/10 , G11C16/14 , H01L27/115 , H01L27/11521 , H01L29/7883 , Y10S438/972
摘要： Each byte of data in a high-density, electrically-erasable, programmable read-only-memory (EEPROM) cell array is selectively erased by forming a plurality of memory cells in each of a plurality of P-wells where the memory cells in each P-well are formed one byte wide by n rows in length. By forming the memory cells in each P-well to be one byte wide by n rows in length, each byte of data can be selectively erased by identifying the corresponding P-well and the row within the P-well.
摘要翻译：通过在多个P阱中的每个P阱中形成多个存储单元来选择性地擦除高密度，电可擦除可编程只读存储器（EEPROM）单元阵列中的每个字节的数据，其中每个P阱中的存储器单元 P-well形成一个字节宽，长度为n行。通过将每个P阱中的存储单元形成为一个字节宽，长度为n行，可以通过识别P阱中的相应P阱和行来选择性地擦除每个字节的数据。

32. 发明授权

US08351248B1 CMOS SRAM memory cell with improved N/P current ratio 有权
标题翻译：具有改善N / P电流比的CMOS SRAM存储单元
公开(公告)号：US08351248B1
公开(公告)日：2013-01-08
申请号：US12624291
申请日：2009-11-23
申请人： Michael J. Hart
发明人： Michael J. Hart
IPC分类号： G11C11/00
CPC分类号： G11C11/412
摘要： A memory cell in an integrated circuit has a first PMOS transistor formed in N-type semiconductor material and a first NMOS transistor formed in P-type semiconductor material. A well bias line coupled to the N-type semiconductor material or to the P-type semiconductor material provides a well bias voltage not equal to the PMOS bias voltage or to the NMOS bias voltage to reverse body-bias the PMOS transistor or to forward body-bias the NMOS transistor.
摘要翻译：集成电路中的存储单元具有形成在N型半导体材料中的第一PMOS晶体管和形成在P型半导体材料中的第一NMOS晶体管。耦合到N型半导体材料或P型半导体材料的阱偏压线提供不等于PMOS偏置电压或NMOS偏置电压的阱偏置电压，以反向PMOS晶体管或前向体的体偏置是NMOS晶体管。

33. 发明申请

US20120002392A1 ELECTRO-STATIC DISCHARGE PROTECTION FOR DIE OF A MULTI-CHIP MODULE 有权
标题翻译：多芯片模块电子放电放电保护
公开(公告)号：US20120002392A1
公开(公告)日：2012-01-05
申请号：US12828007
申请日：2010-06-30
申请人： James Karp , Michael J. Hart , Mohammed Fakhruddin , Steven T. Reilly
发明人： James Karp , Michael J. Hart , Mohammed Fakhruddin , Steven T. Reilly
IPC分类号： H05K7/00 , H01R43/00
CPC分类号： H01L23/60 , H01L25/0655 , H01L25/0657 , H01L27/0255 , H01L2224/16225 , H01L2224/73253 , H01L2225/06572 , H01L2924/14 , H01L2924/15192 , H01L2924/15311 , H01L2924/15787 , H01L2924/19107 , Y10T29/49117
摘要： Electro-static discharge (“ESD”) protection for a die of a multi-chip module is described. A contact has an externally exposed surface after formation of the die and prior to assembly of the multi-chip module. The contact is for a die-to-die interconnect of the multi-chip module. The contact is for an internal node of the multi-chip module after the assembly of the multi-chip module. A driver circuit is coupled to the contact and has a first input impedance. A discharge circuit is coupled to the contact for electrostatic discharge protection of the driver circuit and has a first forward bias impedance associated with a first discharge path. The first forward bias impedance is a fraction of the first input impedance.
摘要翻译：描述了用于多芯片模块的管芯的静电放电（“ESD”）保护。在形成模具之后并且在组装多芯片模块之前，触点具有外部暴露的表面。该接触是用于多芯片模块的管芯到管芯互连。联系人是组装多芯片模块后的多芯片模块的内部节点。驱动器电路耦合到触点并且具有第一输入阻抗。放电电路耦合到触点用于驱动电路的静电放电保护，并且具有与第一放电路径相关联的第一正向偏置阻抗。第一个正向偏置阻抗是第一个输入阻抗的一小部分。

34. 发明授权

US07793238B1 Method and apparatus for improving a circuit layout using a hierarchical layout description 有权
标题翻译：使用层次布局描述改进电路布局的方法和装置
公开(公告)号：US07793238B1
公开(公告)日：2010-09-07
申请号：US12053874
申请日：2008-03-24
申请人： Peter Rabkin , Zhiyuan Wu , Min-Hsing Peter Chen , Jane W. Sowards , Michael J. Hart , Min-Fang Ho
发明人： Peter Rabkin , Zhiyuan Wu , Min-Hsing Peter Chen , Jane W. Sowards , Michael J. Hart , Min-Fang Ho
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F2217/12 , Y02P90/265
摘要： Various approaches for improving an integrated circuit layout. In one approach, a tree-type hierarchical layout representation of the circuit design is traversed. At each block visited during the traversing, a process determines whether there exists an improvement opportunity for each cell associated with the block. In response to determining that an improvement opportunity exists for a cell of a first block of the plurality of blocks, the process determines whether a modification to the cell satisfies one or more rules for every other block of the block type of the first block in the hierarchical representation. If the rules are satisfied, the modification is stored. Otherwise, the modification is discarded.
摘要翻译：用于改善集成电路布局的各种方法。在一种方法中，遍历了电路设计的树型分层布局表示。在遍历期间访问的每个块处，确定是否存在与该块相关联的每个单元的改进机会。响应于确定对于所述多个块的第一块的小区存在改进机会，所述过程确定对所述小区的修改是否满足所述小区的所述第一块的块类型的每个其他块的一个或多个规则分层表示。如果规则满足，则修改被存储。否则，修改被丢弃。

35. 发明授权

US08982581B2 Electro-static discharge protection for die of a multi-chip module 有权
标题翻译：多芯片模块芯片的静电放电保护
公开(公告)号：US08982581B2
公开(公告)日：2015-03-17
申请号：US12828007
申请日：2010-06-30
申请人： James Karp , Michael J. Hart , Mohammed Fakhruddin , Steven T. Reilly
发明人： James Karp , Michael J. Hart , Mohammed Fakhruddin , Steven T. Reilly
IPC分类号： H05K7/00 , H01R43/00 , H01L23/60 , H01L25/065 , H01L27/02
CPC分类号： H01L23/60 , H01L25/0655 , H01L25/0657 , H01L27/0255 , H01L2224/16225 , H01L2224/73253 , H01L2225/06572 , H01L2924/14 , H01L2924/15192 , H01L2924/15311 , H01L2924/15787 , H01L2924/19107 , Y10T29/49117
摘要： Electro-static discharge (“ESD”) protection for a die of a multi-chip module is described. A contact has an externally exposed surface after formation of the die and prior to assembly of the multi-chip module. The contact is for a die-to-die interconnect of the multi-chip module. The contact is for an internal node of the multi-chip module after the assembly of the multi-chip module. A driver circuit is coupled to the contact and has a first input impedance. A discharge circuit is coupled to the contact for electrostatic discharge protection of the driver circuit and has a first forward bias impedance associated with a first discharge path. The first forward bias impedance is a fraction of the first input impedance.
摘要翻译：描述了用于多芯片模块的管芯的静电放电（“ESD”）保护。在形成模具之后并且在组装多芯片模块之前，触点具有外部暴露的表面。该接触是用于多芯片模块的管芯到管芯互连。联系人是组装多芯片模块后的多芯片模块的内部节点。驱动器电路耦合到触点并且具有第一输入阻抗。放电电路耦合到触点用于驱动电路的静电放电保护，并且具有与第一放电路径相关联的第一正向偏置阻抗。第一个正向偏置阻抗是第一个输入阻抗的一小部分。

36. 发明授权

US08692381B1 Integrated circuits with a resistance to single event upset occurrence and methods for providing the same 有权
标题翻译：具有抵抗单事件不稳定发生的集成电路和提供相同的方法
公开(公告)号：US08692381B1
公开(公告)日：2014-04-08
申请号：US12985918
申请日：2011-01-06
申请人： Michael J. Hart
发明人： Michael J. Hart
IPC分类号： H01L27/108
CPC分类号： H01L27/1104 , G11C11/4125 , H01L23/481 , H01L27/0207 , H01L28/90 , H01L29/66181 , H01L29/945 , H01L2924/0002 , H01L2924/00
摘要： Integrated circuits and methods for reducing the Single Event Upset (SEU) susceptibility of a memory cell are disclosed. By using one or more Through Silicon Vias (TSVs) as capacitor(s) coupled to the Q and/or Qbar nodes of the memory cell, the critical charge (Qcrit) of the circuit is increased. In so doing, the memory cell has greater resistance to an SEU occurrence and reduced sensitivity to neutron and alpha or other charged particle events. The capacitor(s) can be coupled between the Q or Qbar node(s) and a silicon substrate, or between the Q and Qbar nodes, for example.
摘要翻译：公开了用于减小存储器单元的单事件触发（SEU）敏感性的集成电路和方法。通过使用一个或多个通硅通孔（TSV）作为耦合到存储器单元的Q和/或Qbar节点的电容器，电路的临界电荷（Qcrit）增加。在这样做时，存储单元对SEU发生具有更大的抵抗力，并降低对中子和α或其他带电粒子事件的敏感性。例如，电容器可以耦合在Q或Qbar节点与硅衬底之间，或Q和Qbar节点之间。

37. 发明授权

US08519741B1 Operating a programmable integrated circuit with functionally equivalent configuration bitstreams 有权
标题翻译：操作具有功能等效配置比特流的可编程集成电路
公开(公告)号：US08519741B1
公开(公告)日：2013-08-27
申请号：US13543508
申请日：2012-07-06
申请人： James Karp , Michael J. Hart
发明人： James Karp , Michael J. Hart
IPC分类号： H03K19/173
CPC分类号： H03K19/1776 , G06F17/5054 , H03K19/17736
摘要： Approaches for operating a programmable integrated circuit (IC) are disclosed. One configuration bitstream of two or more configuration bitstreams is selected. Each configuration bitstream implements a functionally equivalent circuit on the programmable IC and programs a respective subset of pass gates of the programmable IC. Each subset of pass gates programmed by the configuration bitstreams is disjoint from each other subset of pass gates. The programmable IC, which is defect-free, is configured with the selected configuration bitstream. The defect-free programmable IC is then operated for a period of time. The selecting, configuring and operating are repeated, and for successive selecting operations, different ones of the configuration bitstreams are selected.
摘要翻译：公开了用于操作可编程集成电路（IC）的方法。选择两个或多个配置比特流的一个配置比特流。每个配置比特流在可编程IC上实现功能上等效的电路，并对可编程IC的相应子集的通道进行编程。由配置比特流编程的每个通道的子集与传递门的每个其他子集不相交。无缺陷的可编程IC配置有所选配置比特流。然后，无缺陷的可编程IC运行一段时间。重复选择，配置和操作，并且对于连续选择操作，选择不同的配置比特流。

38. 发明授权

US08299564B1 Diffusion regions having different depths 有权
标题翻译：具有不同深度的扩散区域
公开(公告)号：US08299564B1
公开(公告)日：2012-10-30
申请号：US12559457
申请日：2009-09-14
申请人： Yun Wu , Bei Zhu , Zhiyuan Wu , Michael J. Hart
发明人： Yun Wu , Bei Zhu , Zhiyuan Wu , Michael J. Hart
IPC分类号： H01L21/336 , H01L21/8234
CPC分类号： H01L21/823807 , H01L21/823814
摘要： Formation of transistors, such as, e.g., PMOS transistors, with diffusion regions having different depths for equalization of performance among transistors of an integrated circuit is described. Shallow-trench isolation structures are formed in a substrate formed at least in part of silicon for providing the transistors with at least substantially equivalent channel widths and lengths. A series of masks and etches is performed to form first recesses and second recesses defined in the silicon having different depths and respectively associated with first and second transistors. The second recesses are deeper than the first recesses. A silicon germanium film is formed in the first recesses and the second recesses. The silicon germanium film in the second recesses is thicker than the silicon germanium film in the first recesses, in order to increase performance of the second transistor so it is closer to the performance of the first transistor.
摘要翻译：描述了具有扩散区域的诸如PMOS晶体管的晶体管的形成，其具有用于集成电路的晶体管之间的性能均衡的不同深度。浅沟槽隔离结构形成在至少部分硅中形成的衬底中，用于为晶体管提供至少基本相当的沟道宽度和长度。执行一系列掩模和蚀刻以形成在具有不同深度并且分别与第一和第二晶体管相关联的硅中限定的第一凹部和第二凹部。第二凹部比第一凹部更深。在第一凹部和第二凹部中形成硅锗膜。第二凹部中的硅锗膜比第一凹部中的硅锗膜厚，以便增加第二晶体管的性能，使得其更接近于第一晶体管的性能。

39. 发明授权

US09379109B1 Integrated circuit having improved radiation immunity 有权
标题翻译：具有改善的辐射抗扰性的集成电路
公开(公告)号：US09379109B1
公开(公告)日：2016-06-28
申请号：US13439721
申请日：2012-04-04
申请人： James Karp , Michael J. Hart
发明人： James Karp , Michael J. Hart
IPC分类号： H01L27/092
CPC分类号： H01L27/092 , G11C8/16 , G11C11/4125 , H01L21/823892 , H01L27/1104
摘要： An integrated circuit device having improved radiation immunity is described. The integrated circuit device comprises an n-type wafer having a first surface and a second surface; a p-type epitaxial layer formed on the first surface of the n-type wafer, the p-type epitaxial wafer having first elements storing charge; and an n-well formed in the p-type epitaxial layer, the n-well having second elements storing charge; wherein the n-type wafer is positively biased to attract excess minority carriers in the p-type epitaxial layer. A method of improving radiation immunity in an integrated circuit is also described.
摘要翻译：描述了具有改善的辐射抗扰性的集成电路器件。集成电路装置包括具有第一表面和第二表面的n型晶片; 形成在n型晶片的第一表面上的p型外延层，具有第一元件的p型外延晶片存储电荷; 和在p型外延层中形成的n阱，n阱具有存储电荷的第二元素; 其中n型晶片被正偏压以吸引p型外延层中的过量少数载流子。还描述了一种提高集成电路中的辐射抗扰度的方法。

40. 发明授权

US08981491B1 Memory array having improved radiation immunity 有权
标题翻译：具有改善的辐射抗扰性的存储阵列
公开(公告)号：US08981491B1
公开(公告)日：2015-03-17
申请号：US13439706
申请日：2012-04-04
申请人： Michael J. Hart , James Karp
发明人： Michael J. Hart , James Karp
IPC分类号： H01L27/085
CPC分类号： H01L27/0207 , G11C5/005 , G11C11/4125 , H01L27/1104
摘要： A memory array having improved radiation immunity is described. The memory array comprises a plurality of memory elements, each memory element having an p-type transistor formed in an n-type region; and a plurality of p-wells, each p-well having an n-type transistor coupled to a corresponding p-type transistor to form a memory element of the plurality of memory elements; wherein each p-well provides a p-n junction to dissipate minority charge in a portion of the n-type region occupied by a corresponding p-type transistor and associated with at least two adjacent memory elements. A method of implementing a memory array is also described.
摘要翻译：描述了具有改善的辐射抗扰性的存储器阵列。存储器阵列包括多个存储元件，每个存储元件具有形成在n型区域中的p型晶体管; 和多个p阱，每个p阱具有耦合到相应的p型晶体管的n型晶体管，以形成多个存储元件的存储元件; 其中每个p阱提供p-n结以消散由相应的p型晶体管占据并与至少两个相邻的存储元件相关联的n型区域的一部分中的少数电荷。还描述了实现存储器阵列的方法。

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