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31. 发明授权

US08797820B2 Soft breakdown mode, low voltage, low power antifuse-based non-volatile memory cell 有权
标题翻译：软击穿模式，低电压，低功耗基于反熔丝的非易失性存储单元
公开(公告)号：US08797820B2
公开(公告)日：2014-08-05
申请号：US13563665
申请日：2012-07-31
申请人： Jack Z. Peng , David Fong
发明人： Jack Z. Peng , David Fong
IPC分类号： G11C17/18 , G11C17/16
CPC分类号： G11C17/165 , G11C17/16 , G11C17/18
摘要： A non-volatile memory cell using two transistors, a bit select and a sense device and an antifuse device. The antifuse device is implemented with a field-effect transistor operated to behave like an antifuse when the cell is selected and a modest programming voltage under 5.5 volts and a current under 5-μA is applied. Only a soft breakdown is needed in the thin gate oxide because a local sense transistor is used during read operations to detect the programming and amplify it for column sense amplifiers. Reading also only requires low voltages of about one volt.
摘要翻译：使用两个晶体管的非易失性存储单元，位选择和感测装置以及反熔丝装置。反熔断器件采用场效应晶体管来实现，当选择电池时，该场效应晶体管的工作方式就像反熔丝，并且施加5.5伏以下的适当编程电压和5-μA以下的电流。因为在读取操作期间使用局部检测晶体管来检测编程并将其放大为列读出放大器，所以在薄栅氧化层中仅需要软的击穿。读数也只需要约一伏特的低电压。

32. 发明申请

US20130208525A1 SOFT BREAKDOWN MODE, LOW VOLTAGE, LOW POWER ANTIFUSE-BASED NON-VOLATILE MEMORY CELL 有权
标题翻译：软断开模式，低电压，低功耗抗体基于非易失性存储器单元
公开(公告)号：US20130208525A1
公开(公告)日：2013-08-15
申请号：US13563665
申请日：2012-07-31
申请人： Jack Z. Peng , David Fong
发明人： Jack Z. Peng , David Fong
IPC分类号： G11C17/16
CPC分类号： G11C17/165 , G11C17/16 , G11C17/18
摘要： A non-volatile memory cell uses two transistors only, a bit select and a sense device. Each cell further comprises an antifuse device implemented, for example, with a field-effect transistor operated to behave like an antifuse when the cell is selected and a modest programming voltage under 5.5 volts and under 5-μA is applied. Only a soft breakdown is needed in the thin gate oxide because a local sense transistor is used during read operations to detect the programming and amplify it for column sense amplifiers. Reading also only requires low voltages of about one volt.
摘要翻译：非易失性存储单元仅使用两个晶体管，位选择和感测器件。每个单元进一步包括反熔丝装置，例如，当选择单元时，实施了场效应晶体管，该场效应晶体管被操作为表现得像反熔丝，并且施加了5.5伏和5-μA以下的适度的编程电压。因为在读取操作期间使用局部检测晶体管来检测编程并将其放大为列读出放大器，所以在薄栅氧化层中仅需要软的击穿。读数也只需要约一伏特的低电压。

33. 发明授权

US08079027B2 Programming language translation systems and methods 有权
标题翻译：编程语言翻译系统和方法
公开(公告)号：US08079027B2
公开(公告)日：2011-12-13
申请号：US11530043
申请日：2006-09-08
申请人： David Fong , Stanley John , Zheng (Joy) Zhang , Qi (Christine) Chen
发明人： David Fong , Stanley John , Zheng (Joy) Zhang , Qi (Christine) Chen
IPC分类号： G06F9/44 , G06F9/45
CPC分类号： G06F8/51
摘要： Included are embodiments of a description language program stored in a computing device for updating a first version of a computer program. In at least one embodiment, the first version of the computer program is written in a universal format and the program includes logic configured to receive an updated version of the computer program. Other embodiments include logic configured to retrieve the first version of the computer program and logic configured to translate the updated version of the computer program from a proprietary format to the universal format. Still other embodiments include logic configured to utilize at least one tag to compare the translated updated version of the computer program with the first version of the computer program.
摘要翻译：包括存储在用于更新计算机程序的第一版本的计算设备中的描述语言程序的实施例。在至少一个实施例中，计算机程序的第一版本以通用格式编写，并且程序包括被配置为接收计算机程序的更新版本的逻辑。其他实施例包括被配置为检索计算机程序的第一版本的逻辑和被配置为将计算机程序的更新版本从专用格式转换为通用格式的逻辑。其他实施例包括被配置为利用至少一个标签来比较计算机程序的翻译的更新版本与计算机程序的第一版本的逻辑。

34. 发明授权

US07907465B2 Electrically programmable fuse bit 有权
标题翻译：电可编程熔丝位
公开(公告)号：US07907465B2
公开(公告)日：2011-03-15
申请号：US12577084
申请日：2009-10-09
申请人： Jack Z. Peng , David Fong , Glen A. Rosendale
发明人： Jack Z. Peng , David Fong , Glen A. Rosendale
IPC分类号： G11C17/18 , G11C17/00 , H01H85/00
CPC分类号： G11C17/18
摘要： One-time programmable (OTP) nonvolatile fuse memory cells are disclosed that do not require decoding or addressing for reading their data content. Each fuse memory cell has its content latched at its output and available at all times and can be used, for example, for code storage memories, serial configuration memories, and as individual fuse bits for ID (identification), trimming, and other post-fabrication System-on-Chip (SoC) customization needs. Means are also provided for temporary data storage for design testing, etc. In alternative embodiments, using two differentially programmed fuses in a single memory cell, the selection and programming circuitry are merged.
摘要翻译：公开了一次性可编程（OTP）非易失性熔丝存储器单元，其不需要用于读取其数据内容的解码或寻址。每个保险丝存储单元的内容在其输出端被锁存并且始终可用，并且可以用于例如代码存储存储器，串行配置存储器，以及作为用于ID（识别），修整和其他后期处理的单个保险丝位。制造片上系统（SoC）定制需求。还提供了用于设计测试等的临时数据存储的手段。在替代实施例中，在单个存储器单元中使用两个差分编程的熔丝，合并选择和编程电路。

35. 发明申请

US20100091545A1 ELECTICALLY PROGRAMMABLE FUSE BIT 有权
标题翻译：可选可编程保险丝位
公开(公告)号：US20100091545A1
公开(公告)日：2010-04-15
申请号：US12577084
申请日：2009-10-09
申请人： Jack Z. Peng , David Fong , Glen A. Rosendale
发明人： Jack Z. Peng , David Fong , Glen A. Rosendale
IPC分类号： G11C17/16 , G11C7/10 , G11C8/00
CPC分类号： G11C17/18
摘要： One-time programmable (OTP) nonvolatile fuse memory cells are disclosed that do not require decoding or addressing for reading their data content. Each fuse memory cell has its content latched at its output and available at all times and can be used, for example, for code storage memories, serial configuration memories, and as individual fuse bits for ID (identification), trimming, and other post-fabrication System-on-Chip (SoC) customization needs. Means are also provided for temporary data storage for design testing, etc. In alternative embodiments, using two differentially programmed fuses in a single memory cell, the selection and programming circuitry are merged.
摘要翻译：公开了一次性可编程（OTP）非易失性熔丝存储器单元，其不需要用于读取其数据内容的解码或寻址。每个保险丝存储单元的内容在其输出端被锁存并且始终可用，并且可以用于例如代码存储存储器，串行配置存储器，以及作为用于ID（识别），修整和其他后期处理的单个保险丝位。制造片上系统（SoC）定制需求。还提供了用于设计测试等的临时数据存储的手段。在替代实施例中，在单个存储器单元中使用两个差分编程的熔丝，合并选择和编程电路。

36. 发明授权

US07506305B2 Dynamic contextual helper user interface 有权
标题翻译：动态上下文帮助用户界面
公开(公告)号：US07506305B2
公开(公告)日：2009-03-17
申请号：US10618919
申请日：2003-07-14
申请人： Aaron Cornelius , David Fong , Jeremy Mercer , Giovanni Stallo
发明人： Aaron Cornelius , David Fong , Jeremy Mercer , Giovanni Stallo
IPC分类号： G06F9/44 , G06F3/00
CPC分类号： G06F3/0481 , G06F9/453 , G06F11/327
摘要： A visual design surface that identifies configuration errors to a user in an inconspicuous manner is disclosed. Shapes representing software artifacts are arranged on the design surface. Each shape may have one or more configuration parameter. The parameters associated with each shape are analyzed to locate configuration errors. When an error is identified, an error icon is placed next to the shape. The user may select the icon and be presented with one or more proposed solutions.
摘要翻译：公开了以不显眼的方式识别用户的配置错误的视觉设计表面。表示软件工件的形状被布置在设计表面上。每个形状可以具有一个或多个配置参数。分析与每个形状相关的参数以定位配置错误。当识别出错误时，会在形状旁边放置一个错误图标。用户可以选择图标并呈现一个或多个提出的解决方案。

37. 发明申请

US20090039897A1 Systems and Methods for Scan Chain Testing Using Analog Signals 审中-公开
标题翻译：使用模拟信号进行扫描链测试的系统和方法
公开(公告)号：US20090039897A1
公开(公告)日：2009-02-12
申请号：US11837128
申请日：2007-08-10
申请人： David Fong
发明人： David Fong
IPC分类号： G01R31/00
CPC分类号： G01R31/3167 , G01R31/318547 , G01R31/31921
摘要： Systems and methods for utilizing analog signals for scan chain testing of a device are disclosed. At least one embodiment includes a method for utilizing an analog signal for scan chain testing of a device comprising: passing digital input signals from a test module into a signal disassembler configured to divide the digital input signals into bits corresponding to each of the digital input signals, passing the bits into a digital-to-analog converter configured to generate an analog input signal, passing the analog input signal to an analog-to-digital converter within the device under test to obtain bits corresponding to each of the digital input signals, passing the bits as inputs to scan chains within the device under test, and utilizing the bits to test the device under test by the scan chains.
摘要翻译：公开了用于利用模拟信号进行设备扫描链测试的系统和方法。至少一个实施例包括利用模拟信号进行装置的扫描链测试的方法，包括：将来自测试模块的数字输入信号传送到信号分解器，该信号分解器配置成将数字输入信号分成与每个数字输入信号相对应的位将所述位传送到被配置为产生模拟输入信号的数模转换器，将所述模拟输入信号传递到被测器件内的模数转换器，以获得与每个所述数字输入信号相对应的位，将这些位作为输入传送到被测器件内的扫描链，并利用这些位来测试被扫描链测试的器件。

38. 发明申请

US20080098366A1 Assertion Tester 审中-公开
标题翻译：断言测试仪
公开(公告)号：US20080098366A1
公开(公告)日：2008-04-24
申请号：US11539663
申请日：2006-10-09
申请人： David Fong , Stanley John , Zheng (Joy) Zhang , Qi (Christine) Chen
发明人： David Fong , Stanley John , Zheng (Joy) Zhang , Qi (Christine) Chen
IPC分类号： G06F9/44 , G06F9/45
CPC分类号： G06F17/5022 , G06F17/505
摘要： Included is a method for testing an assertion written for a logic program that can be simulated in a simulation program. Embodiments of the method include receiving the assertion independent from the logic program and independent from the simulation program, wherein the assertion includes at least one variable from the simulation program and determining the at least one variable in the assertion. Embodiments of the method also include testing the assertion independent from the logic program and the simulation program, wherein testing the assertion includes testing the assertion with at least one value for the at least one variable and determining at least one violation of the assertion.
摘要翻译：包括一种用于测试为在仿真程序中可以模拟的逻辑程序写入的断言的方法。该方法的实施例包括独立于逻辑程序接收断言并且独立于模拟程序，其中断言包括来自模拟程序的至少一个变量并且确定断言中的至少一个变量。该方法的实施例还包括独立于逻辑程序和仿真程序测试断言，其中测试该断言包括用至少一个变量的至少一个值测试该断言，并确定至少一次违反该断言。

39. 发明申请

US20070294647A1 Transferring software assertions to hardware design language code 审中-公开
标题翻译：将软件断言转移到硬件设计语言代码
公开(公告)号：US20070294647A1
公开(公告)日：2007-12-20
申请号：US11445013
申请日：2006-06-01
申请人： David Fong , Zheng (Joy) Zhang , Qi (Christine) Chen
发明人： David Fong , Zheng (Joy) Zhang , Qi (Christine) Chen
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5045
摘要： Systems and methods are disclosed for transferring assertions in a software programming language source file to an HDL source file. In one such method, a first source file contains source code in a software programming language and a second source file contains HDL source code translated from the source code in the first source file. The second source file excludes assertions translated from the source code in the first source file. This method comprises the steps of: reading a software assertion from from the first source file; locating a second block within the second source file, where the second block corresponds to a first block that contains the software assertion; mapping the software assertion to a hardware assertion expressed in the HDL; determining a location within the second block for insertion of the hardware assertion; and inserting the hardware assertion at the determined location within the second source file.
摘要翻译：公开了用于将软件编程语言源文件中的断言传送到HDL源文件的系统和方法。在一种这样的方法中，第一源文件包含软件编程语言的源代码，第二源文件包含从第一源文件中的源代码翻译的HDL源代码。第二个源文件排除了从第一个源文件中的源代码翻译的断言。该方法包括以下步骤：从第一源文件读取软件断言; 将第二块定位在第二源文件中，其中第二块对应于包含软件断言的第一块; 将软件断言映射到HDL中表示的硬件断言; 确定所述第二块内的位置以插入所述硬件断言; 以及将所述硬件断言插入所述第二源文件中的所确定的位置。

40. 发明申请

US20070206417A1 MEMORY TRANSISTOR GATE OXIDE STRESS RELEASE AND IMPROVED RELIABILITY 有权
公开(公告)号：US20070206417A1
公开(公告)日：2007-09-06
申请号：US11368576
申请日：2006-03-06
申请人： David Fong , Jianguo Wang , Jack Peng , Harry Luan
发明人： David Fong , Jianguo Wang , Jack Peng , Harry Luan
IPC分类号： G11C16/06 , G11C11/34
CPC分类号： G11C7/08 , G11C7/18 , G11C16/28 , G11C2207/061 , G11C2207/065
摘要： Methods and apparatus for decreasing oxide stress and increasing reliability of memory transistors are disclosed. Duration and frequency of exposure of memory transistor gates to read signals are significantly reduced. In some embodiments, after a short read cycle, the content of the memory cell is latched and maintained as long as the subsequent read attempts are directed to the same memory cell. In these embodiments the read cycle need only be long enough to latch the memory content of the cell, and as long as the subsequent read attempts target the same memory cell the latched value will be used instead of repeating the read process.

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