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    • 31. 发明申请
    • MULTI-GRANULARITY PARALLEL STORAGE SYSTEM
    • 多粒度并行存储系统
    • US20140344515A1
    • 2014-11-20
    • US14117295
    • 2011-12-31
    • Donglin WangZijun LiuXiaojun XueXing ZhangZhiwei ZhangShaolin Xie
    • Donglin WangZijun LiuXiaojun XueXing ZhangZhiwei ZhangShaolin Xie
    • G11C7/10G11C11/406G11C21/00
    • G11C7/1072G06F3/0601G06F9/3895G06F12/02G06F12/0607G11C11/40615G11C21/00
    • A multi-granularity parallel storage system including a plurality of memories, a shift generator, an address increment lookup unit, an address shifter, a row address generator, and a plurality of address adders. The shift generator is configured to generate a shift value. The address increment lookup unit is configured to generate input data for the address shifter. The address shifter is configured to cyclically shift the input data rightward by Shift elements and then output the shifted data. The row address generator is configured to generate a row address RowAddr and input the generated row address RowAddr to the other input terminal of each address adder. Each address adder is configured to perform a non-sign addition of the input data at the two input terminals to obtain a read/write (R/W) address for one of the memories and input the R/W address to an address input terminal of the memory.
    • 包括多个存储器,移位发生器,地址增量查找单元,地址移位器,行地址生成器和多个地址加法器的多粒度并行存储系统。 移位发生器被配置为产生移位值。 地址增量查找单元被配置为生成地址移位器的输入数据。 地址移位器被配置为通过Shift元素向右循环移位输入数据,然后输出移位的数据。 行地址生成器被配置为生成行地址RowAddr,并将生成的行地址RowAddr输入到每个地址加法器的另一个输入端。 每个地址加法器被配置为在两个输入端子处执行输入数据的非符号相加以获得其中一个存储器的读/写(R / W)地址,并将R / W地址输入到地址输入端 的记忆。
    • 32. 发明申请
    • Facilitating the Use of Selectable Elements on Touch Screen
    • 促进在触摸屏上使用可选元素
    • US20140019908A1
    • 2014-01-16
    • US13993128
    • 2012-01-03
    • Xing ZhangNingxin HuXiaoqing Zhao
    • Xing ZhangNingxin HuXiaoqing Zhao
    • G06F3/0488
    • G06F3/0488G06F3/04886
    • When the user touches a touch selectable element, the appearance of the computer recognized selected element may be changed so that the user can confirm that the element is, in fact, the element the user intended to select. If it is not, in some embodiments, the user can slide the user's finger to the correct element and, again, that element may be modified in a way to indicate to the user which element has now been selected. When the user removes the user's finger from the touch selectable element, in some embodiments, the element is then selected. Also, the user, in some embodiments, can touch blank areas of the display screen to reveal which elements on the display screen are touch selectable elements.
    • 当用户触摸可触摸可选元素时,可以改变识别的所选元件的外观,使得用户可以确认元件实际上是用户想要选择的元件。 如果不是,在一些实施例中,用户可以将用户的手指滑动到正确的元件,并且再次可以以向用户指示哪个元素已被选择的方式进行修改。 当用户从触摸可选元素移除用户的手指时,在一些实施例中,然后选择该元素。 此外,在一些实施例中,用户可以触摸显示屏幕的空白区域,以显示显示屏幕上的哪些元素是可触摸的可选元素。
    • 33. 发明申请
    • INTERFACE TREATMENT METHOD FOR GERMANIUM-BASED DEVICE
    • 用于基于锗的器件的接口处理方法
    • US20130309875A1
    • 2013-11-21
    • US13702562
    • 2012-06-14
    • Ru HuangMin LiXia AnMing LiMeng LinXing Zhang
    • Ru HuangMin LiXia AnMing LiMeng LinXing Zhang
    • H01L21/02
    • H01L21/02052H01L21/306
    • Disclosed herein is an interface treatment method for germanium-based device, which belongs to the field of manufacturing technologies of ultra large scaled integrated (ULSI) circuits. In the method, the natural oxide layer on ther surface of the germanium-based substrate is removed by using a concentrated hydrochloric acid solution having a mass percentage concentration of 15%˜36%, and dangling bonds of the surface are performed a passivation treatment by using a diluted hydrochloric acid solution having a mass percentage concentration of 5%˜10% so as to form a stable passivation layer on the surface. This method makes a good foundation for depositing a high-K (high dielectric constant) gate dielectric on the surface of the germanium-based substrate after cleaning and passivating, enhances quality of the interface between the gate dielectric and the substrate, and improves the electrical performance of germanium-based MOS device.
    • 本文公开了一种锗系器件的接口处理方法,属于超大规模集成(ULSI)电路制造技术领域。 在该方法中,通过使用质量百分比浓度为15%〜36%的浓盐酸溶液除去锗基底板的表面上的天然氧化物层,并且通过以下方式进行钝化处理: 使用质量百分比浓度为5%〜10%的稀盐酸溶液,以在表面上形成稳定的钝化层。 该方法为清洗和钝化后在锗基基板表面上沉积高K(高介电常数)栅极电介质提供了良好的基础,提高了栅极电介质和基板之间界面的质量,改善了电气 锗系MOS器件的性能。
    • 34. 发明授权
    • Semiconductor device and method for fabricating the same
    • 半导体装置及其制造方法
    • US08541847B2
    • 2013-09-24
    • US13201618
    • 2010-09-25
    • Xia AnYue GuoQuanxin YunRu HuangXing Zhang
    • Xia AnYue GuoQuanxin YunRu HuangXing Zhang
    • H01L27/088H01L21/336
    • H01L21/26506H01L21/26513H01L21/823807H01L29/16H01L29/6659H01L29/7833H01L29/7848
    • The present invention provides a semiconductor device and a method for fabricating the same, wherein the method comprises: providing a germanium-based semiconductor substrate having a plurality of active regions and device isolation regions between the plurality of the active regions, wherein a gate dielectric layer and a gate over the gate dielectric layer are provided on the active regions, and the active regions include source and drain extension regions and deep source and drain regions; performing a first ion implantation process with respect to the source and drain extension regions, wherein the ions implanted in the first ion implantation process include silicon or carbon; performing a second ion implantation process with respect to the source and drain extension regions; performing a third ion implantation process with respect to the deep source and drain regions; performing an annealing process with respect to the germanium-based semiconductor substrate which has been subjected to the third ion implantation process. According to the method for fabricating a semiconductor device, through the implantation of silicon impurities, appropriate stress may be introduced into the germanium channel effectively by the mismatch of lattices in the source and drain regions, so that the mobility of electrons in the channel is enhanced and the performance of the device is improved.
    • 本发明提供一种半导体器件及其制造方法,其中该方法包括:在多个有源区之间提供具有多个有源区和器件隔离区的锗基半导体衬底,其中栅介电层 并且栅极电介质层上的栅极设置在有源区上,有源区包括源极和漏极延伸区以及深的源极和漏极区; 对源极和漏极延伸区域执行第一离子注入工艺,其中在第一离子注入工艺中注入的离子包括硅或碳; 对源极和漏极延伸区域执行第二离子注入工艺; 相对于深源极和漏极区域执行第三离子注入工艺; 对已进行第三离子注入工艺的锗基半导体衬底进行退火处理。 根据制造半导体器件的方法,通过硅杂质的注入,可以通过源极和漏极区域中的晶格失配有效地将合适的应力引入锗通道中,使得通道中电子的迁移率增强 并提高了设备​​的性能。
    • 36. 发明申请
    • FABRICATION METHOD OF GERMANIUM-BASED N-TYPE SCHOTTKY FIELD EFFECT TRANSISTOR
    • 基于锗的N型肖特基效应晶体管的制造方法
    • US20120289004A1
    • 2012-11-15
    • US13390755
    • 2011-10-14
    • Ru HuangZhiqiang LiYue GuoXia AnQuanxin YunYinglong HuangXing Zhang
    • Ru HuangZhiqiang LiYue GuoXia AnQuanxin YunYinglong HuangXing Zhang
    • H01L21/336
    • H01L29/0895H01L29/41783H01L29/517H01L29/66643H01L29/78
    • The present invention discloses a fabrication method of a Ge-based N-type Schottky field effect transistor and relates to a filed of ultra-large-scaled integrated circuit fabrication process. The present invention forms a thin high K dielectric layer between a substrate and a metal source/drain. The thin layer on one hand may block the electron wave function of metal from inducing an MIGS interface state in the semiconductor forbidden band, on the other hand may passivate the dangling bonds at the interface of Ge. Meanwhile, since the insulating dielectric layer has a very thin thickness, and electrons can substantially pass freely, the parasitic resistances of the source and the drain are not significantly increased. The method can weaken the Fermi level pinning effect, cause the Fermi energy level close to the position of the conduction band of Ge and lower the electron barrier, thereby increasing the current switching ratio of the Ge-based Schottky transistor and improve the performance of the NMOS device.
    • 本发明公开了一种Ge系N型肖特基场效应晶体管的制造方法,涉及超大规模集成电路制造工艺。 本发明在衬底和金属源极/漏极之间形成薄的高K电介质层。 薄层一方面可能阻止金属的电子波函数在半导体禁带中引起MIGS界面态,另一方面可能会钝化Ge界面处的悬挂键。 同时,由于绝缘介电层具有非常薄的厚度,并且电子可以基本上自由地通过,所以源极和漏极的寄生电阻不会显着增加。 该方法可以削弱费米能级钉扎效应,使费米能级接近Ge导带的位置,降低电子势垒,从而提高Ge基肖特基晶体管的电流开关比,提高Ge NMOS器件。
    • 38. 发明申请
    • METHOD FOR INTRODUCING CHANNEL STRESS AND FIELD EFFECT TRANSISTOR FABRICATED BY THE SAME
    • 引入通道应力和场效应晶体管的方法
    • US20120032239A1
    • 2012-02-09
    • US13131602
    • 2011-04-01
    • Ru HuangQuanxin YunXia AnXing Zhang
    • Ru HuangQuanxin YunXia AnXing Zhang
    • H01L29/772H01L21/336
    • H01L29/7848H01L29/6653H01L29/66636H01L29/7833H01L29/7843
    • The present invention relates to CMOS ultra large scale integrated circuits, and provides a method for introducing channel stress and a field effect transistor fabricated by the same. According to the present invention, a strained dielectric layer is interposed between source/drain regions and a substrate of a field effect transistor, and a strain is induced in a channel by the strained dielectric layer which directly contacts the substrate, so as to improve a carrier mobility of the channel and a performance of the device. The specific effects of the invention include: a tensile strain may be induced in the channel by using the strained dielectric layer having a tensile strain in order to increase an electron mobility of the channel; a compressive strain may be induced in the channel by using the strained dielectric layer having a compressive strain in order to increase a hole mobility of the channel. According to the invention, not only an effectiveness of the introduction of channel stress is ensued, but the device structure of the field effect transistor is also improved fundamentally, so that a capability for suppressing a short channel effect of the device is increased.
    • 本发明涉及CMOS超大规模集成电路,并且提供了一种引入沟道应力的方法和由其制造的场效应晶体管。 根据本发明,应变电介质层介于源极/漏极区域和场效应晶体管的衬底之间,并且通过直接接触衬底的应变介电层在沟道中诱发应变,从而改善 信道的载波移动性和设备的性能。 本发明的具体效果包括:通过使用具有拉伸应变的应变电介质层,可以在沟道中诱发拉伸应变,以增加通道的电子迁移率; 可以通过使用具有压缩应变的应变电介质层在沟道中诱发压缩应变,以增加通道的空穴迁移率。 根据本发明,不仅引入通道应力的有效性,而且基本上也提高了场效应晶体管的器件结构,从而增加了抑制器件的短沟道效应的能力。
    • 40. 发明授权
    • Interlaced video motion estimation
    • 隔行扫描视频运动估计
    • US06914938B2
    • 2005-07-05
    • US10173896
    • 2002-06-18
    • Jian ZhangReji MathewXing Zhang
    • Jian ZhangReji MathewXing Zhang
    • H04N20060101H04N5/14H04N7/12
    • H04N5/144H04N19/105H04N19/147H04N19/16H04N19/172H04N19/533
    • A method for determining motion vectors in an interlaced video coding system for coding images comprising interlaced odd and even field. The method (30) includes selecting (32) a current odd field block and a current even field block that respectively comprise odd and even fields of a selected current image block. Differences are identified (33) and thereafter, suitable best matching odd and even field matching reference blocks are determined (34). From the suitable best matching odd and even field matching reference blocks a reduced field search area is provided (35) that is used to complete further searching (36) and selection of field motion vectors (38). Pseudo-frame motion vector selection is also conducted (43) and a preferred motion vector is selected (44) from either a field motion vector pair or pseudo-frame motion vector.
    • 一种用于确定用于对包含隔行的奇数和偶数场的图像进行编码的隔行视频编码系统中的运动矢量的方法。 方法(30)包括选择(32)分别包括所选当前图像块的奇数和偶数场的当前奇数场块和当前偶数场块。 鉴别差异(33),此后确定合适的最佳匹配奇数和偶数场匹配参考块(34)。 从合适的最佳匹配奇数和偶数场匹配参考块提供了一个减小的场搜索区域(35),用于完成进一步的搜索(36)和场运动矢量(38)的选择。 还执行伪帧运动矢量选择(43),并且从场运动矢量对或伪帧运动矢量中选择(44)优选的运动矢量。